3D C technology

Pouya Dormiani
Christopher Lucas
hat is a 3D C?
"Stacked 2D (Conventional) Cs Could be Heterogeneous.
otivation
nterconnect structures increasingly consume more of the power and
delay budgets in modern design
Plausible solution: increase the number of "nearest neighbors seen
by each transistor by using 3D C design
Smaller wire cross-sections, smaller wire pitch and longer lines to
traverse larger chips increase RC delay.
RC delay is increasingly becoming the dominant factor
At 250 nm Cu was introduced alleviate the adverse effect of
increasing interconnect delay.
130 nm technology node, substantial interconnect delays will result.
3D Fabrication Technologies
any options available for realization of 3D circuits
Choice of Fabrication depends on requirements of
Circuit System
Beam
RecrystaIIization
Processed Wafer
Bonding
SiIicon EpitaxiaI
Growth
SoIid Phase
CrystaIIization
Deposit polysillicon
and fabricate TFTs
-not practial for 3D circuits
due to high temp of melting
polysillicon
-Suffers from Low carrier
mobility
-However high perfomance
TFT's
have been fabricated using
low temp processing which
can be used to implement 3D
circuits
Bond two fully
processed wafers
together.
-Similar Electrical Properties
on all devices
-ndependent of temp. since
all chips are fabricated then
bonded
-Good for applications where
chips do independent
processing
-However Lack of
Precision(alignemnt) restricts
interchip communication to
global metal lines.
Epitaxially grow a
single cystal Si
-High temperatures cause
siginificant cause significant
degradation in quality of
devices on lower layers
-Process not yet
manufacturable
Low Temp
alternative to SE.
-Offers Flexibilty of creating
multiple layers
-Compatible with current
processing environments
-Useful for Stacked SRA
and EEPRO cells
Performance Characteristics
Timing
Energy
ith shorter interconnects in 3D Cs, both switching
energy and cycle time are expected to be reduced
Timing
n current technologies, timing is
interconnect driven.
Reducing interconnect length in
designs can dramatically reduce
RC delays and increase chip
performance
The graph below shows the
results of a reduction in wire
length due to 3D routing
Discussed more in detail later in
the slides
Energy performance
ire length reduction has an impact on
the cycle time and the energy dissipation
Energy dissipation decreases with the
number of layers used in the design
Following graphs are based on the 3D tool
described later in the presentation
Energy performance graphs
Design tools for 3D-C design
Demand for EDA tools
As the technology matures, designers will
want to exploit this design area
Current tool-chains
ostly academic
e will discuss a tool from T
3D Standard Cell tool Design
3D Cell Placement
Placement by min-cut partitioning
3D Global Routing
nter-wafer vias
Circuit layout management
AGC
3D Standard Cell Placement
Natural to think of a 3D
integrated circuit as
being partitioned into
device layers or planes
in cut part-itioning
along the 3
rd
dimension
is same as minimizing
vias
Total wire length vs. Vias
Can trade off increased total wire length for fewer inter-plane
vias by varying the point at which the design is partitioned
into planes
Plane assignment performed prior to detailed placement
Yields smaller number of vias, but greater overall wire length
Total wire length vs. Vias (Cont)
Plane assignment not made until detailed placement
stage
Yields smaller total wire length but greater number of vias
ntro to Global Routing
Overview
Global Routing involves generating a "loose
route for each net.
Assigns a list of routing regions to a net without
actually specifying the geometrical layout of the
wires.
Followed by detailed routing
Finds the actual geometrical shape of the net
within the assigned routing regions.
Usually either sequential or hierarchical
algorithms
llustration of routing areas
x
z
y
x
z
y
Detailed routing of net when
routing areas are known
Hierarchical Global Routing
Tool uses a hierarchical global routing
algorithm
Based on nteger programming and Steiner
trees
nteger programming approach still too slow
for size of problem and complexity (NP-hard)
Hierarchical routing methods break down the
integer program into pieces small enough to
be solved exactly
2D Global Routing
A 2D Hierarchical global router works by recursively
bisecting the routing substrate.
ires within a Region are fully contained or terminate at a
pin on the region boundry.
At each partitioning step the pins on the side of the
routing region is allocated to one of the two subregions.
ires Connect cells on both sides of the partition line.
These are cut by the partition and for each a pin is inserted
into the side of the partition
Once complete, the results can be fed to a detailed
router or switch box router (A switchbox is a rectangular
area bounded on all sides by blocks)
llustration of Bisection
Extending to 3D
Routing in 3D consists of routing a set of aligned
congruent routing regions on adjacent wafers.
ires can enter from any of the sides of the routing region in
addition to its top and bottom
3D router must consider routing on each of the layers in
addition to the placement of the inter-waver vias
Basis idea is: You connect a inter-waver via to the port
you are trying to connect to, and route the wire to that via
on the 2D plane.
All we need now is enough area in the 2D routing space to route
to the appropriate via
3D Routing Results
Percentage Of 2D
TotaI wire Length
Minimizing for Wire Length:
2 Layers ~ 28%
5 Layers ~ 51 %
Minimizing for via count:
2 Layers ~ 7%
5 Layers ~ 17%
3D-AGC
AGC is an open source layout editor developed at UC
Berkeley
3D-AGC is an extension to AGC by providing
support for ulti-layer C design
hat's different
New Command :bond
Bonds existing 2D Cs and places inter-layer Vias in the design
file
Once Two layers are bonded they are treated as one entity
Concerns in 3D circuit
Thermal ssues in 3D-circuits
E
Reliability ssues
Thermal Issues in 3D Circuits
Thermal EIIects dramatically impact interconnect and device reliability in 2D
circuits
Due to reduction in chip size oI a 3D implementation, 3D circuits exhibit a sharp
increase in power density
Analysis oI Thermal problems in 3D is necessary to evaluate thermal robustness oI
diIIerent 3D technology and design options.
Heat Flow in 2D
Heat generated arises due to switching
n 2D circuits we have only one layer of Si to
consider.
Heat Flow in 3D
ith multi-layer circuits , the upper
layers will also generate a significant
fraction of the heat.
Heat increases linearly with level increase
Heat Dissipation
All active layers will be insulated from each other by layers of dielectrics
ith much lower thermal conductivity than Si
Therefore heat dissipation in 3D circuits can accelerate many failure
mechanisms.
eat Dissipation in
WaIer Bonding versus Epitaxial Growth
WaIer Bonding(b)
2X Area Ior heat dissipation
Epitaxial Growth(a)
eat Dissipation in
WaIer Bonding versus Epitaxial Growth
Design 1
Equal Chip Area
Design 2
Equal metal wire pitch
High epitaxial temperature
Temperatures actually higher for Epitaxial second layers
Since the temperature of the second active layer T2 will
Be higher than T1 since T1 is closer to the substrate
and T2 is stuck between insulators
E in 3D Cs
Interconnect Coupling Capacitance and cross talk
Coupling between the top layer metal oI the Iirst active layer and the device on
the second active layer devices is expected
E
nterconnect nductance Effects
Shorter wire lengths help reduce the
inductance
Presence of second substrate close to global
wires might help lower inductance by
providing shorter return paths
Reliability ssues?
Electro thermal and Thermo-mechanical eIIects
between various active layers can inIluence electro-
migration and chip perIormance
Die yield issues may arise due to mismatches
between die yields oI diIIerent layers, which aIIect
net yield oI 3D chips.
mplications on Circuit Design
and Architecture
Buffer nsertion
Layout of Critical Paths
icroprocessor Design
ixed Signal C's
Physical design and Synthesis
Buffer nsertion
Use of buffers in 3D circuits to break up long interconnects
At top layers inverter sizes 450 times min inverter size for the relevant
technology
These top layer buffers require large routing area and can reach up to
10,000 for high performance designs in 100nm technology
ith 3D technology repeaters can be placed on the second layer and
reduce area for the first layer.
Buffer nsertion
ayout oI Critical Paths and
Microprocessor Design
Once again interconnect delay dominates in 2D
design.
ogic blocks on the critical path need to
communicate with each other but due to
placement and desig constraints are placed Iar
away Irom each other.
With a second layer oI Si these devices can be
placed on diIIerent layes oI Si and thus closer to
each other using(VIICs)
In Microprocessor design most critical paths
involve on chip caches on the critical path.
Computational modules which access the cache
are distributed all over the chip while the cache
is in the corner.
Cache can be placed on a second layer and
connected to these modules using (VIICs)
ixed Signal Cs and Physical
Design
Digital signals on chip can couple and interIere with
RF signals
With multiple layers RF portions oI the system can be
separated Irom their digital counterparts.
Physical Design needs to consider the multiple layers
oI Silicon available.
Placement and routing algorithms need to be
modiIied
Conclusion
3D C design is a relief to interconnect
driven C design.
Still many manufacturing and
technological difficulties
Needs strong EDA applications for
automated design