Bi ging K thut Vi x l

Ngnh in t-Vin thng i hc Bch khoa Nng ca H Vit Vit, Khoa CNTT-TVT

Ti liu tham kho [1] K thut vi x l, Vn Th Minh, NXB Gio dc, 1997 [2] K thut vi x l v Lp trnh Assembly cho h vi x l, Xun Tin, NXB Khoa hc & k thut, 2001

Chng 1
1.1 Cc h thng s
- H thp phn

- H nh phn - H thp lc phn

1.2 Cc h thng m ho
- ASCII

- BCD

1.3 Cc linh kin in t s c bn

- Cc cng logic: AND, OR, XOR,NOT - Cc b gii m

1.1 Cc h thng s

H m thp phn (Decimal) Cn gi l h m c s mi

(V c qu t ngi c chn ngn tay hoc mi mt ngn chn?)

Dng mi k hiu: 1,2,3,4,5,6,7,8,9,0 V d:1.1: Ba nghn Chn trm By mi Tm 3978 = 3x103 + 9x102 + 7x101 + 8x100 = 3000 + 900 + 70 + 8

1.1 Cc h thng s

H m nh phn (Binary) Cn gi l H m c s hai S dng hai k hiu (bit): 0 v 1

(Cc h thng in t s ch s dng hai mc in p?)

Kch c, LSB, MSB ca s nh phn S nh phn khng du (Unsigned) S nh phn c du (S b hai)

S nh phn

Mi k hiu 0 hoc 1 c gi l 1 Bit (Binary Digit- Ch s nh phn) Kch c ca mt s nh phn l s bit ca n MSB (Most Significant Bit): Bit st tri LSB (Least Significant Bit): Bit st phi

V d 1.1: 1010101010101010
MSB LSB

l mt s nh phn 16-bit

S nh phn khng du

Ch biu din c cc gi tr khng m (>= 0) Vi n-bit c th biu din cc gi tr t 0 n 2n 1 V d 1.3: Gi tr V ca s nh phn khng du 1101 c tnh:
V(1101) = 1x23 + 1x22 + 0x21 + 1x20 = 8 + 4 + 0 + 1 = 13

S nh phn khng du

Tng qut: Nu s nh phn N n-bit: N = b( n-1) b( n-2) . b1 b0 th gi tr V ca n l: V = b(n -1) x 2(n-1)+b (n-2) x2 (n-2)+ + b1 x 21 + b0 x 20

Cc s nh phn khng du 4-bit biu din c cc gi tr t ? n ?

16 gi tr t 0 n 15
Nh phn khng du 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Gi tr thp phn 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

S nh phn khng du

Di gi tri ca cc s khng du 8-bit l [0,255] (unsigned char trong C) Di gi tri ca cc s khng du 16bit l [0,65535] (unsigned int trong C)

Chuyn i thp phn sang nh phn

V d 1.4 Chuyn 25 sang nh phn khng du. Dng phng php chia 2 lin tip Chia 2 Thng s = = = = = 12 6 3 1 0 D s 1 0 0 1 1 LSB

25/2 12/2 6/2 3/2 1/2

MSB

Kt qu l: 11001

S nh phn c du

Biu din c c cc gi tr m Cn gi l S b hai Vi n-bit c th biu din cc gi tr t 2(n-1) n 2(n-1) 1 V d 1.3: Gi tr V ca s nh phn c du 1101 c tnh: V(1101) = 1x23 + 1x22 + 0x21 + 1x20
=8 + 4 + 0 +1 =3

S nh phn c du

Tng qut: Nu s nh phn N n-bit: N = b( n-1) b( n-2) . b1 b0 th gi tr V ca n l: V = b(n -1) x 2(n-1)+b (n-2) x2 (n-2)+ + b1 x 21 + b0 x 20

Cc s nh phn c du 4-bit biu din c cc gi tr t ? n ?

16 gi tr t - 8 n 7
Nh phn c du 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 Gi tr thp phn 0 1 2 3 4 5 6 7 -8 -7 -6

1011
1100 1101 1110 1111

-5
-4 -3 -2 -1

S nh phn c du

Di gi tri ca cc s c du 8-bit l [-128,+127] (char trong C) Di gi tri ca cc s c du 16-bit l [-32768,+32767] (int trong C)

Tm i s (Ly b 2)

Tng ca mt s vi i s ca n bng 0 V d 1.5

i s ca s nh phn c du 10011101? 10011101 01100010 + 1 ------------01100011 S c du (-99) Ly b 1 Cng 1 Kt qu (+99)

Chuyn s thp phn sang nh phn c du

V s dng:Ging nh chuyn thp phn sang nh phn khng du ri thm bit 0 vo st bn tri V d: Chuyn 25 sang nh phn c du: Kt qu: 011011 Vi s m: Chuyn i s sang nh phn c du ri ly b 2

Chuyn s thp phn sang nh phn c du V d 1.6 Chuyn 26 sang nh phn 1. chuyn i s: +26 = 11010 2. a 0 vo st tri: 011010 3. B 1: 100101 4. Cng 1: + 1 -------------26 = 100110

S thp lc phn

Quen gi l s Hexa (Hexadecimal) Cn gi l h m c s mi su S dng 16 k hiu biu din: 0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F Mi k hiu tng ng vi 4-bit Mc ch: Biu din s nh phn dng ngn gn 11110000 = F0 10101010 01010101 Nh phn = = AA 55 Thp lc phn

Mi k hiu tng ng vi 4-bit

Hexa 0 1 2 3 4 5 6 7 Binary 0000 0001 0010 0011 0100 0101 0110 0111 Hexa 8 9 A B C D E F Binary 1000 1001 1010 1011 1100 1101 1110 1111

Chuyn i Hexa & nh phn

V d 1.7 Chuyn s hexa 2F8 v ABBA sang nh phn Thay th mi k hiu hexa bng 4-bit tng ng vi n 2 F 8 0010 1111 1000 A B B A 1010 1011 1011 1010 Kt qu 2F8h = 001011111000b ABBAh = 1010101110111010b

Chuyn i Hexa & nh phn

V d 1.8 Chuyn s nh phn 1100101011111110 sang hexa - Trc ht theo hng t LSB v MSB chia s nh phn thnh cc nhm 4-bit - Sau thay th mi nhm 4-bit bng k hiu hexa tng ng vi n 1100 C 1010 A 1111 F = 1110 E CAFEh

Kt qu: 1100101011111110b

1.2 Cc h thng m ho

ASCII: American Standard Code for Information Interchange. Dng biu din cc k t (characters):
Gm k t hin th c v k t iu khin

Mi k t c biu din bng 8-bit gi l m ASCII ca k t

Cc Cc Cc Cc Cc line ch ci in v thng: A..Z v a..z ch s thp phn: 0,1,,9 du chm cu: ; , . : vn vn k t c bit: $ & @ / { vn vn k t iu khin: carriage return (CR) , feed (LF), beep, vn vn

M ASCII

Vi bng m c sp xp theo trt t tng dn ca m ASCII:

Cc ch s thp phn: 0,1,,9 nm lin tip nhau, ch s 0 c m ASCII l 30h Cc ch ci in:A..Z nm lin tip nhau, ch A c m ASCII l 41h Cc ch ci thng: a..z nm lin tip nhau, ch a c m ASCII l 61h M ASCII ca ch in v ch thng tng ng ch khc nhau bit 5 A: 01000001 B: 01000010 Z: 01011010 a: 01100001 b: 01100010 z: 01111010 32 k t iu khin c xp u bng m (00h n 1Fh)

Bng m ASCII

Bng m ASCII

M BCD

BCD (Binary Coded Decimal) Quen gi l s BCD Dng m ho cc s thp phn bng cc k hiu nh phn Mi ch s thp phn c biu din bng mt t hp 4-bit Cc t hp 4-bit khng s dng gi l cc t hp cm Nhiu linh kin in t s dng m ny (B gii m BCD-LED by on 7447)

Bng m BCD
Thp phn 0 1 2 3 4 5 6 7 BCD 0000 0001 0010 0011 0100 0101 0110 0111 Thp phn 8 9 BCD 1000 1001 1010 1011 1100 1101 1110 1111

M BCD

ng nhm m ho BCD vi vic chuyn i thp phn sang nh phn: V d 1.9: Cho s thp phn 15 M BCD ca n l: 00010101

S nh phn khng du 8-bit tng ng l: 00001111

Bit, Nibble, Byte, Word

Bit: Mt ch s nh phn 0 hoc 1 Nibble: 4-bit (na byte) Byte: 8-bit (Cn gi l Octet) Word (T): 16-bit Double Word (T kp): 32-bit K = 210 = 1024 Kb (kilbit) = 1024 bit = 128 byte KB (kilbyte) = 1024 byte Kbps (Kilobit per second): Kilbit trn giy M = 220 = 1024 K = 1048576 Mb (Mgabit) = 1024 Kb = 1048576 MB (Mgabyte) = 1024 KB = 1048576 G = 230 = 1024 M = 1048576 K Gb (Gigabit) = 1024 Mb = 1048576 GB (Gigabyte) = 1024 MB = 1048576 T=?

bit byte Kb KB

1.3 Cc linh kin in t s c bn

Phn chia linh lin s theo mt tch hp: SSI, MSI, LSI, VLSI

SSI (Small Scale Integration): Vi mch tch hp c nh MSI (Medium Scale Integration): Vi mch tch hp c trung LSI (Large Scale Integration): Vi mch tch hp c ln VLSI (Very Large Scale Integration):Vi mch tch hp c cc ln

SSI: Cc cng logic and, or, xor, not MSI: Cc b gii m, Cc cht, m LSI,VLSI: Cc b vi x l, vi iu khin, DSPs

Cng logic AND

A 1 1 B 1 0 A AND B 1 0
A A AND B

B
Cng AND c th c nhiu hn 2 u vo Trn mt chip c th c nhiu cng AND

0 0

1 0

0 0

Cng logic AND: IC 7408

Cng logic AND: IC 7411

Cng logic OR
A 1 1 0 0 B 1 0 1 0 A OR B 1 1 1 0
A B
Cng OR c th c nhiu hn 2 u vo Trn mt chip c th c nhiu cng OR

A OR B

Cng logic OR: IC 7432

Cng logic XOR

A
1 1 0 0

B
1 0 1 0

A XOR B
0 1 1 0

A B

A XOR B

Cng XOR c th c nhiu hn 2 u vo Trn mt chip c th c nhiu cng XOR

Cng logic NOT

A 1 1 0 NOT A 0
A NOT A

0 1

m 3 trng thi

c 0 1

z HiZ x

c 1 0

z HiZ x

Chip gii m 74138

Chip gii m 74138

Flip Flop kiu D

Flip Flop kiu D

Flip Flop kiu D

Flip Flop kiu D

Cht 8-bit 74373

Cht 8-bit 74573

IC 74244

IC 74244

m 2 chiu 74245

m 2 chiu 74245

What is a microprocessor?

Intels first microprocessor, the 4004, was introduced in 1971. It contained 2300 transistors. Todays Pentium 4 processor, by contrast, contains 55 million transistors. One of the most common tasks microprocessors perform is to serve as the brains inside personal computers, but they deliver intelligence to countless other devices as well. For example, they may give your telephone speed-dial and re-dial options, automatically turn down your homes thermostat at night and make your car safer and more energy efficient.

1971

In 1971, Intels first microprocessor was the 4004. This breakthrough invention powered the Busicom calculator and paved the way for embedding intelligence in inanimate objects as well as the personal computer.

1978

In 1978, a pivotal sale to IBM's new personal computer division made the Intel 8088 the brains of IBM's new hit product-the IBM PC. The 8088's success launched Intel into the ranks of the Fortune 500 companies, and Fortune magazine named the company one of the "Business Triumphs of the Seventies."

1982

Then, in 1982, the 286, also known as the 80286, became the first Intel processor that could run all the software written for its predecessor. This software compatibility remains a cornerstone of Intel's family of microprocessors. Within 6 years of its release, there were an estimated 15 million 286-based PCs around the world.

1989

In 1989, the move to a 486 processor allowed the shift from a command-level computer to pointand-click computing. The Intel 486 processor was the first to offer a built-in math coprocessor, which speeds up computing because it offloads complex math functions from the central processor.

1993

In 1993, the jump to the Pentium processor allowed computers to more easily incorporate "real world" data such as speech, sound, handwriting and photographic images.

1997

In 1997, the 7.5 million-transistor Pentium II processor incorporated Intel MMX technology, which is designed specifically to process video, audio and graphics data efficiently.

With this processor, PC users could

capture, edit and share digital photos with friends and family via the Internet,

edit and add text, music or between-scene transitions to home movies, and,
with a video phone, send video over standard phone lines and the Internet.

1998

In 1998, the Pentium II XeonTM processor was designed to meet the performance requirements of mid-range and higher servers and workstations. The Pentium II Xeon processors featured technical innovations specifically designed for workstations and servers that utilized demanding business applications such as Internet services, corporate data warehousing, digital content creation, and electronic and mechanical design automations.

1999

In 1999, the Intel Celeron processor was designed for the value PC market segment. It provided consumers great performance at an exceptional value, and it delivered excellent performance for uses such as gaming and educational software.

1999

Also in 1999, the Pentium III processor was released and featured 70 new instructions that dramatically enhanced the performance of advanced imaging, 3-D, streaming audio, and video and speech recognition applications. It was designed to significantly enhance Internet experiences, allowing users to do such things as browse through realistic online museums and stores and download high-quality video.

2000

In 2000, users of the newly released Pentium 4 processor could create professional-quality movies, deliver TV-like video via the Internet, communicate with real-time video and voice, render 3D graphics in real time, quickly encode music for MP3 players, and simultaneously run several multimedia applications while still connected to the Internet. As a comparison, Intel's first microprocessor, the 4004, ran at 108 kilohertz, compared to the Pentium 4 processor's initial speed of 1.5 gigahertz. If automobile speed had increased similarly over the same period, you could now drive from San Francisco to New York in about 13 seconds.

History of Intel Microprocessor

The Continuing Evolution of Intel Microprocessors CIS105 December 2002
1600 1,400 1400 1200

Speed (MHZ)

1000 800 600 400 400 200 200 0.74 0 1971 1974 1979 1982 1985 1989 1993 1995 1997 1998 1998 1999 1999 2000 2 8 12 33 100 200 233 333 400 550

Year

Bch Khoa Online: hutonline.net Tm kim & download ebook: bookilook.com

Bi ging K thut Vi x l
Ngnh in t-Vin thng i hc Bch khoa Nng ca H Vit Vit, Khoa CNTT-TVT

Ti liu tham kho [1] K thut vi x l, Vn Th Minh, NXB Gio dc, 1997 [2] K thut vi x l v Lp trnh Assembly cho h vi x l, Xun Tin, NXB Khoa hc & k thut, 2001

Chng 2

Vi x l v H thng vi x l
2.1 B vi x l
- B vi x l (Microprocessor) l g? - Cc thnh phn ca b vi x l

- ng dng ca b vi x l

2.2 Cc h vi x l
- H x86 ca Intel- Lut Moore

- H 68x ca Motorola

2.3 H thng vi x l
B nh Cc cng I/O Bus h thng: D-Bus, A-Bus, C-Bus Thit k h thng vi x l?

2.1 B vi x l

Mt b vi x l l mt mch tch hp cha hng ngn, thm ch hng triu transistor (LSI, VLSI) c kt ni vi nhau Cc transistor y cng nhau lm vic lu tr v x l d liu cho php b vi x l c th thc hin rt nhiu chc nng hu ch Chc nng c th ca mt b vi x l c xc nh bng phn mm (c th lp trnh c)

B vi x l

B vi x l u tin ca Intel,4004, c gii thiu vo nm 1971. 4004 cha 2300 transistor. B vi x l Pentium 4 hin nay cha 55 triu transistor. B vi x l thng c s dng trong cc my vi tnh (microcomputer) vi vai tr l CPU. Ngoi ra, chng cn c mt nhiu thit b khc.

Cc thnh phn ca b vi x l

ALU v Control Unit

ALU Thc hin cc php ton logic (AND, OR, XOR, NOT) v cc php ton s hc (cng, tr, nhn, chia) Thc hin vic chuyn d liu Vic thc hin lnh thc s din ra ALU Control Unit C trch nhim lin quan n vic tm v thc hin cc lnh bng cch cung cp cc tn hiu iu khin v nh thi cho ALU v cc mch khc bit phi lm g v lm khi no.

Cc thanh ghi (Registers)

Thanh ghi l ni m b vi x l c th lu tr c mt s nh phn (Kch c ca thanh ghi tnh bng bit) B vi x l dng cc thanh ghi lu tr d liu tm thi trong qu trnh thc hin chng trnh Cc thanh ghi c th c truy cp bng cc cu lnh ngn ng my thng c gi l cc thanh ghi ngi s dng c th nhn thy c (c th truy cp c) Cc thanh ghi iu khin v cc thanh ghi trng thi c CU dng iu khin vic thc hin chng trnh. a s cc thanh ghi ny ngi s dng khng th nhn thy c

2.2 Cc h vi x l

Hin nay, c rt nhiu nh sn xut ra cc chip vi x l:Intel, AMD, Motorola, Cyrix Thng thng, mt h vi x l l cc chip vi x l c sn xut bi mt nh sn xut no . Trong phm vi mt h vi x l, theo thi gian v theo cng ngh ch to c cc i (th h) vi x l khc nhau phn bit theo di T ca chng (bit) v tc (Hz). di T (Word Length) ca mt chip vi x l l kch c ti a ca cc ton hng nh phn m n c th thc hin cc php ton trn .

Tc ca h vi x l x86 ca Intel
The Continuing Evolution of Intel Microprocessors CIS105 December 2002
1600 1,400 1400 1200

Speed (MHZ)

1000 800 600 400 400 200 200 0.74 0 1971 1974 1979 1982 1985 1989 1993 1995 1997 1998 1998 1999 1999 2000 2 8 12 33 100 200 233 333 400 550

Year

H vi x l x86 ca Intel
Model 4004 8008 8080 8086 80286
80386 processor 80486 DX processor Pentium processor Pentium II processor Pentium III processor Pentium 4 processor

Nm sn xut 1971 1972 1974 1978 1982

1985 1989 1993 1997 1999 2000

S lng Transistor 2,300 2,500 5,000 29,000 120,000

275,000 1,180,000 3,100,000 7,500,000 24,000,000 55,000,000

H vi x l x86 ca Intel 70s

4004
Introduced Clock Speeds Bus Width Number of Transistors Addressable Memory Virtual Memory Brief Description 11/15/71 108KHz 4 bits 2,300 (10 microns) 640 bytes -First microcomputer chip, Arithmetic manipulation

8008
4/1/72 200KHz 8 bits 3,500 (10 microns) 16 KBytes -Data/character manipulation

8080
4/1/74 2MHz 8 bits 6,000 (6 microns) 64 KBytes -10X the performance of the 8008

8086
6/8/78 5MHz, 8MHz, 10MHz 16 bits 29,000 (3 microns) 1 MB -10X the performance of the 8080

H vi x l x86 ca Intel 80s

Intel386TM DX Microprocessor
10/17/85 16MHz, 20MHz, 25MHz, 33MHz 32 bits 275,000 (1 micron) 4 gigabytes 64 terabytes First X86 chip to handle 32-bit data sets

80286
Introduced Clock Speeds Bus Width Number of Transistors Addressable Memory Virtual Memory Brief Description 2/1/82 6MHz, 8MHz, 10MHz, 12.5MHz 16 bits 134,000 (1.5 microns) 16 megabytes 1 gigabyte 3-6X the performance of the 8086

Intel386TM SX Microprocessor
6/16/88 16MHz, 20MHz, 25MHz, 33MHz 16 bits 275,000 (1 micron) 16 megabytes 64 terabytes 16-bit address bus enabled low-cost 32-bit processing

Intel486TM DX CPU Microprocessor

4/10/89 25MHz, 33MHz, 50MHz 32 bits 1.2 million (1 micron) (.8 micron with 50MHz) 4 gigabytes 64 terabytes Level 1 cache on chip

H vi x l x86 ca Intel 90s

Intel486TM SX Microprocessor
Introduced Clock Speeds Bus Width Number of Transistors Addressable Memory Virtual Memory Brief Description 4/22/91 16MHz, 20MHz, 25MHz, 33MHz 32 bits 1.185 million (1 micron) 4 gigabytes 64 terabytes Identical in design to Intel486TM DX but without math coprocessor

Pentium Processor
3/22/93 60MHz,66MHz 64 bits 3.1 million (.8 micron) 4 gigabytes 64 terabytes Superscalar architecture brought 5X the performance of the 33-MHz Intel486TM DX processor

Pentium Pro Processor

11/01/95 150MHz, 166MHz, 180MHz, 200MHz 64 bits 5.5 million (0.35 micron) 64 gigabytes 64 terabytes Dynamic execution architecture drives high-performing processor

Pentium II Processor
5/07/97 200MHz, 233MHz, 266MHz, 300MHz 64 bits 7.5 million (0.35 micron) 64 gigabytes 64 terabytes Dual independent bus, dynamic execution, Intel MMXTM technology

2.3 H thng vi x l

Lut Moore

Dr. Gordon E. Moore, Chairman Emeritus of Intel Corporation, d on rng C mt nm ri th s lng transistor c tch hp trn chip vi x l tng gp i

2.3 H thng vi x l
Address Bus

MEMORY

I/O Ports

Microprocessor
Data Bus

Control Lines (Control Bus)

S khi chc nng ca mt h thng vi x l

H thng vi x l

Gm 3 khi chc nng: Vi x l, B nh, Cc cng I/O B nh c thc hin bng cc chip nh bn dn ROM hoc RWM, l ni lu tr chng trnh v d liu. i vi vi x l, b nh l mt tp hp cc nh phn bit theo a ch ca chng. Cc cng I/O c thc hin bng cc chip MSI hoc LSI, l phn mch giao tip gia vi x l vi cc thit b I/O. B vi x l cng phn bit cc cng I/O theo a ch ca chng.

H thng vi x l

3 khi chc nng: Vi x l, B nh, Cc cng I/O ca mt h thng vi x l trao i tn hiu vi nhau thng qua Bus h thng. Bus h thng l mt tp hp cc ng truyn dn dng chung, bao gm: Bus a ch (A-Bus), Bus d liu (D-Bus) v Bus iu khin (C-Bus) Cc tn hiu a ch di chuyn trn A-Bus theo hng t vi x l n B nh v cc cng I/O. S lng ng truyn dn ca A-Bus (gi l rng ca A-Bus) tnh bng bit, phn nh kh nng qun l b nh ca chip vi x l.

H thng vi x l

Cc tn hiu d liu di chuyn trn D-Bus theo c 2 hng t vi x l n B nh v cc cng I/O v ngc li (mi lc mt hng). S lng ng truyn dn ca DBus (gi l rng ca D-Bus) tnh bng bit, phn nh mt phn tc trao i d liu ca chip vi x l vI cc khi chc nng khc. a s cc tn hiu trn C-Bus l cc tn hiu iu khin ring l, c tn hiu xut pht t vi x l, c tn hiu i vo vi x l. Vi x l s dng cc tn hiu ny iu khin hot ng v nhn bit trng thi ca cc khi chc nng khc.

Thit k phn cng ca h thng vi x l

Thit k b nh cho h thng vi x l: Ghp ni cc chip nh bn dn sn c vi bus h thng sao cho khi b vi x l truy cp b nh th khng xy ra xung t gia cc chip nh vi nhau v khng xung t vi cc chip dng lm cng I/O Tng t, Thit k cc cng I/O cho h thng vi x l: Ghp ni cc chip MSI hoc LSI thng dng lm cng I/O vi bus h thng sao cho khi b vi x l truy cp cc thit b I/O th khng xy ra xung t gia cc chip vi nhau v khng xung t vi cc chip dng lm b nh

Thit k phn mm ca h thng vi x l

Vit chng trnh iu khin hot ng ca h thng phn cng theo chc nng mong mun (thng dng ngn ng Assembly ca chip vi x l dng trong h thng) Dch chng trnh vit sang ngn ng my s dng cc chng trnh dch thch hp Np chng trnh ngn ng my vo b nh ca h thng vi x l Kim tra hot ng ca h thng v thc hin cc hiu chnh nu cn thit C th nh s tr gip ca cc chng trnh m phng trn my tnh

 Bch Khoa Online: hutonline.net Tm kim & download ebook: bookilook.com

Bay ging K thut Vi x l

Ngnh in t-Vin thng i hc Bch khoa Nng ca H Vit Vit, Khoa CNTT-TVT

Ti liu tham kho [1] K thut vi x l, Vn Th Minh, NXB Gio dc, 1997 [2] K thut vi x l v Lp trnh Assembly cho h vi x l, Xun Tin, NXB Khoa hc & k thut, 2001

Chng 3 Vi x l 8088-Intel 3.1 Kin trc v hot ng ca 8088 - Nguyn l hot ng - S khi chc nng 3.2 Cu trc thanh ghi ca 8088 3.3 Phng php qun l b nh 3.4 M t tp lnh Assembly

Nguyn l hot ng ca mt b vi x l

Ly - Gii m - Thc hin lnh

Tm v copy cc byte lnh t b nh

To ra cc tn hiu iu khin thc hin lnh

Gii m lnh

Chu k lnh v Chu k my

Chu k lnh: Tng thi gian tm lnh, gii m lnh v thc hin 1 lnh Ni chung, Chu k lnh ca cc lnh khc nhau l khc nhau Chu k lnh bao gi cng bng mt s nguyn ln chu k my Chu k my bng nghch o ca tn s hot ng (tc ng h) ca b vi x l

3.1 Kin trc v Hot ng ca 8088

n v giao tip Bus - BIU

Pht cc tn hiu a ch n b nh v cc cng I/O thng qua A-Bus c m lnh t b nh thng qua D-Bus c d liu t b nh thng qua D-Bus Ghi d liu vo b nh thng qua D-Bus c d liu t cc cng I thng qua D-Bus Ghi d liu ra cc cng O thng qua D-Bus

n v thc hin - EU
Bao gm CU v ALU CU : Gii m lnh to ra cc tn hiu iu khin nhm thc hin lnh c gii m ALU: thc hin cc thao tc khc nhau i vi cc ton hng ca lnh

T chc ca microprocessor
CPU Control registers

ALU BIU Control

Control Address Data

General purpose registers

Status Registers

X l lnh ca cc vi x l trc 8086/8088

Mt th tc n gin gm 3 bc:
Ly lnh t b nh Gii m lnh Thc hin lnh
Ly cc ton hng t b nh (nu c) Lu tr kt qu

Fetch 1

Decode 1

Execute 1

Fetch 2

Decode 2

Execute 2

...

Microprocessor

Busy

Idle

Busy

Busy

Idle

Busy

...

Bus

C ch Pipelining
Pipelining

Fetch 1

Fetch 2

Fetch 3

Fetch 4

Store 1

Fetch 5 Idle

Fetch 6

Load 2

Fetch 7 Idle

...

Bus

Decode Decode Decode Decode 1 2 3 4

Decode Decode 5 6

Decode 7

...

Instruction Unit

Exec. 1

Exec. 2

Exec. 3

Exec. 4

Idle Idle

Exec. 5

Exec. 6

Idle

Exec. 7

Execution Unit

Memory request

Memory request

3.2 Cu trc thanh ghi ca 8088

8088 c 14 thanh ghi 16-bit

Cu trc thanh ghi ca h x86

General Purpose
Special Registers
Accumulator
EAX AH AX AL

Instr Pointer
EIP BL

Index Registers
IP

Stack Pointer
FLAG ESP

SP

Base
EBX

BH BX

Flags
EFLAG

Base Pointer
EBP

BP

Count

CH CX ECX

CL

Segment Registers
CS

Dest Index
EDI

DI

Data

DH DX EDX

DL DS

Code Segment Data Segment

Source Index
ESI

SI

ES
SS FS GS

Extra Segment
Stack Segment

Cu trc thanh ghi 8086/8088

7 0 7 0

Accumulator Base Counter Data

15

AH BH CH DH CS DS SS ES
15

AL BL CL DL
0

AX BX CX DX

Code Segment Data Segment Stack Segment Extra Segment

Instruction Pointer Stack Pointer Base Pointer Source Index

Destination Index

IP SP BP SI DI

} }

Cc thanh ghi a nng

7 0 7 0

Accumulator Base Counter Data

AH BH CH DH

AL BL CL DL

AX BX CX DX

- C th truy cp nh cc thanh ghi 8-bit

- Lu tr tm thi d liu truy cp nhanh hn v trnh khi phi truy cp b nh - C cng dng c bit i vi mt s cu lnh

Cc thanh ghi segment

15 0

Code Segment Data Segment Stack Segment Extra Segment

CS DS SS ES

- Lu tr a ch segment ca mt nh cn truy cp

- Kt hp vi cc thanh ghi offset nht nh

Cc thanh ghi offset

Instruction Pointer Stack Pointer Base Pointer Source Index Destination Index

IP SP BP SI DI

- Lu tr a ch offset ca mt nh cn truy cp

- Kt hp vi cc thanh ghi segment nht nh

Thanh ghi c
15 0

x OF DF IF TF SF ZF x AF x PF x CF

- Khng phi tt c cc bit u c s dng - Mi bit c s dng c gi l mt c - Cc c u c tn v c th c Lp/Xo ring l - Bao gm cc c trng thi v cc c iu khin

Flags register
AC (Alignment check) (VM) Virtual mode (RF) Resume
(NT) Nested task (IOPL) Input/output privilege level (O) Overflow (D) Direction (I) Interrupt (T) Trace (S) Sign (Z) Zero (A) Auxiliary Carry (P) Parity (C) Carry

8086, 8088, 80186

80386, 80486DX

80286

80486SX

3.3 Phng php qun l b nh

- B nh c xem l mt tp hp cc nh - Mi nh c nhn dng bng mt a ch vt l duy nht 20-bit - Trong hot ng truy cp mt nh, a ch vt l ca n c to ra t hai gi tr 16-bit: a ch segment v a ch Offset - a ch logic = a ch segment:a ch offset

Mi lin h gia CVL v CLG

A=Bus

19 a ch vt l

15

15

Thanh ghi offset.

Thanh ghi Segment

0000

3.4 M t tp lnh Assembly ca 8086/8088

- Khun dng: Mnemonics Cc ton hng - Nhm lnh chuyn s liu - Nhm lnh s hc - Nhm lnh logic - Nhm lnh R nhnh - Nhm lnh thao tc string - Nhm lnh hn hp

Nhm lnh chuyn s liu Data Transfer Instructions

-Chuyn s liu (sao chp s liu) t v tr ny sang v tr khc - Ngun s liu khng thay i - ich s c gi tr nh gi tr ca Ngun - Cc lnh chuyn s liu khng nh hng n cc c trng thi trn thanh ghi c - Mt s lnh tiu biu: MOV, XCHG

- Tc dng: (ch) (Ngun) - ch: c th l:

Data Transfer Instructions MOV Khun dng: MOV ch,Ngun

1. Mt thanh ghi 8 hoc 16 bit ca VXL 2. Mt v tr nh (1 hoc 2 nh lin tip nhau)

Ngun: c th l:

1. Mt thanh ghi 8 hoc 16 bit ca VXL 2. Mt v tr nh (1 hoc 2 nh lin tip nhau) 3. Mt gi tr c th

Mt s lu i vi MOV
- ch v Ngun phi c cng kch c - ch v Ngun khng th ng thi thuc b nh - Nu ch l mt thanh ghi segment ca VXL th Ngun khng th l mt gi tr c th (ni cch khc, khng th np gi tr trc tip cho mt thanh ghi segment bng lnh MOV)

Data Transfer Instructions - XCHG

Khun dng: XCHG T/h1,T/h2

- Tc dng: (T/h1) (T/h2) - T/h1: c th l:
1. Mt thanh ghi 8 hoc 16 bit ca VXL 2. Mt v tr nh (1 hoc 2 nh lin tip nhau)

T/h2: c th l:

1. Mt thanh ghi 8 hoc 16 bit ca VXL 2. Mt v tr nh (1 hoc 2 nh lin tip nhau)

Mt s lu i vi XCHG
- T/h1 v T/h2 phi c cng kch c - T/h1 v T/h2 khng th ng thi thuc b nh - T/h1 v T/h2 khng th l cc thanh ghi segment

Cc mode a ch
- Khi thc hin lnh, VXL s thc hin nhng thao tc nht nh trn s liu, cc s liu ny c gi chung l cc ton hng. - Cc ton hng trong mt cu lnh c th l mt phn ca cu lnh ( dng m my), c th nm mt thanh ghi ca VXL hoc B nh -Cch xc nh ton hng trong cc cu lnh c gi l cc mode (nh) a ch

Cc mode a ch
- Mode a ch thanh ghi: MOV AX,BX - Mode a ch tc th: MOV AL,55h - Cc mode a ch b nh: Cc cch thc xc nh a ch vt l ca ton hng nm trong b nh: Mode a ch trc tip Cc mode a ch gin tip

Mode a ch trc tip (Direct Addressing Mode)

Mode a ch gin tip thanh ghi (Register Indirect Addressing Mode)

Mode a ch c s-ch s

(Based-Indexed Addressing Mode)

Nh cc mode a ch b nh nh th no? Tt c bt u trong bng sau y:

DISP BX SI DI

BP

Ly ra 0 hoc 1 phn t t mi ct (Khng ly 2 phn t t mt ct) Phi ly t nht 1 phn t t bng

Cc v d
Instruction Comment Addressing Mode Register 89 D8 Memory Contents MOV AX, BX Move to AX the 16-bit value in BX
OP MODE

MOV AX, DI

Move to AX the 16-bit value in DI

Register

89 F8

OP

MODE

MOV AH, AL

Move to AL the 8-bit value in AX

Register

88 C4

OP

MODE

MOV AH, 12h

Move to AH the 8-bit value 12H

Immediate

B4 12

OP

DATA8

MOV AX, 1234h

Move to AX the value 1234h

Immediate

B8 34

OP

DATA16

MOV AX, CONST

Move to AX the constant defined as CONST

Move to AX the address or offset of the variable X Move to AX the value at memory location 1234h Move to AX the value in memory location DS:X

Immediate

B8 lsb msb

OP

DATA16

MOV AX, X

Immediate

B8 lsb msb

OP

DATA16

MOV AX, [1234h]

Direct

A1 34 12

OP

DISP16

MOV AX, [X]

Direct

A1 lsb msb

OP

DISP16

Cc v d
Instruction Comment Move to the memory location pointed to by DS:X the value in AX Move to AX the 16-bit value pointed to by DS:DI Move to address DS:DI the 16-bit value in AX Move to AX the 16-bit value pointed to by DS:BX Move to the memory address DS:BX the 16-bit value stored in AX Move to memory address SS:BP the 16-bit value in AX Move to AX the value in memory at DS:BX + TAB Move value in AX to memory address DS:BX + TAB Move to AX the value in memory at DS:BX + DI Addressing Mode Memory Contents

MOV [X], AX

Direct

A3 lsb msb

OP

DATA16

MOV AX, [DI]

Indexed

8B 05

OP

MODE

MOV [DI], AX

Indexed Register Indirect Register Indirect Register Indirect Register Relative Register Relative Base Plus Index

89 05

OP

MODE

MOV AX, [BX]

8B 07

OP

MODE

MOV [BX], AX

89 07

OP

MODE

MOV [BP], AX

89 46

OP

MODE

MOV AX, TAB[BX]

8B 87 lsb msb

OP

MODE

DISP16

MOV TAB[BX], AX

89 87 lsb msb

OP

MODE

DISP16

MOV AX, [BX + DI]

8B 01

OP

MODE

Cc v d
Instruction Comment Addressing Mode Memory Contents

MOV [BX + DI], AX

Move to the memory location pointed to by DS:X the value in AX

Base Plus Index

89 01

OP

MODE

MOV AX, [BX + DI + 1234h]

Move word in memory location DS:BX + DI + 1234h to AX register

Base Rel Plus Index

8B 81 34 12

OP

MODE

DISP16

MOV word [BX + DI + 1234h], 5678h

Move immediate value 5678h to memory location BX + DI + 1234h

Base Rel Plus Index

C7 81 34 12 78 56

Mt lnh c th di t1 n 6 byte Byte 1 gm:

M my

Opcode (6 bit) xc nh php ton cn thc hin Bit D xc nh ton hng REG ca Byte 2 l ngun hay ch: 1: ch

0: Ngun
Bit W xc nh kch c ca ton hng l 8 bit hay 16 bit 0: 8 bit

1: 16 bit
Byte 2 gm:Mode field (MOD), Register field (REG) Register/memory field (R/M field)

Anatomy of an instruction
Opcode Mode Displacement Data/Immediate

D W

OPCODE

Opcode contains the type of instruction we execute plus two special bits, D and W The mode byte is used only in instructions that use register addressing modes and encodes the source and destination for instructions with two operands D stands for direction and defines the data flow of the instruction
D=0, data flows from REG to R/M D=1, data flows from R/M to REG

MOD

REG

R/M

W stands for the size of data

W=0, byte-sized data W=1, word (in real mode) or double-word sized (in protected mode)

Anatomy of an instruction
Opcode Mode Displacement Data/Immediate

D W

OPCODE

MOD field specifies the addressing mode 00 no displacement 01 8-bit displacement, sign extended 10 16-bit displacement 11 R/M is a register, register addressing mode If MOD is 00,01, or 10, the R/M field selects one of the memory addressing modes

MOD

REG

R/M

Registers in the REG and R/M fields

Code 000 001 010 011 100 101 110 111 W=0 (Byte) AL CL DL BL AH CH DH BH W=1 (Word) AX CX DX BX SP BP SI DI W=1 (DWord) EAX ECX EDX EBX ESP EBP ESI EDI

Example
Consider the instruction 8BECh 1000 1011 1110 1100 binary Opcode 100010 -> MOV D=1 data goes from R/M to REG W=1 data is word-sized MOD=11, register addressing REG=101 destination, R/M=100 source MOV BP, SP
Code 000 001 W=0 AL CL W=1 AX CX W=1 EAX ECX

010
011 100 101 110 111

DL
BL AH CH DH BH

DX
BX SP BP SI DI

EDX
EBX ESP EBP ESI EDI

Displacement addressing
If MOD is 00, 01, or 10 R/M has an entirely different meaning
MOD 00 01 10 11 No displacement 8-bit sign-extended displacement 16-bit displacement R/M is a register (register addressing mode) FUNCTION

R/M Code 000 001 010 011 100 101 110

Function DS:BX+SI DS:BX+DI SS:BP+SI SS:BP+DI DS:SI DS:DI SS:BP

Examples: If MOD=00 and R/M=101 mode is [DI] If MOD=01 and R/M=101 mode is [DI+33h] If MODE=10 and R/M=101 modes is [DI+2233h]

111

DS:BX

Example
Instruction 8A15h 1000 1010 0001 0101 Opcode 100010 -> MOV D=1, data flows from R/M to REG W=0, 8-bit argument MOD=00 (no displacement) REG=010 (DL) REG=101 ([DI] addressing mode) MOV DL, [DI]

Code 000 001

W=0 AL CL

W=1 AX CX

W=1 EAX ECX

010
011 100 101 110 111

DL
BL AH CH DH BH

DX
BX SP BP SI DI

EDX
EBX ESP EBP ESI EDI

R/M Code
000 001 010 011 100 101 110 111

Function
DS:BX+SI DS:BX+DI SS:BP+SI SS:BP+DI DS:SI DS:DI SS:BP DS:BX

Direct Addressing Mode

MOD is always 00 R/M is always 110 REG encodes the register to/from we take data as usual Third byte contains the lower-order bytes of the displacement, fourth byte contains the high order byte of the displacement

Direct Addressing
Example: 8816 00 10 1000 1000 0001 0110 0000 0000 0001 0000 Opcode 100010 -> MOV W=0 (byte-sized data) D=0 data flows from REG MOD 00, REG=010 (DL), R/M=110 Low-order byte of displacement 00 High-order byte of displacement 10 MOV [1000h], DL
Code 000 001 010 011 100 101 111 AL CL DL BL AH CH BH

W=0

W=1 AX CX DX BX SP BP

W=1 EAX ECX EDX EBX ESP EBP

110

DH

SI
DI

ESI
EDI

Segment MOV instructions

Different opcode 100011 Segments are selected by setting the REG Example MOV BX, CS field
REG Code 000 001 010 011 100 101 Segment reg. ES CS SS DS FS GS

Opcode 10001100
MOD=11 (register addressing) REG=001 (CS) R/M=011 (BX) 8CCB

M my
REG xc nh thanh ghi cho ton hng th nht

M my
MOD v R/M cng nhau xc nh ton hng th hai

M my
MOD v R/M cng nhau xc nh ton hng th hai

V d
M ho lnh MOV

BL,AL

Opcode i vi MOV l 100010 Ta m ho AL sao cho AL l ton hng ngun: D = 0 (AL l ton hng ngun) W bit = 0 (8-bit) MOD = 11 (register mode) REG = 000 (m ca AL)

R/M = 011 (m ca BL)

Kt qu:: 10001000 11000011 = 88 C3

Nhm lnh S hc
Bn cnh tc dng, cn ch n nh hng ca lnh i vi cc c trng thi Cc lnh s hc th/thng: ADD, SUB, Cc lnh s hc khc: CMP. NEG, INC, DEC, nh hng n cc c trng thi
CF OF AF
Ph thuc vo qu trnh thc hin php ton

ZF = 1 nu Kt qu bng 0 SF = 1 nu MSB ca Kt qu = 1 PF = 1 nu byte thp ca kt qu c Parity chn

Arithmetic Instructions - ADD Khun dng: ADD ch,Ngun

- Tc dng: (ch) (ch)+(Ngun) - ch: c th l:
1. Mt thanh ghi 8 hoc 16 bit ca VXL 2. Mt v tr nh (1 hoc 2 nh lin tip nhau)

Ngun: c th l:

1. Mt thanh ghi 8 hoc 16 bit ca VXL 2. Mt v tr nh (1 hoc 2 nh lin tip nhau) 3. Mt gi tr c th

nh hng ca ADD
ZF = 1 nu Kt qu bng 0 SF = 1 nu MSB ca Kt qu = 1 PF = 1 nu byte thp ca kt qu c Parity chn

CF c lp nu trn khng du (c nh t MSB) OF c lp nu trn c du: - C nh t MSB, Khng c nh vo MSB - C nh vo MSB, Khng c nh t MSB AF c lp nu c nh t nibble thp vo nibble cao (t bit 3 vo bit 4)

Cc c trn thanh ghi c

Cc bit nht nh trn thanh ghi c iu khin hot ng hoc phn nh trng thi ca vi x l
Cc c iu khin (TF, IF, DF)
Quyt nh cch p ng ca vi x l trong cc tnh hung nht nh

Cc c trng thi (CF, PF, AF, ZF, SF, OF)

B nh hng bi cc php ton nht nh Phc v cho cc lnh c iu kin

Cc c iu khin
DF - Direction flag (C hng)
DF = 1: hung xung DF = 0: hng ln

IF Interrupt flag (C ngt)

IF = 1: cho php ngt ngoi IF = 0: cm ngt ngoi (i vi ngt che c)

TF - Trace flag
TF = 1: vi x l thc hin tng lnh mt

Cc c trng thi
Carry
carry or borrow at MSB in add or subtract last bit shifted out

Zero
result is 0

Sign
result is negative

Parity
low byte of result has even parity

Overflow
signed overflow occurred during add or subtract

Auxiliary
carry or borrow at bit 3

(Signed) Overflow
Can only occur when adding numbers of the same sign (subtracting with different signs) Detected when carry into MSB is not equal to carry out of MSB
Easily detected because this implies the result has a different sign than the sign of the operands

Programs can ignore the Flags!

Signed Overflow Example

10010110 + 10100011 00111001
Carry in = 0, Carry out = 1 Neg+Neg=Pos Signed overflow occurred OF = 1 (set)

00110110 + 01100011 10011001

Carry in = 1, Carry out = 0 Pos+Pos=Neg Signed overflow occurred OF = 1 (set)

Examples of No Signed Overflow

10010110 + 01100011 11111001
Carry in = 0, Carry out = 0 Neg+Pos=Neg No Signed overflow occurred OF = 0 (clear)

10010110 + 11110011 10001001

Carry in = 1, Carry out = 1 Neg+Neg=Neg No Signed overflow occurred OF = 0 (clear)

Unsigned Overflow
The carry flag is used to indicate if an unsigned operation overflowed The processor only adds or subtracts - it does not care if the data is signed or unsigned!
10010110 + 11110011 10001001
Carry out = 1 Unsigned overflow occurred CF = 1 (set)

DEBUG's Register Display

-R 000 SP=0010 BP=0000 SI=0000 DI=0000 00F IP=004F NV UP DI PL NZ NA PO NC

The state of the Flags are shown in line 2

OV/NV: EI/DI: NG/PL: AC/NA: CY/NC: (no)oVerflow DN/UP: direction En(Dis)abled Interrupts sign ZR/NZ: (not)Zero (no)Auxiliary PE/PO: Even/Odd (no)Carry (set/clear)

Arithmetic Instructions - SUB Khun dng: SUB ch,Ngun

- Tc dng: (ch) (ch)-(Ngun) - ch: c th l:
1. Mt thanh ghi 8 hoc 16 bit ca VXL 2. Mt v tr nh (1 hoc 2 nh lin tip nhau)

Ngun: c th l:

1. Mt thanh ghi 8 hoc 16 bit ca VXL 2. Mt v tr nh (1 hoc 2 nh lin tip nhau) 3. Mt gi tr c th

nh hng ca SUB
ZF = 1 nu Kt qu bng 0 SF = 1 nu MSB ca Kt qu = 1 PF = 1 nu byte thp ca kt qu c Parity chn

CF c lp nu trn khng du (c mn vo MSB) OF c lp nu trn c du: - C mn t MSB, Khng c mn t MSB - C mn t MSB, Khng c mn vo MSB AF c lp nu c mn t nibble cao vo nibble thp (t bit 4 vo bit 3)

Arithmetic Instructions - CMP Khun dng: CMP ch,Ngun

- Tc dng: (ch)-(Ngun) - ch: c th l:
1. Mt thanh ghi 8 hoc 16 bit ca VXL 2. Mt v tr nh (1 hoc 2 nh lin tip nhau)

Ngun: c th l:

1. Mt thanh ghi 8 hoc 16 bit ca VXL 2. Mt v tr nh (1 hoc 2 nh lin tip nhau) 3. Mt gi tr c th

Arithmetic Instructions INC, DEC, NEG

INC T/h
Trong : T/h c th l cc thanh ghi hoc v tr nh

Tc dng: (T/h) (T/h)+1 DEC T/h

Trong : T/h c th l cc thanh ghi hoc v tr nh

Tc dng: (T/h) (T/h)-1

Lu : Cc lnh INC v DEC khng nh hng n c CF

Lnh NEG T/h: o du ca T/h (Ly b 2)

Lnh NEG s lp c OF nu gi tr ca T/h l gi tr m nht trong di gi tr ca cc s c du tng ng

Nhm lnh Logic

Cn ch n nh hng ca lnh i vi cc c trng thi Cc lnh logic th/thng: NOT, AND, OR, XOR NOT A: ~A AND A,B: A &= B OR A,B : A |= B XOR A,B: A ^= B NOT khng nh hung n cc c trng thi. Cc lnh khc:
CF = 0 OF = 0 ZF = 1 nu Kt qu bng 0 SF = 1 nu MSB ca Kt qu = 1 PF = 1 nu byte thp ca kt qu c Parity chn AF khng xc nh

Mt s v d
AL 1100 1010 NOT AL AL 0011 0101 AL 0011 0101 BL 0110 1101 AND AL, BL AL 0010 0101 AL 0011 0101 BL 0000 1111 AND AL, BL AL 0000 0101 AL BL 0011 0101 0110 1101 OR AL, BL AL 0111 1101 AL BL 0011 0101 0000 1111 OR AL, BL AL 0011 1111 AL 0011 0101 BL 0110 1101 XOR AL, BL AL 0101 1000

Mt s ng dng
Bi ton Xo bit: Xo mt bit no ca mt ton hng m khng lm nh hng n cc bit cn li ca ton hng Bi ton Kim tra bit: Xc nh mt bit no ca mt ton hng l bng 0 hay 1 (thng qua gi tr ca mt c trng thi) Bi ton Lp bit: Lp mt bit no ca mt ton hng m khng lm nh hng n cc bit cn li ca ton hng

Nhm lnh logic

Cc lnh logic khc: Lnh TEST, Cc lnh dch (Shift) v Cc lnh quay (Rotate) Lnh TEST ch khc lnh AND l khng gi li kt qu ca php ton Cc lnh dch v Cc lnh quay u c hai khun dng: Khun dng 1: Mnemonic Ton hng,1 Khun dng 2: Mnemonic Ton hng,CL Tc dng ca mt cu lnh theo khun dang 2 ging nh tc dng lin tip ca N cu lnh tng ng theo khun dng 1, vi N l gi tr ca thanh ghi CL

Cc lnh Dch tri: SHL, SAL

CF Register 0

Shift right SHR

Register

CF

Shift right SAR

Register CF

Rotate through Carry L/R (Quay tri/phi thng qua carry)

RCL

RCR

Rotate left/right (Quay tri/phi khng qua carry)

ROL

ROR

Nhm lnh r nhnh

Lm thay i trt t thc hin lnh bnh thng ca vi x l
Lnh nhy khng iu kin: JMP Cc lnh nhy c iu kin: Jxxx Lnh lp: LOOP v cc bin th ca n Cc lnh c lin quan n Chng trnh con: - CALL (gi chng trnh con) - RET (tr v chng trnh gi) Cc lnh c lin quan n Chng trnh con phc v ngt - INT (gi chng trnh con phc v ngt - Gi ngt) - IRET (quay v chng trnh gi ngt)

Lnh nhy khng iu kin

JMP nhn
Nhy gn: E9 xx xx (3 byte) Nhy ngn: EB xx (2 byte) Nhy xa: EA xx xx xx xx (5 byte) Nhn: tn do ngI lp trnh t t ra theo qui tc t tn ca Assembler v c th t vo trc mt cu lnh bt k trong chng trnh cng vi du :

nhn: Cu lnh cn thc hin

Nhn s c dch thnh a ch Khong cch nhy: Khong cch i s (c du) t lnh nhy n lnh cn thc hin

C ch thc hin lnh nhy

Cc lnh nhy ngn v gn ch lm thay i gi tr ca thanh ghi IP
Lnh nhy ngn cng khong cch nhy 8-bit c du vo gi tr hin thi ca IP Lnh nhy gn cng khong cch nhy 16-bit c du vo gi tr hin thi ca IP

Lnh nhy xa lm thay i c CS v IP

Gn cho CS v IP cc gi tr mi

M my ca lnh nhy
1106:0100 EB2A JMP 012C 012C-0102=002A 1106:0102 EBFC JMP 0100 0100-0104=FFFC 1106:0104 E97F00 JMP 0186 0186-0106=0080 (too far for short!) 0186-0107=007F 1106:0107 E9F5FE JMP FFFF FFFF-010A=FEF5

Cc lnh nhy c iu kin

Jxxx nhn
C gn 40 menmonic khc nhau

Cc lnh nhy iu kin n: ph thuc vo gi tr ca 1 c. JNZ/JNE - Nhy nu c ZF = 0, ngha l kt qu ca php ton trc khc khng JC - Nhy nu CF = 1, ngha l cu lnh trc lp c carry JZ/JE JNC

Cc lnh nhy c iu kin

Tt c cc lnh nhy c iu kin phi l nhy ngn
khong cch nhy: -128 to +127 bytes

T hp vi lnh nhy khng iu kin c th vt qua gii hn ny. Cc lnh nhy iu kin kp: ph thuc vo gi tr ca nhiu c JB/JNAE JNL/JGE

ng dng ca cc lnh nhy c iu kin

Kt hp vi JMP xy dng cc cu trc lp trnh c bn:
- Cu trc iu kin - Cu trc lp Cc lnh nhy thng theo sau cc lnh lm thay i gi tr ca cc c trng thi:
CMP TEST

Cu trc iu kin
mov ax,n cmp ax,7 jz nhan1 lnh 1 jmp nhan2 nhan1:lnh 2 nhan2:lnh 3

Cu trc lp
mov ax,n
nhan1: cmp ax,0 jz nhan2 lnhi sub ax,2 jmp nhan1 nhan2: lnhk

Cu trc iu kin - AND

char n; int w,x; if (n>='A' && w==x) whatever();
;if(n>='A'&&w==x) mov ah,n cmp ah,'A' jl nogo mov ax,w cmp ax,x jne no_go ;then-part call whatever nogo:

Cu trc iu kin - OR
char n,k; unsigned int w; if (n<>k || w<=10) whatever();
;if(n<>k||w<=10) mov ah,n cmp ah,k jne then_ cmp w,10 ja end_if then_: call whatever end_if:

Lnh LOOP
LOOP nhan
Gim CX i 1 Nu (CX) <> 0 th JMP nhan. Nu khng th tip tc thc hin lnh theo trt t bnh thng mov cx,9 nhan: lnh 1 lnh 2 lnh 3 loop nhan

LOOPZ/E v LOOPNZ/E
Cc bin th ca LOOP Gi tr ca c ZF c th lm kt thc sm vng lp Loop while ZF/equal && CX!=0 Loop while (NZ/ not equal) && CX!=0 Lu : LOOP gim CX nhng khng nh hung n cc c LOOPZ == LOOPE LOOPNZ==LOOPNE Cc lnh trong vng lp c th tc ng n c ZF (CMP ?)

Chng trnh con

Chng trnh con trong ngn ng Assembly c gi l Th tc (Procedure) Mt th tc c th c thc hin nhiu ln C lin quan n stack: - lu gi a ch quay v - lu gi gi tr ca cc thanh ghi ca vi x l

Stack ?
Cu trc d liu LIFO RWM
- PUSH : ghi d liu vo stack, - POP: c d liu t stack

(SS:SP) tr n nh ca stack (SS:BP) truy cp stack ngu nhin (khng theo LIFO)

Stack Initialization
The .stack directive hides an array allocation statement that looks like this
The_Stack DB Stack_Size dup (?)

On program load
SS is set to a segment address containing this array (usually The_Stack starts at offset 0) SP is set to the offset of The_Stack+Stack_Size which is one byte past the end of the stack array
This is the condition for an empty stack

Initial Stack Configuration

.stack 12 ;Reserve space for the stack Loader determines actual segment address for the start of the stack
This is an empty stack
Stack Size: 000C

SS:0340

SP:000C

How Does The Stack Work?

The stack grows backwards through memory towards the start of the stack segment
Stack Size: 000C

SS:0340

SP:0008

Push decrements stack pointer Pop increments stack pointer

PUSH
PUSH ngun
Push ngun vo stack

PUSHF
Push thanh ghi c vo stack

Lnh PUSH trc ht s gim SP i 2 ri lu gi tr ca ngun vo v tr nh c tr bi (SS:SP)

V d PUSH
Stack Size: 000C
3C 09 A4 40 2C FF A2 43 07 06 4C 2A 09 46

SS:0340

SP:0008

PUSH AX

AX: 0123

3C 09 A4 40 2C FF A2 23 01 06 4C 2A 09 46

SS:0340

SP:0006

POP
POP ch
Pop d liu t nh stack vo ch

POPF
Pop d liu t nh stack vo thanh ghi c

Lnh POP trc ht copy d liu c tr bi (SS:SP) n ch ri tng SP ln 2

V d POP
3C 09 A4 40 2C FF A2 23 01 06 4C 2A 09 46

SS:0340

SP:0006

POP ES
3C 09 A4 40 2C FF A2 23 01 06 4C 2A 09 46

SS:0340
ES: 0123

SP:0008

Trn stack!
Stack Size: 000C

SS:0340

SP:FFFE

Stack Overflow Stack Underflow

Stack Size: 000C

SS:0340

SP:000D

Th tc
Tn_Th_tc PROC kiu ;thn ca th tc RET ;quay v chung trnh gi Tn_Th_tc ENDP

kiu l NEAR hoc FAR

ngm nh l NEAR

Mt th tc c th c nhiu lnh RET

Lnh CALL v RET

Gi mt th tc (NEAR) CALL Tn_Th_tc
push IP vo stack copy a ch ca Tn_Th_tc vo IP

Tr v t mt th tc (NEAR) RET
pop gi tr nh stack vo IP

Th tc Far
Gi th tc (FAR) CALL Tn_th_tc
ln lt push CS v IP vo stack copy a ch ca Tn_th_tc vo CS v IP

Tr v t th tc (FAR) RET
pop gi tr t nh stack ln lt vo IP v CS

Gi ngt
Gi ngt l mt li gi th tc c bit
FAR Thanh ghi c phi c bo ton

INT S ngt
Thanh ghi c c push, TF v IF b xo CS v rI IP c push a ch ca mt chng trnh con phc v ngt (Vector ngt) tng ng vi S ngt c copy vo CS v IP

Tr v t ngt
IRET Tc dng ca lnh:
Gi tr nh ca stack c pop vo IP Gi tr nh ca stack c pop vo CS Gi tr nh ca stack c pop vo thanh ghi c

Chng trnh b ngt tip tc thc hin dng nh khng c chuyn g xy ra

Xut k t ra mn hnh PC
Ngt 21h
Ngt ny h tr rt nhiu dch v trn PC Nhn dng dch v bng s dch v (s hm). S dch v cn c np vo thanh ghi AH Tu theo tng dch v, c th cn thm mt s i s khc c np vo cc thanh ghi xc nh

AH = 2, DL = M ASCII ca k t cn xut
K t c hin th ti v tr hin thI ca con tr

Xut xu k t ra mn hnh PC
Dch v 09h ca ngt 21h
DX = a ch Offset ca xu (trong on d liu) DS = a ch segment ca xu Xu k t phi kt thc bng k t '$'

np a ch offset ca xu vo DX, c th:

LEA MOV DX, Tnxu DX, OFFSET Tn xu

Nhp 1 k t t bn phm PC
Dch v 01h ca ngt 21h Khi NSD g mt k t t bn phm:
K t s hin trn mn hnh AL s cha m ASCII ca k t
AL=0 nu k t c nhp l k t iu khin

Nhm lnh thao tc string

Chng ta hiu: string l mt mng byte hoc t nm trong b nh Cc thao tc string:
Sao chp Tm kim Lu tr So snh

Cc c im
Ngun: (DS:SI), ch: (ES:DI)
DS, ES cha a ch Segment ca string SI, DI cha a ch Offset ca string

C hng DF (0 = Up, 1 = Down)

DF = 0 - Tng a ch (tri qua phi) DF = 1 - Gim a ch (phI qua tri)

Chuyn (Sao chp)

MOVSB, MOVSW
Chuyn 1 byte hoc 1 word t v tr nh ny sang v tr nh khc Tc dng ca lnh:
Sao chp byte/word t (DS:SI) n (ES:DI) Tng/Gim SI v DI 1 hoc 2 gi tr

Nu CX cha mt gi tr khc khng:

REP MOVSB hoc REP MOVSW s t ng sao chp (CX) ln v CX s v khng

V d:Sao chp mng

; Sao chp 10 byte t mng a sang mng b, gi s (DS) = (ES)

mov mov mov cld rep

cx, 10 di, offset b si, offset a ;xo c DF movsb

V d: Tnh tin cc nh
mov mov mov std rep
a

cx, 7 di, offset a+9 si, offset a+6 ;lp c DF movsb SI

DI

V d
pattern
mov mov mov cld rep
SI

db "!@#*" db 96 dup (?) cx,96 si, offset pattern di, offset pattern+4
movsb
DI

! @ # * a

Lu tr string
STOSB, STOSW Copy AL hoc AX vo mt mng byte hoc word
ch (ES:DI)

Thng c s dng c tin t REP v s ln lp trong CX

Tng hoc Gim DI

ph thuc DF

V d:
arr dw 200 dup (?)
mov ax,50A0h mov di,offset arr mov cx,200 cld AX 50 A0 rep stosw

DI

A0 50 A0 50 arr

Np String
LODSB, LODSW
Byte hoc word ti (DS:SI) c copy vo AL hoc AX SI tng hoc gim 1 hoc 2 gi tr ph thuc DF

Thng c dng vi STOSx trong mt vng lp x l tng phn t trong mt mng

V d:
mov di, offset b mov si, offset a mov cx,30 cld lp: lodsb and al,0DFh stosb loop lp

Qut String
SCASB, SCASW So snh AL hoc AX vi byte hoc word tI (ES:DI) v t ng tng hoc gim DI Lnh ny nh hng n cc c trng thi
Tu theo kt qu so snh Dng trong mt vng lp REPs
REPZ, REPE, REPNZ, REPNE

V d
arr db 'abcdefghijklmnopqrstuvwxyz' mov di, offset arr mov cx,26 cld mov al,target repne scasb jne nomatch

So snh String
CMPSB, CMPSW So snh byte hoc word ti (DS:SI) vi byte hoc word tI (ES:DI), tc ng n cc c v tng hoc gim SI v DI Thng dng so snh hai mng vi nhau

V d
mov si, offset str1 mov di, offset str2 cld mov cx, 12 repe cmpsb jl str1smaller jg str2smaller ;the strings are equal - so far ;if sizes different, shorter string is less

Nhm lnh hn hp
- Cc lnh Lp/Xo trc tip cc c:
STC, CLC STD, CLD STI, CLI - Lnh NOP (No Operation): Khng lm g!!! - Lnh NOP thng c dng trong cc vng lp to tr (delay)bng phn mm - Cc lnh Nhp/Xut d liu i vi cc cng I/O IN OUT

Lnh IN
- Nu a ch ca cng Nh hn hoc bng FFh: IN Acc, a ch cng - Trong : Acc c th l AL hoc AX - Nhp d liu t cng vo Acc - Nu a ch ca cng Ln hn FFh: MOV DX, a ch cng IN Acc, DX - Trong : Acc c th l AL hoc AX - Nhp d liu t cng vo Acc

Lnh OUT
- Nu a ch ca cng Nh hn hoc bng FFh: OUT a ch cng, Acc - Trong : Acc c th l AL hoc AX - Xut d liu t Acc ra cng - Nu a ch ca cng Ln hn FFh: MOV DX, a ch cng OUT DX, Acc - Trong : Acc c th l AL hoc AX - Xut d liu t Acc ra cng

Tm tt chng
- Tnh tng thch v Cu trc thanh ghi ca cc vi x l h x86 - Tnh tng thch v Tp lnh ca cc vi x l h x86

K thut Vi x l
in t-Vin thng i hc Bch khoa Nng

Chng 4
4.1 4.2 4.3 4.4 4.5 Phn loi b nh bn dn Hot ng ca cc chip EPROM Hot ng ca cc chip SRAM Bus h thng ca h vi x l 8088 Bi ton thit k b nh

Mc

tiu v bin php thit k

Ghp ni cc chip nh EPROM v SRAM vi Bus h thng sao cho khng xy ra xung t: Cc chip nh b cm khi vi x l truy cp cc cng I/O Ch c mt chip nh hot ng khi vi x l truy cp b nh Thc hin mt mch gii m a ch b nh dng cc chip gii m hoc cc cng logic hoc kt hp c hai

4.1 Phn loi b nh bn dn

B nh bn dn
(Semiconductor memory)

SAM (Sequential Access Memory)

RAM

(Random Access Memory)

ROM (Read Only Memory)

RWM (Read Write memory)

PROM

EPROM

SRAM

DRAM

4.2 Cc chip EPROM

A0 A1 A2 A3 A4 A5 A6 A7 A8 A p-1 D0 D1 D2 D3 D4 D5 D6 D m-1

m chn d liu

p chn a ch

EPROM

iu khin c
Chn chip Cc chn iu khin

OE PGM CE Vpp

Dung lng ca 1 chip nh

Mt chip nh c xem nh mt mng gm n nh. Mi nh lu tr c m-bit d liu Dung lng ca chip thng c biu din: nxm V d: Mt chip c dung lng 2Kx8 ngha l chip c 2048 nh v mi nh c th lu tr c 1 byte d liu m chnh l s chn d liu ca chip log2(n) = p l s chn a ch ca chip

Hot ng ghi d liu vo EPROM

Vic ghi d liu vo EPROM c gi l lp trnh cho EPROM c thc hin bng thit b chuyn dng gi l B np EPROM Chn Vpp c cp in p tng ng vi tng loi chip gi l in p lp trnh D liu ti cc chn d liu s c ghi vo mt nh xc nh nh cc tn hiu a vo cc chn a ch v mt xung (thng gi l xung lp trnh) a vo chn PGM

Hot ng c d liu t mt chip EPROM c d liu t 1 nh no ca 1 chip EPROM no , B vi x l cn phi:

Chn chip : 0 -----> CE

p cc tn hiu a ch ca nh cn c vo cc
chn a ch Ap-1 A0 c: 0 ------ > OE Kt qu l m bit d liu cn c xut hin cc chn d liu Dm-1 D0

H EPROM thng dng 27x

S hiu ca chip 2716 2732 2764 27128 27256 Dung lng 2Kx8 4Kx8 8Kx8 16Kx8 32Kx8

27512
Bng 4.1 H EPROM 27x

64Kx8

EPROM 1 A7 A6 A5 A4 A3 A2 A10 __ Vcc A8 A9 24

2716

2732

23
22 21 20 19 Vpp __
OE

S chn ca 2716 v 2732

3 4 5 6

A11
__
OE / Vpp

7
8 9 10 11 12

A1
A0 D0 D1 D2

CE/PGM 18

D7 D6 D5 D4

17 16 15 14 13

GND

D3

EPROM 2764
Cc chn a ch

Cc chn d liu Chn chip

iu khin c

EPROM 2764

Lp trnh cho 2764

Trc ht cn phi xo
Xo mt chip tc l lm cho tt c cc bit = 1

Xo mt chip EPROM bng tia cc tm Lp trnh bng cch:

VPP mc mc 12.5V E v P u mc thp TTL

Cc bit d liu a vo cc chn d liu Cc bit a ch a vo cc chn a ch

4.3 Cc chip SRAM

A0 A1 A2 A3 A4 A5 A6 A7 A8 A p-1 D0 D1 D2 D3 D4 D5 D6 D m-1

P chn a ch

m chn d liu

SRAM

iu khin c Chn chip iu khin ghi

OE CS
WE

c d liu t mt chip SRAM

c d liu t 1 nh no ca 1 chip SRAM no , vi x l cn phi:

Chn chip : 0 -----------> CS p cc tn hiu a ch vo Ap-1 A0 c: 0 ----------- > OE

Kt qu l m bit d liu cn c xut hin cc chn d liu Dm-1 D0

Ghi d liu vo mt chip SRAM

ghi m bit d liu vo 1 nh no ca 1 chip SRAM no , vi x l cn phi: Chn chip : 0 --------> CS p cc tn hiu a ch vo Ap-1 A0 p m bit d liu cn ghi vo cc chn d liu Dm-1 D0 Ghi: 0 --------- > WE Kt qu l cc bit d liu cc chn d liu s c ghi vo nh chn

SRAM 6264
Dung lng 8Kx8 8 chn d liu 13 chn a ch Hai chn chn chip Chn iu khin c Chn iu khin ghi

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 OE WE CS1 CS2 I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7

6264

32K x 8 Static RAM

1 2 3 4 5 6 7 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 Vcc __ WE A13 A8 A9 A11 __ OE A10
CE

28 27 26 25 24 23 22

8
9

21
__ 20

10
11 12 13 14

D7

19
18 17 16 15

D0
D1 D2 GND 51256S

D6
D5 D4 D3

S khi 6264

Chc nng ca 6264

4.4 Bus h thng ca 8088

Bus a ch 20-bit: gm cc ng a ch c k hiu t A19 n A0 Bus d liu 8-bit: gm cc ng d liu c k hiu t D7 n D0 Bus iu khin gm cc ng iu khin ring l phc v cho hot ng truy cp b nh v cc cng I/O, mi ng thng c k hiu bng tn ca tn hiu iu khin Bus h thng khng ni trc tip vi cc chn ca 8088: thng qua cc mch m, cht.

80x86 Microprocessors
Product Year Introduced Technology Clock Rate Number of Pins Number of transistors Number of instructions Physical Memory Virtual Memory 8008 1972 PMOS 0.50.8 18 3000 66 16K none 808 0 1974 NMO S 2-3 40 4500 111 64K none 808 5 1976 NMO S 3-8 40 6500 113 64K none 808 6 1978 NMO S 5-10 40 29K 133 1M none 808 8 1979 NMO S 5-8 40 29K 133 1M none 16M 1G 16M4GB 64T 4GB 64T 4GB 64T 64G 64T 130K 8028 6 1982 NMOS 1016? 80386 1985 CMOS 16-40 132 275K 80486 1989 CMOS 66 168 1.2M Pent. 1992 BICMO S 6066+ 273 3M Pent. Pro 1995 BICMO S 150 387 5.5M

Internal Data Bus

External Data Bus Address Bus Data Types

8
8 8 8

8
8 16 8

8
8 16 8

16
16 20 8,16

16
8 20 8,16

16
16 24 8,16

32
16,32 24,32 8,16,32

32
32 32 8,16,3 2

64
64 32 8,16,3 2

32
64 36 8,16,3 2

8088/8086 Microprocessor

DIP 40 pin Data bus

Bus d liu trong :16 bit Bus d liu ngoi ca 8088: 8 bit dng AD0-AD7 Bus d liu ngoi ca 8086:16 bit dng AD0-AD15 ALE (Address Latch Enable)

8088/8086 Microprocessor

Bus a ch
ALE = 1 S dng 74LS373 tch v cht a ch

u vo: AD0-AD7 (8088) hoc AD0-AD15 (8086) v ALE u ra: A0-A7 (8088) hoc A0-A15 (8086)

S chn ca 8088

S chn 8088/8086 (Min Mode)

Minimum/Maximum Mode

nh hng n cc chn 24-31 Minimum Mode

Cc chn 24-31 l cc tn hiu iu khin I/O v b nh Cc tn hiu iu khin u t 8088/8086 Tng t vi 8085A

Maximum Mode
Mt s tn hiu iu khin c to ra t ngoi Mt s chn c thm chc nng mi Khi c dng b ng x l ton 8087

S chn ca 8088
MN / MX READY CLK RESET TEST HLDA A8 HOLD NM I A9 A10 A11 A12 A13 A14 A15 A16 / S3 A17 / S4 A18 / S5 A19 / S6 SSO DEN DT / R IO / M RD WR ALE INTR INTA AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7

8088

Tn hiu cc chn ca 8088

MN / MX READY CLK RESET TEST HLDA A8 HOLD NM I A9 A10 A11 A12 A13 A14 A15 A16 / S3 A17 / S4 A18 / S5 A19 / S6 SSO DEN DT / R IO / M RD WR ALE INTR INTA AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7

Cc chn a ch/D liu

Cc chn a ch

8088

Cc chn a ch/Trng thi

Cho php cht a ch

Cc chn a ch/D liu

Cc chn AD7 n AD0 K thut Multiplexing: Tn hiu cc chn ny lc ny l tn hiu a ch, lc khc l tn hiu d liu ph thuc vo tn hiu iu khin ALE (Address Latch Enable): ALE = 1: AD7 n AD0 = A7 n A0 ALE = 0: AD7 n AD0 = D7 n D0

Cc chn a ch v Cc chn a ch/Trng thi

Cc chn a ch: A15 n A8 Tn hiu cc chn ny lun l tn hiu a ch Cc chn a ch/trng thi: A19/S6 n A16/S3: ALE = 1: A19 n A16 ALE = 0: S6 n S3

Processor Timing Diagram of 8088 (Minimum Mode) for Memory or I/O Read (with 74245)
T1 CLOCK
__

T2

T3

T4

DT/R ALE D7 - D0
from memory to 74LS245

D7 - D0 (from memory)
D7 - D0 from 74LS245

AD7 - AD0 A15 - A8

A7 - A0

garbage

A15 - A8

A19/S6 - A16/S3
A19 - A0
from 74LS373 to memory __

A19 - A16

S6 - S3

A19 - A0 from 74LS373

IO/M
____

if I/O ACCESS this is HIGH, if MEMORY ACCESS this is LOW

RD
______

DEN

M t chn

BHE Bus High Enable Phn bit byte thp v byte cao ca mt t (ch vi 8086)

M t chn

NMI Non Maskable Interrupt u vo ngt khng che c

M t chn

INTR Interrupt Request u vo ngt che c Ni vi chip iu khin ngt 8259 INTA: chp nhn ngt

M t chn

CLK Clock u vo ng h Ni vi chip 8284

M t chn

RESET Kt thc hot ng hin thi v huy b mi th Sau khi reset

CS=FFFFH DS=0000H SS=0000H ES=0000H IP=0000H Cc c b xo Hng I lnh rng

M t chn

READY Chn thm mt trng thi i (wait state)

M t chn

TEST n t 8087 (B ng x l) ng b 8088 v 8087

M t chn

MN/MX Minimum mode = +5V Maximum mode = Gnd

M t chn Max

QS0, QS1 Queue status Trng thi ca hng i lnh:

00 No operation 01 first byte of opcode from queue 10 empty the queue 11 subsequent byte from queue

M t chn Max

S0, S1, S2 Status Signal Pins (S2S0)

000 INTA interrupt acknowledge 001 IORC read I/O port 010 IOWC write I/O port 011 none - halt 100 MRDC code access 101 MRDC read memory 110 MWTC write memory 111 none - passive

M t chn Max

LOCK Locks processor to system bus Gain the lock by using LOCK prefix on an assembly instruction Used with status signals to prevent DMA from gaining control of the buses

M t chn Max

RQ/GT0, RQ/GT1 Request/Grant Bi-directional Gain control of local bus RQ/GT0 normally permanently high (disabled) RQ/GT1 is connected to the 8087

M t chn Min

INTA Interrupt acknowledge Chp nhn ngt

M t chn Min

ALE Address Latch Enable Tn hiu cc chn a ch/D liu v cc chn a ch/Trng thi lc ALE = 1 l cc tn hiu a ch

M t chn

AD0-AD7 Cc chn a ch/D liu Tn hiu cc chn ny l 8 bit a ch thp A0 n A7 khi ALE =1, l 8 bit d liu D0 n D7 khi ALE = 0

74LS373
D0 D1 D2 D3 D4 D5 D6 D7 OE LE Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7

74LS373

74LS373

Dng 74LS373 tch v cht a ch

M t chn Min

DEN Data Enable D liu c ngha

M t chn Min

DT/R iu khin hng ca tn hiu d liu: 1: Tn hiu d liu i ra t 8088 0: Tn hiu d liu i vo 8088

M t chn Min

IO/M Phn bit: truy cp I/O hay B nh

1: 8088 truy cp I/O 0: 8088 truy cp b nh

M t chn Min

WR 0: Tn hiu trn bus d liu c ghi vo b nh hoc I/O Ghi b nh: ? Xut d liu ra cng: ?

M t chn Min

HLDA Hold Acknowledge 0: Chp nhn yu cu DMA HOLD

Bo cho B iu khin DMA c php s dng bus h thng

M t chn Min

HOLD Nhn tn hiu yu cu DMA t B iu khin DMA (DMAC) DMAC mun s dng bus h thng

M t chn Min

SSO 8088 Dng vi IO/M v DT/R xc nh trng thi ca chu k bus hin thi

Cc tn hiu iu khin

C th s dng cc cng logic to ra cc tn hiu iu khin khc t cc tn hiu iu khin sn c

3 Tn hiu:

RD, WR and IO/M

RD W R 0 1

IO/M Signal 0 MEMR

1
0 1 0

0
1 0 0

0
1 1 X

MEMW
IOR IOW Never happens

To ra cc tn hi iu khin (Min Mode)

To ra cc tn hi iu khin (Min Mode)

8088 Bus Min Mode

74LS245
A0 A1 A2 A3 A4 A5 A6 A7 B0 B1 B2 B3 B4

74LS245

B5 B6 B7

DIR

Bus h thng ca h 8088 Mode Minimum

A7 - A0 DEN DT / R E DIR B7 - B0 D7 - D0

74LS245
Q7 - Q0

Bus d liu

Bus a ch

AD7 - AD0 GND

D7 - D0 OE LE

A7 - A0 A15 - A8 A19 - A16

74LS373
Q7 - Q0

A15 - A8

D7 - D0 GND OE LE

8088
A19/S6 - A16/ S3

74LS373
Q7 - Q4 Q3 - Q0

MEMORY

D7 - D4 D3 - D0 GND OE LE

ALE RD IO / M WR

74LS373
RD

MEMR
WR

MEMW

Minimum Mode 8088

D7 - D0 D7 - D0

A19 - A0

A19 - A0

8088 Minimum Mode

B nh c chn khi no?

MEMORY

MEMR

RD

MEMW

WR

Minimum Mode 8088

D7 - D0

220 nh (1MB)
D7 - D0

A19 - A0

A19 - A0

8088 Minimum Mode

MEMORY

MEMR

RD

MEMW

WR

CS

Khng gian a ch b nh 1M
A19 n A0 (HEX) 00000 FFFFF AAAA 1111 9876 0000 1111 AAAA 1111 5432 0000 1111 AAAA 1198 1000 0000 1111 AAAA 7654 AAAA 3210

0000 1111

0000 1111

V d: Mt a ch bt k 34FD0h 0011 0100 11111 1101 0000

B nh y 1MB
AX BX CX DX CS SS DS ES BP SP SI DI IP 3F1C 0023 0000 FCA1 XXXX XXXX 2000 XXXX XXXX XXXX XXXX XXXX XXXX MEMR RD FFFFF FFFFE FFFFD A19 : A0 A19 : A0 : : 20023 20022 20021 20020 : : 10008 10007 10006 10005 10004 10003 10002 10001 10000 MEMW WR : : 00001 00000 36 25 19 : : 13 7D 12 29 : : 8A F4 07 88 42 39 27 98 45 : : 95 23

D7 : D0

D7 : D0

CS

Nu ch cn b nh c dung lng nh hn 1MB th gii quyt nh th no?

Ph thuc vo cc chip nh sn c Ph thuc yu cu phn b a ch cho cc loi b nh vt l khc nhau

512K u tin ca khng gian a ch b nh (Cc a ch c bit cao nht A19 = 0)

A18 n A0 (HEX) 00000 7FFFF

AAAA 1111 9876 0000 0111

AAAA 1111 5432 0000 1111

AAAA 1198 1000 0000 1111

AAAA 7654

AAAA 3210

0000 1111

0000 1111

512K tip theo ca khng gian a ch b nh (Cc a ch c bit cao nht A19 = 1)

A18 n A0 (HEX) 80000 FFFFF

AAAA 1111 9876 1000 1111

AAAA 1111 5432 0000 1111

AAAA 1198 1000 0000 1111

AAAA 7654

AAAA 3210

0000 1111

0000 1111

B nh 512KB

AX BX CX DX CS SS DS ES BP SP SI DI IP

3F1C 0023 0000 FCA1 XXXX XXXX 2000 XXXX XXXX XXXX XXXX XXXX XXXX CS

Lm g vi A19?
A19 A18 : A0 D7 : D0 MEMR MEMW A18 : A0 D7 : D0 RD WR 7FFFF 7FFFE 7FFFD : : 20023 20022 20021 20020 : : 00001 00000 36 25 19 : : 13 7D 12 29 : : 95 23

iu g xy ra nu 8088 c nh A0023h?
AX BX CX DX CS SS DS ES BP SP SI DI IP 3F1C 0023 0000 FCA1 XXXX XXXX A000 XXXX XXXX XXXX XXXX XXXX XXXX CS

A19 A18 : A0 D7 : D0 MEMR MEMW

A18 : A0 D7 : D0 RD WR

7FFFF 7FFFE 7FFFD : : 20023 20022 20021 20020 : : 00001 00000

36 25 19 : : 13 7D 12 29 : : 95 23

MOV AH, [BX]

iu g xy ra nu 8088 c nh A0023h?

A19 n A0 (HEX) A0023

AAAA 1111 9876 1010

AAAA 1111 5432 0000

AAAA 1198 1000 0000

AAAA 7654

AAAA 3210

0010

0011

A19 khng c ni n b nh nn nu 8088 pht logic 1 trn A19 th b nh cng khng nhn bit c.

iu g xy ra nu 8088 c nh 20023h?

A18 n A0 (HEX) 20023

AAAA 1111 9876 0010

AAAA 1111 5432 0000

AAAA 1198 1000 0000

AAAA 7654

AAAA 3210

0010

0011

Vi b nh tnh hnh khng c g khc!

Nu B nh gm 2 khi 512KB nh th ny?

AX BX CX DX CS SS DS ES BP SP SI DI IP 3F1C 0023 0000 FCA1 XXXX XXXX 2000 XXXX XXXX XXXX XXXX XXXX XXXX A18 : A0 D7 : D0 RD WR CS 7FFFF 7FFFE 7FFFD : 20023 20022 20021 20020 : 00001 00000 12 98 2C : 33 45 92 A3 : D4 97 A19 A18 : A0 D7 : D0 MEMR MEMW A18 : A0 D7 : D0 RD WR CS 7FFFF 7FFFE 7FFFD : 20023 20022 20021 20020 : 00001 00000 36 25 19 : 13 7D 12 29 : 95 23

C vn !!!

Vn l: Xung t Bus. Hai khi nh s cung cp d liu cng mt lc khi 8088 c b nh Gii php: Dng A19 lm ngi phn x gii quyt xung t trn bus. Nu A19 mc logic 1 th khi nh trn hot ng (khi nh di b cm) v ngc li

B nh gm hai khi nh 512KB

AX BX CX DX CS SS DS ES BP SP SI 3F1C 0023 0000 FCA1 XXXX XXXX 2000 XXXX XXXX XXXX XXXX 7FFFF 12 A19 A18 : A0 D7 : D0 MEMR MEMW A18 : A0 D7 : D0 RD WR CS 7FFFF 7FFFE 7FFFD : 20023 20022 20021 20020 : 00001 00000 36 25 19 : 13 7D 12 29 : 95 23

DI
IP

XXXX
XXXX

A18
: A0 D7

7FFFE
7FFFD : 20023 20022 20021 20020 : 00001 00000

98
2C : 33 45 92 A3 : D4 97

:
D0 RD WR CS

Khng gian a ch b nh 1M
A19 n A0 (HEX) 00000 7FFFF 80000 AAAA 1111 9876 0000 0111 1000 AAAA 1111 5432 0000 1111 0000 AAAA 1198 1000 0000 1111 0000 AAAA 7654 AAAA 3210

0000 1111 0000

0000 1111 0000

FFFFF

1111

1111

1111

1111

1111

B nh gm hai khi nh 512KB

AX BX CX DX CS SS DS ES BP SP SI DI IP 3F1C 0023 0000 FCA1 XXXX XXXX 2000 XXXX XXXX XXXX XXXX XXXX XXXX A19 A18 : A0 D7 : D0 MEMR MEMW A18 : A0 D7 : D0 RD 7FFFF 7FFFE 7FFFD : 20023 20022 20021 20020 : 00001 00000 36 25 19 : 13 7D 12 29 : 95 23

Khi P xut mt a ch t 80000h to 00000h n 7FFFFh, FFFFFh, B nh ny hot ng

WR CS

7FFFF A18 : A0 D7 : D0 RD WR CS 7FFFE 7FFFD : 20023 20022 20021 20020 : 00001 00000

12 98 2C : 33 45 92 A3 : D4 97

B nh gm hai khi nh 512KB

AX BX CX DX CS SS DS ES BP SP SI DI IP 3F1C 0023 0000 FCA1 XXXX XXXX 2000 XXXX XXXX XXXX XXXX XXXX XXXX A18 : A0 D7 : D0 RD WR CS 7FFFF 7FFFE 7FFFD : 20023 20022 20021 20020 : 00001 00000 12 98 2C : 33 45 92 A3 : D4 97 A19 A18 : A0 D7 : D0 MEMR MEMW A18 : A0 D7 : D0 RD WR CS 7FFFF 7FFFE 7FFFD : 20023 20022 20021 20020 : 00001 00000 36 25 19 : 13 7D 12 29 : 95 23

Thit k B nh cho H vi x l
AX BX CX DX CS SS DS ES BP SP SI DI IP 3F1C 0023 0000 FCA1 XXXX XXXX 2000 XXXX XXXX XXXX XXXX XXXX XXXX A19 A18 : A0 D7 : D0 MEMR MEMW A19 A18 : A0 D7 : D0 RD WR A18 : A0 D7 : D0 7FFFF 7FFFE 7FFFD : 20023 20022 20021 20020 36 25 19 : 13 7D 12 29 : 95 23

Ghp ni cc chip nh: RD WR ring l vi Bus h 00001 CS 00000 thng sao cho khng xy ra xung t nh7FFFF A18 7FFFE mch gii m a ch : 7FFFD A0 : b nh
D7 : D0 RD WR CS 20023 20022 20021 20020 : 00001 00000

12 98 2C : 33 45 92 A3 : D4 97

Nu b i khi nh bn di?
AX BX CX DX CS SS DS ES BP SP SI DI IP 3F1C 0023 0000 FCA1 XXXX XXXX 2000 XXXX XXXX XXXX XXXX XXXX XXXX A18 : A0 D7 : D0 RD WR CS 7FFFF 7FFFE 7FFFD : 20023 20022 20021 20020 : 00001 00000 12 98 2C : 33 45 92 A3 : D4 97 A19 A18 : A0 D7 : D0 MEMR MEMW A18 : A0 D7 : D0 RD WR CS 7FFFF 7FFFE 7FFFD : 20023 20022 20021 20020 : 00001 00000 36 25 19 : 13 7D 12 29 : 95 23

Nu b i khi nh bn di th
AX BX CX DX CS SS DS ES BP SP SI DI IP 3F1C 0023 0000 FCA1 XXXX XXXX 2000 XXXX XXXX XXXX XXXX XXXX XXXX A19 A18 : A0 D7 : D0 MEMR MEMW A18 : A0 D7 : D0 7FFFF 7FFFE 7FFFD : 20023 20022 20021 20020 : 00001 00000 36 25 19 : 13 7D 12 29 : 95 23

Khi P xut ra mt da Khi P xut ra mt a ch t 00000h n ch t 80000h n 7FFFFh, Khng c FFFFFh, Chip nh chiphot ng ny nh no hot ng!

RD WR CS

Gii m y v khng y

Gii m y (Full Decoding)

Tt c cc ng a ch c ngha u c s dng vo mch gii m Mi nh ch c mt a ch vt l duy nht

Gii m khng y (Partial Decoding)

Khng phi tt c cc ng a ch c ngha u c s dng vo mch gii m Mt nh c hn mt a ch vt l

Gii m y
AX BX CX DX CS SS DS ES BP SP SI DI IP 3F1C 0023 0000 FCA1 XXXX XXXX 2000 XXXX XXXX XXXX XXXX XXXX XXXX A19 A18 : A0 D7 : D0 MEMR MEMW A18 : A0 D7 : D0 RD WR CS 7FFFF 7FFFE 7FFFD : 20023 20022 20021 20020 : 00001 00000 36 25 19 : 13 7D 12 29 : 95 23

Gii m y
A19 n A0 (HEX) 80000 FFFFF AAAA 1111 9876 1000 1111 AAAA 1111 5432 0000 1111 AAAA 1198 1000 0000 1111 AAAA 7654 AAAA 3210

0000 1111

0000 1111

A19 phi mc 1 th chip nh mi hot ng (c chn)

Gii m y
A19 n A0 (HEX) 00000 7FFFF AAAA 1111 9876 0000 0111 AAAA 1111 5432 0000 1111 AAAA 1198 1000 0000 1111 AAAA 7654 AAAA 3210

0000 1111

0000 1111

Do , nu vi x l pht ra mt a ch t 00000h n 7FFFFh (A19 mc logic 0) chip nh s khng c chn.

Gii m khng y
AX BX CX DX CS SS DS ES BP SP SI DI IP 3F1C 0023 0000 FCA1 XXXX XXXX 2000 XXXX XXXX XXXX XXXX XXXX XXXX CS

A19 A18 : A0 D7 : D0 MEMR MEMW

A18 : A0 D7 : D0 RD WR

7FFFF 7FFFE 7FFFD : : 20023 20022 20021 20020 : : 00001 00000

36 25 19 : : 13 7D 12 29 : : 95 23

Gii m khng y
A19 n A0 (HEX) 00000 7FFFF 80000 AAAA 1111 9876 0000 0111 1000 AAAA 1111 5432 0000 1111 0000 AAAA 1198 1000 0000 1111 0000 AAAA 7654 AAAA 3210

0000 1111 0000

0000 1111 0000

FFFFF

1111

1111

1111

1111

1111

A19 khng c ngha vi chip nh

Gii m khng y
A19 n A0 (HEX) 00000 7FFFF 80000 AAAA 1111 9876 0000 0111 1000 AAAA 1111 5432 0000 1111 0000 AAAA 1198 1000 0000 1111 0000 AAAA 7654 AAAA 3210

0000 1111 0000

0000 1111 0000

FFFFF

1111

1111

1111

1111

1111

a ch thc t

Gii m khng y
A19 n A0 (HEX) 00000 7FFFF 80000 AAAA 1111 9876 0000 0111 1000 AAAA 1111 5432 0000 1111 0000 AAAA 1198 1000 0000 1111 0000 AAAA 7654 AAAA 3210

0000 1111 0000

0000 1111 0000

FFFFF

1111

1111

1111

1111

1111

a ch thc t

B nh gm 2 chip 512Kx8
A19 A18 : A0 D7 : D0 MEMR MEMW A18 : A0 D7 : D0 RD WR CS

512KB #2

8088 Minimum Mode

A18 : A0 D7 : D0 RD WR CS

512KB #1

B nh ch c mt chip 512Kx8 (Ver. 1)

A19 A18 : A0 D7 : D0 MEMR MEMW A18 : A0 D7 : D0 RD WR CS

512KB

8088 Minimum Mode

B nh ch c mt chip 512Kx8 (Ver. 2)

A19 A18 : A0 D7 : D0 MEMR MEMW A18 : A0 D7 : D0 RD WR CS

512KB

8088 Minimum Mode

B nh ch c mt chip 512Kx8 (Ver. 3)

A19 A18 : A0 D7 : D0 MEMR MEMW A18 : A0 D7 : D0 RD WR CS

512KB

8088 Minimum Mode

A17

B nh gm 4 chip 256Kx8
A19 A18 A17
:

A0 D7
:

D0 RD WR CS A17
:

256KB #4

A0 D7
:

A0 D7
:

D0 MEMR MEMW

D0 RD WR CS A17
:

256KB #3

8088 Minimum Mode

A0 D7
:

D0 RD WR CS A17
:

256KB #2

A0 D7
:

D0 RD WR CS

256KB #1

A17

B nh gm 4 chip 256Kx8
A19 A18 A17
:

A0 D7
:

D0 RD WR CS A17
:

256KB #4

A0 D7
:

A0 D7
:

D0 MEMR MEMW

D0 RD WR CS A17
:

256KB #3

8088 Minimum Mode

A0 D7
:

D0 RD WR CS A17
:

256KB #2

A0 D7
:

D0 RD WR CS

256KB #1

Di a ch ca chip #1
A19 AAAA n 1111 A0 9876 (HEX) ----- ---AAAA 1111 5432 AAAA 1198 1000 AAAA 7654 AAAA 3210

----

----

----

----

----- ----

----

----

----

----

Di a ch ca chip #2
A19 AAAA n 1111 A0 9876 (HEX) ----- ---AAAA 1111 5432 AAAA 1198 1000 AAAA 7654 AAAA 3210

----

----

----

----

----- ----

----

----

----

----

Di a ch ca chip #3
A19 AAAA n 1111 A0 9876 (HEX) ----- ---AAAA 1111 5432 AAAA 1198 1000 AAAA 7654 AAAA 3210

----

----

----

----

----- ----

----

----

----

----

Di a ch ca chip #4
A19 AAAA n 1111 A0 9876 (HEX) ----- ---AAAA 1111 5432 AAAA 1198 1000 AAAA 7654 AAAA 3210

----

----

----

----

----- ----

----

----

----

----

B nh gm 4 chip 256Kx8 dng cc cng logic

A19 A18 A17
:

A17
:

A0 D7
:

D0 RD WR CS A17
:

256KB #4

A0 D7
:

A0 D7
:

D0 MEMR MEMW

D0 RD WR CS A17
:

256KB #3

8088 Minimum Mode

A0 D7
:

D0 RD WR CS A17
:

256KB #2

A0 D7
:

D0 RD WR CS

256KB #1

B nh gm 4 chip 256Kx8 dng cc cng logic

A19 A18 A17
:

A17
:

A0 D7
:

D0 RD WR CS A17
:

256KB #4

A0 D7
:

A0 D7
:

D0 MEMR MEMW

D0 RD WR CS A17
:

256KB #3

8088 Minimum Mode

A0 D7
:

D0 RD WR CS A17
:

256KB #2

A0 D7
:

D0 RD WR CS

256KB #1

B nh gm 4 chip 256Kx8 dng mt chip gii m 2-4

A19 A18 A17
:

A17
:

A0 D7
:

D0 RD WR I1 I0 O3 CS A17
:

256KB #4

A0 D7
:

A0 D7
:

D0 MEMR MEMW

D0 RD WR O2 CS A17
:

256KB #3

8088 Minimum Mode

A0 D7
:

D0 RD WR O1 CS A17
:

256KB #2

A0 D7
:

D0 RD WR O0 CS

256KB #1

A12

Ghp ni cc chip nh 8Kx8 vi P 8088

A19 A18 A17 A16 A15 A14 A13 A12

:

A0 D7
:

D0 RD WR CS

8KB #?

A0 D7
:

8088 Minimum Mode

D0 MEMR MEMW

: :
A12
:

A0 D7
:

D0 RD WR CS A12
:

8KB #2

A0 D7
:

D0 RD WR CS

8KB #1

A12
:

B nh gm 128 chip 8Kx8

A19 A18 A17 A16 A15 A14 A13 A12

:

A0 D7
:

D0 RD WR CS

8KB #128

A0 D7
:

8088 Minimum Mode

D0 MEMR MEMW

: :
A12
:

A0 D7
:

D0 RD WR CS A12
:

8KB #2

A0 D7
:

D0 RD WR CS

8KB #1

A12
:

B nh gm 128 chip 8Kx8

A19 A18 A17 A16 A15 A14 A13 A12

:

A0 D7
:

D0 RD WR CS

8KB #128

A0 D7
:

8088 Minimum Mode

D0 MEMR MEMW

: :
A12
:

A0 D7
:

D0 RD WR CS A12
:

8KB #2

A0 D7
:

D0 RD WR CS

8KB #1

Di a ch ca Chip #__
A19 AAAA n 1111 A0 9876 (HEX) ----- ---AAAA 1111 5432 AAAA 1198 1000 AAAA 7654 AAAA 3210

----

----

----

----

----- ----

----

----

----

----

A12
:

B nh gm 128 chip 8Kx8

A19 A18 A17 A16 A15 A14 A13 A12

:

A0 D7
:

D0 RD WR CS

8KB #128

A0 D7
:

8088 Minimum Mode

D0 MEMR MEMW

: :
A12
:

A0 D7
:

D0 RD WR CS A12
:

8KB #2

A0 D7
:

D0 RD WR CS

8KB #1

Pht biu bi ton

Thit k b nh cho h vi x l 8088 tho mn cc yu cu: ROM c dung lng 2Kx8 chim dng cc a ch t FFFFFh tr xung RWM c dung lng 2Kx8 chim dng cc a ch tip theo ngay sau ROM Ch c php s dng: EPROM 2716 2Kx8, SRAM 4016 2Kx8 Chip gii m 74LS138 v cc cng logic

Bc 1: V bn b nh cn thit k
FFFFFh

ROM

2K

FF800h FF7FFh Cc a ch bin

RWM

2K

FF000h

Cha s dng 00000h

Bc 2: Chuyn cc a ch bin t H sang B A19 n A0 (HEX) FF800 FFFFF AAAA 1111 9876 AAAA 1111 5432 AAAA 1198 1000 AAAA 7654 AAAA 3210

1111
1111

1111
1111

1000
1111

0000
1111

0000
1111

Bc 2: Chuyn cc a ch bin t H sang B A19 n A0 (HEX) FF000 AAAA 1111 9876 AAAA 1111 5432 AAAA 1198 1000 AAAA 7654 AAAA 3210

1111 1111

1111 1111

0000 0111

0000 1111

0000 1111

FF7FF

Nhn xt

Khi cc a ch dnh cho ROM c pht ln A-Bus: A19 A12 = 1 v A11 = 1 Khi cc a ch dnh cho RWM c pht ln A-Bus: A19 A12 = 1 v A11 = 0

Bc 3: V mch gii m a ch b nh

Ghp cc chn d liu ca cc chip nh vi D-Bus Ghp cc chn a ch v cc chn iu khin: Khi vi x l truy cp cc cng I/O th cc chip nh b cm (Khi IO/M = 1) Khi vi x l truy cp b nh (IO/M = 0) th ch c mt chip nh lm vic C th c nhiu li gii khc nhau

74LS138: Mt chip gii m 3-8

C B A

Y0 Y1 Y2 Y3 Y4 Y5

U1 74LS138 74LS138
A2 A1 A0 E3 E2 E1 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0

74LS138

G1 G2A G2B

Y6 Y7

B nh cn thit k
A11
:

A19 A18 A17

:

A0 D7
:

D0 MEMR MEMW

C B A
74LS138

8088 Minimum Mode

G1 G2A G2B

Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7

A0 D7
:

2Kx8 4016

D0 OE WE CS

A11
:

A0 D7
:

2Kx8 2716

D0 OE CE

Bi ging K thut Vi x l
Ngnh in t-Vin thng i hc Bch khoa Nng ca H Vit Vit, Khoa TVT

Ti liu tham kho [1] K thut vi x l, Vn Th Minh, NXB Gio dc, 1997 [2] K thut vi x l v Lp trnh Assembly cho h vi x l, Xun Tin, NXB Khoa hc & k thut, 2001

Chng 5 Thit k cc cng I/O

5.1 I/O c phn vng nh v I/O tch bit
- I/O c phn vng nh (Memory Mapped I/O) - I/O tch bit (Isolated I/O)

5.2 Cc chip MSI dng lm cng I/O

- Cng ra - Cng vo

5.3 Chip 8255

- S chn, S khi chc nng - Cc mode hot ng - Gii m a ch - Lp trnh cho 8255

5.1 Cn phn bit 2 kiu thit k

I/O c phn vng nh (Memory mapped I/O): - 1 cng c xem nh mt nh - 1 cng c a ch 20-bit - c truy cp khi IO/M = 0 - khng cn mch gii m a ch ring I/O tch bit (isolated I/O) - 1 cng c xem ng l 1 cng - 1 cng c a ch 16-bit, 12-bit, 8-bit - c truy cp khi IO/M = 1 - cn mch gii m a ch I/O ring

5.2 Cc chip MSI thng dng lm cng I/O

74LS373 74LS374 74LS244 74LS245 Khi s lng cng t v c nh Cch mc mch s quyt nh cho chip l cng ra hay cng vo v a ch ca n

S dng 74LS245 lm cng ra

A19

A18 : A0
D7 D6 D5 A0 A1 A2 B0 B1 B2

8088 Minimum Mode

D4 D3 D2 D1 D0

A3 B3 A4 B4 74LS245 B5 A5 A6 B6 A7 B7
E DIR 5V

IOR IOW

A A A A A A A A A A A A A A A A IOW 1111119876543210 543210

: mov al, 55 mov dx, F000 out dx, al :

S dng 74LS373 lm cng ra

A19 A18

: A0
D7 D6 D5 D4 D0 D1 D2 D3 D4 D5 D6 D7 LE IOR IOW Q0 Q1 Q2 Q3 Q4 Q6 Q7 OE

8088 Minimum Mode

D3 D2 D1 D0

74LS373 Q5

A A A A A A A A A A A A A A A A IOW 1111119876543210 543210

: mov al, 55 mov dx, F000 out dx, al :

S dng 74LS245 lm cng vo

A19 A18 5V

: A0
D7 D6 D5 D4 A0 A1 A2 A3 A4 A5 A6 A7 E IOR IOW B0 B1 B2 B3 B4 B6 B7 DIR

8088 Minimum Mode

D3 D2 D1 D0

74LS245 B5

A A A A A A A A A A A A A A A A IOR 1111119876543210 543210

: mov dx, F000 in al, dx :

Cng ra

Cng vo

5.3 Chip LSI thng dng lm cng I/O

PPI 8255 Khi s lng cng I/O nhiu v khng c nh Cch mc mch s quyt nh a ch cho cc cng cn vai tr ca cng s c quyt nh bi phn mm

8255 PPI

S khi chc nng ca 8255

Cc mode lm vic
Mode 0 - PA, PB, PCH (CU) v PCL (CL) - C th l Input hoc Output - Vic Nhp hoc Xut d liu l c lp Mode 1 - PA, PB - C th l Input hoc Output - Vic Nhp hoc Xut d liu l ph thuc vo mt s bt ca PC (cc tn hiu handshaking) Mode 2 - PA - PA va l Input va l Output - Vic Nhp/Xut d liu vi PA l ph thuc vo mt s bt ca PC (cc tn hiu handshaking)

Nhm lm vic
Nhm A: PA v PCH Nhm B: PB v PCL nh cu hnh lm vic cho 1 chip 8255: Gi 1 T iu khin nh cu hnh n thanh ghi iu khin ca chip Lp/xo mt bit ca PC: Gi 1 T iu khin Lp/Xo bit n thanh ghi iu khin ca chip

T iu khin nh cu hnh lm vic cho mt chip 8255

T iu khin lp/xo bit cho mt chip 8255

The 8255 Programmable Peripheral Interface Intel has developed several peripheral controller chips designed to support the 80x86
processor family. The intent is to provide a complete I/O interface in one chip. 8255 PPI provides three 8 bit input ports in one 40 pin package making it more economical than 74LS373 and 74LS244 The chip interfaces directly to the data bus of the processor, allowing its functions to be programmed; that is in one application a port may appear as an output, but in another, by reprogramming it as an input. This is in contrast with the 74LS373 and 74LS244 which are hard wired and fixed. 8255 Pins PA0 - PA7: input, output, or bidirectional port PB0 - PB7: input or output PC0 - PC7: This 8 bit port can be all input or output. It can also be split into two parts, CU (PC4 - PC7) and CL (PC0 - PC3). Each can be used for input and output. RD or WR IOR and IOW of the system are connected to these two pins RESET A0, A1, and CS CS selects the entire chip whereas A0 and A1 select the specific port (A, B, or C) or Control Register.

Gii m a ch cho 8255

Mode 0 - Simple input/output Simple I/O mode: any of the ports A, B, CL, and CU can be programmed as input or output. Example: Configure port A as input, B as output, and all the bits of port C as output assuming a base address of 50h Control word should be 1001 0000b = 90h
MOV AL, 90h OUT 53h,AL IN AL, 50h OUT 51h, AL OUT 52h, AL

Mode 1: I/O with Handshaking Capability Handshaking refers to the process of communicating back and forth between two intelligent devices Example. Process of communicating with a printer a byte of data is presented to the data bus of the printer the printer is informed of the presence of a byte of data to be printed by activating its strobe signal whenever the printer receives the data it informs the sender by activating an output signal called ACK the ACK signal initiates the process of providing another byte of data to the printer 8255 in mode 1 is equipped with resources to handle handshaking signals

Mode 1 Strobed Output Signals OBFa (output buffer full for port A) indicates that the CPU has written a byte of data into port A must be connected to the STROBE of the receiving equipment ACKa (acknowledge for port A) through ACK, 8255 knows that data at port A has been picked up by the receiving device 8255 then makes OBFa high to indicate that the data is old now. OBFa will not go low until the CPU writes a new byte of data to port A. INTRa (interrupt request for port A) it is the rising edge of ACK that activates INTRa by making it high. INTRa is used to get the attention of the microprocessor. it is important that INTRa is high only if INTEa, OBFa, ACKa are all high it is reset to zero when the CPU writes a byte to port A

Mode 1 Input Ports with Handshaking Signals STB When an external peripheral device provides a byte of data to an input port, it informs the 8255 through the STB pin. STB is of limited duration. IBF (Input Buffer Full) In response to STB, the 8255 latches into its internal register the data present at PA0-PA7 or PB0-PB7. Through IBF it indicates that it has latched the data but it has not been read by the CPU yet. To get the attention of the CPU, it IBF activates INTR INTR Falling edge of RD makes INTR low The RD signal from the CPU is of limited duration and when it goes high the 8255 in turn makes IBF inactive by setting it low. IBF in this way lets the peripheral know that the byte of data was latched by the 8255 and read into the CPU as well.

Lp trnh cho 8255

Li gii

Lp trnh cho 8255

B A

Li gii

To chui xung bng phn mm

Bi ging K thut Vi x l
Ngnh in t-Vin thng i hc Bch khoa Nng ca H Vit Vit, Khoa TVT

Ti liu tham kho [1] K thut vi x l, Vn Th Minh, NXB Gio dc, 1997 [2] K thut vi x l v Lp trnh Assembly cho h vi x l, Xun Tin, NXB Khoa hc & k thut, 2001

Chng 6 Cc kiu I/O

6.1 Thm d (Polling) 6.2 I/O iu khin bng ngt (Interrupt)
-

6.3 DMA (Direct Memory Access)

Thm d
A19 A18 : A0 D7 D6 D5 D4 D3 A0 A1 A2 A3 A4 A5 A6 A7 E IOR IOW B0 B1 B2 B3 B4 B6 B7 DIR 5V

8088 Minimum Mode

D2 D1 D0

74LS245 B5

mov L1: in cmp je

A A A A A A A A A A A A A A A A IOR 1111119876543210 543210

dx, F000 al, dx al, FF L1 : :

A19 A18 :

5V

The Circuit
A0 B0 A1 B1 A2 B2 A3 B3 A4 B4 74LS245 B5 A5 A6 A7 E B6 B7 DIR D0 Q0 D1 Q1 D2 Q2 D3 Q3 D4 Q4 D574LS373 Q5 D6 Q6 D7 Q7 A A A A A A A A A A A A A A A A IOR 1111119876543210 543210 LE OE

A0
D7 D6 D5 D4 D3

8088 Minimum Mode

D2 D1 D0

IOR IOW

AAAAAAAAAAAAAAAAIOW 1111119876543210 543210

Bi ton
Chng trnh to ra hiu ng LED chy: - Ban u LED chy t trn xung - Khi nhn phm thp nht th LED thay i hng chy - Khi nhn phm cao nht th chng trnh kt thc

Chng trnh
mov mov mov out mov dec jnz cmp jne rol cmp jne jmp ror cmp jne dx, ah, al, dx, cx, cx L2 ah, L3 al, al, L1 L4 al, al, L1 F000 00 01 al FFFF L4: mov bl, in al, cmp al, je L6 test al, jnz L5 xor ah, jmp L6 test al, jz L7 mov al, jmp L1 al dx FF 01 FF 80 bl

L1:
L2:

00 1 01 L5: L6: 1 80 L7:

L3:

Khuyt im ca thm d
Tn nhiu thi gian NgI s dng c th nh phm trc khi lnh in al, dx c thc hin, do b vi xi x l s khng bit rng ngI s dng nhn phm Lm sao khc phc cc khuyt im ?

Khuyt im ca thm d
L1: L2: mov mov mov out mov dec jnz cmp jne rol cmp jne jmp ror cmp jne dx, ah, al, dx, cx, cx L2 ah, L3 al, al, L1 L4 al, al, L1 F000 00 01 al FFFF L4: mov bl, in al, cmp al, je L6 test al, jnz L5 xor ah, jmp L6 test al, jz L7 mov al, jmp L1 al dx FF 01 FF 80 bl

00
1 01 L5: L6: 1 80 L7:

L3:

Ngt l g?

Thm d
instruction
While studying, Ill check the bucket every 5 minutes to see if it is already full so that I can transfer the content of the bucket to the drum.

Input Memory Device

P THM D

Ngt
instruction
Ill just study. When the speaker starts playing music it means that the bucket is full. I can then transfer the content of the bucket to the drum.

Input Memory Device

Interrupt request P INTERRUPT

Interrupt- Ngt
B vi x l khng cn phi kim tra tnh sn sng ca thit b I/O. Cc thit b I/O s bo cho vi x l bit khi chng sn sng B vi x l c th lm cng vic khc khi thit b I/O khng c nhu cu trao I d liu

Interrupt- Ngt
Mt s thut ng cn nh:
Yu cu ngt u vo ngt u ra chp nhn ngt Chng trnh con phc v ngt Vector ngt S ngt Bng cc vector ngt

Interrupt Service Routine (ISR) - Chng trnh con phc v ngt Interrupt vector - Vector ngt

L chng trnh c thc hin khi c mt yu cu ngt c chp nhn Kt thc bng lnh IRET a ch ca chng trnh con phc v ngt Bao gm 4 byte:
2 byte cho a ch Offset 2 byte cho a ch Segment

Interrupt Vector Number S ngt

L mt s c dng phn bit cc yu cu ngt. Bi v c th c nhiu hn mt thit b pht yu cu ngt n b vi x l cho nn cho b vi x l c th nhn bit c thit b th mI thit b s c gn cho mt s ngt Trong h thng 8088, co th c n 256 s ngt (t 00h n FFh)

Interrupt Vector Table Bng cc vector ngt

L vng nh c dnh ring lu tr cc vector ngt C th xem nh l mt mng cc vector ngt
Mng ny c 256 phn t Mi phn t gm 4 byte: 2 byte u lu a ch offset, 2 byte sau lu a ch segment Cc vector ngt c lu tr theo trt t tng dn ca s ngt

Bng cc vector ngt

Phn ng ca vi x l khi khng c ngt

1. Khi bt cng tc ngun hoc nhn nt reset. B vi x l c khi ng: (IP) = 0000h (CS) = FFFFh IF = 0 B vi x l tm v ly 1 byte lnh. IP tng ln 1. B vi x l gii m v thc hin lnh nu tt c cc byte lnh ca mt lnh c ly. Quay tr li bc 2.

2. 3. 4. 5.

Phn ng ca vi x l khi c ngt

6. 7. Thit b I/O a yu cu ngt n b vi x l bng cch lm cho u vo ngt INTR chuyn sang mc cao. B vi x l s hon thnh lnh ang thc hin trc khi chp nhn ngt B vi x l chp nhn ngt bng cch a ra tn hiu chp nhn ngt mc thp t chn INTA. Lc ny thit b I/O s lm cho tn hiu INTR chuyn v mc thp. Thit b I/O s a s ngt c gn cho n n b vi x l thng qua D-Bus. B vi x l s lu tr s ngt ny vo mt thanh ghi tm thi

8.

Phn ng ca vi x l khi c ngt

B vi x l lu gi tr hin thi ca thanh ghi c vo stack. B vi x l xo c ngt B vi x l lu gi tr hin thi ca CS vo stack. B vi x l lu gi tr hin thI ca IP vo stack. B vi x l nhn s ngt vi 4. Kt qu ny chnh l a ch ca ni lu tr vector ngt tng ng trong bng cc vector ngt. Hai byte u tin ca vector ngt c copy vo IP v hai byte tip theo c copy vo CS. 14. Quay tr v bc 2. 9. 10. 11. 12. 13.

8088 v mt thit b ra n gin

A19 A18 : A0 D7 D6 D5 D4 D3 D0 D1 D2 D3 D4 D5 D6 D7 LE IOR IOW Q0 Q1 Q2 Q3 Q4 Q6 Q7 OE

8088 Minimum Mode

D2 D1 D0

74LS373 Q5

A A A A A A A A A A A A A A A A IOW 1111119876543210 543210

8088 v mt thit b vo n gin

A19 A18 : A0 D7 D6 D5 D4 D3 A0 A1 A2 A3 A4 A5 A6 A7 E IOR IOW B0 B1 B2 B3 B4 B6 B7 DIR 5V

8088 Minimum Mode

D2 D1 D0

74LS245 B5

A A A A A A A A A A A A A A A A IOR 1111119876543210 543210

8088 v thit b vo hot ng theo c ch ngt

A19 A18 5V

: A0
D7 D6 D5 D4 A7 A6 A5 A4 A3 A2 A1 A0 E IOR IOW INTR INTA INTR A A A A A A A A A A A A A A A A IOR 1111119876543210 543210 B7 B6 B5 B4 B3 B1 B0

8088 Minimum Mode

D3 D2 D1 D0

74LS245 B2

DIR

8088 v mt thit b vo hot ng theo c ch ngt

A19 A18 :

5V

A0
D7 D6 D5 D4 D3 D2 A7 A6 A5 A4 A3 A1 A0 E IOR IOW INTR INTA 5V B0 B1 B2 B3 B4 B6 B7

74LS245 B5 A2

8088 Minimum Mode

D1 D0

DIR

5V

set

INTR

A A A A A A A A A A A A A A A A IOR 1111119876543210 543210

clr 5V

8088 v mt thit b vo hot ng theo c ch ngt

A19 A18 : A0 D7 D6 D5 D4 D3 D2 D1 D0 A7 A6 A5 A4 B7 B6 B5 B4 5V

8088 Minimum Mode

A3 B3 74LS245 B2 A2 A1 B1 A0 E B0

DIR

IOR IOW INTR INTA

5V 5V D set Q INTR

A A A A A A A A A A A A A A A A IOR 1111119876543210 543210

clr

INTA

8088 v mt thit b vo hot ng theo c ch ngt

A19 A18 : A0 D7 D6 D5 D4 D3 D2 D1 D0 A7 A6 A5 A4 B7 B6 B5 B4

5V

5V D7 D6 D5 D4 D3 D2 D1 D0 INTA DIR A7 A6 A5 A4 A3 74LS245 A2 A1 A0 E B7 B6 B5 B4 B3 B2 B1 B0

8088 Minimum Mode

A3 B3 74LS245 B2 A2 A1 B1 A0 E B0

DIR

IOR IOW INTR INTA

5V 5V D set Q INTR

A A A A A A A A A A A A A A A A IOR 1111119876543210 543210

clr

INTA

8088 v mt thit b vo hot ng theo c ch ngt

A19 A18 : A0 D7 D6 D5 D4 D3 D2 D1 D0 A7 A6 A5 A4 A3 74LS245 A2 A1 A0 E IOR IOW INTR INTA B7 B6 B5 B4 B3 B2 B1 B0

5V

INT 3
5V D7 D6 D5 D4 D3 D2 D1 D0 INTA DIR A7 A6 A5 A4 A3 A2 A1 A0 E B7 B6 B5 B4 B3 B1 B0

74LS245 B2

8088 Minimum Mode

DIR

5V 5V D set Q INTR

A A A A A A A A A A A A A A A A IOR 1111119876543210 543210

clr

Q INTA RESET

A19 A18 :

5V

A0
D7 D6 D5 D4 D3

The Circuit
A0 B0 A1 B1 A2 B2 A3 B3 A4 B4 74LS245 B5 A5 A6 A7 E B6 B7 DIR

8088 Minimum Mode

D2 D1 D0

IOR IOW

D0 Q0 D1 Q1 D2 Q2 D3 Q3 D4 Q4 D574LS373 Q5 D6 Q6 D7 Q7
A A A A A A A A A A A A A A A A IOR 1111119876543210 543210 LE OE

AAAAAAAAAAAAAAAAIOW 1111119876543210 543210

Chng trnh chnh

ISR bt u t 52800h mov mov mov mov mov mov mov sti mov mov mov ax,0000 ds, ax bx, 000C ax, 2800 [bx], ax ax, 5000 [bx+02], ax dx, F000 ah, 00 al, 01 L1: cmp je out mov dec jnz cmp jne rol jmp ror jmp ah, L4 dx, cx, cx L2 ah, L3 al, L1 al, L1 88 al FFFF Kt thc

L2:

00 1

L3:
L4:

Chng trnh con phc v ngt (ISR)

mov in test jnz xor jmp test jnz mov mov iret bl, al, al, S1 ah, S2 al, S2 ah, al, al dx 01 FF 80 88 bl

S1:

S2:

8259

ICW

ICW1, ICW2

ICW3, ICW4

OCW1 v OCW2

OCW3

8259 n

ICW1: 13H ICW2: 08H ICW3: 09H

Interrupt Sources in PC

Sources of NMI

8259s ni tng

8259s ni tng

IRQ9 Instead of IRQ2

Interrupts (Summary)

Edge Triggered and Interrupt Sharing

Level triggered mode: IRQ line should be brought down before EOI. Edge triggered mode: noise on IRQ lines might cause false interrupts. New computer and busses.
Level triggered. Interrupt sharing.