M-RAM (Magnetoresistive Random

Access Memory)

Cg- l
+ _
M-RAM M. Bernacki, S. Wsek
Information flux.
Information
O
u
t
s
i
d
e




w
o
r
d

Input
Output
Information
transmission
Information
Processing
Information
storage
DRAM, MRAM

Magnetic (HDD)
Optical (CD, DVD)

M-RAM M. Bernacki, S. Wsek
Memory categories.
WHY DO WEE NEED
M-RAM MEMORY ????
M-RAM M. Bernacki, S. Wsek
Basic attractions
of M-RAM.
Nonvolatility;
Speed;
Low-power consumption;
Scalability.

M-RAM M. Bernacki, S. Wsek
Basic attractions
of M-RAM.
Transfer data to microprocessor
without
creating a bottleneck!

M-RAM M. Bernacki, S. Wsek
History and development...
M-RAM quick view.
Magnetoresistivity. AMR effect - 80-th.
GMR effect - 80-th.
TMR effect 1995 year.
M-RAM based on:
M-RAM M. Bernacki, S. Wsek
Storage and states of a bit.
Storage state:

DRAM: charge of capacitor.
Flash, EEPROM: charge on floating gate.
FeRAM: charge of a ferroelectric capacitor.

T
M
R



[
%
]

Field [Oe]
MRAM: charge and spin.

1
0
Soft ferromagnet
Insulator
Hard ferromagnet
M-RAM M. Bernacki, S. Wsek
Implementation
of 1-MTJ / 1-transistor cell.
Word
line
NiFe (free layer)
CoFe (fixed layer)
Ru
CoFe (pinned layer)
Al
2
O
3
(tunneling barrier)
S
A
F

clad clad
H
w
I
H 2
w
I
H
unclad

2
M-RAM M. Bernacki, S. Wsek
Write.
Word
line
With digit line
current
Without digit line
current
M-RAM M. Bernacki, S. Wsek
Write.
Word
line
R
A

[
k
O
h
m
-
u
m
2
]

Easy axis field [Oe]
M-RAM M. Bernacki, S. Wsek
Read.
Word
line
Word line
M-RAM M. Bernacki, S. Wsek
Sizes of MTJ.
Ferromagnet I
Tunnel barrier
Ferromagnet II
NiFe (free layer)
CoFe (fixed layer)
Ru
CoFe (pinned layer)
Al
2
O
3
(tunneling barrier)
4nm
1..2nm
3nm
3nm
M-RAM M. Bernacki, S. Wsek
Other MRAM cell
architectures.
Twin cell arrays:
Circuit is faster than the 1T1TMR implementation.
Less atractive on a cell density and cost basis.
Diode cell:
SOI diodes allow the integration of a memory with most
circuits without sacrificing silicon wafer surface area.
SOI diodes suitable for this aplication havent been developed yet.
Transistorless array:
Large reduce in cell area.
Complex circuity required to read bit state, slow read.
M-RAM M. Bernacki, S. Wsek
MRAM 32Kb
memory segment.
Bit line
31
Digit
line
Digit
line
Word line
Bit
line 0
Word line
M-RAM M. Bernacki, S. Wsek
Reference generator.
R
MAX
R
MAX
R
MIN
R
MIN
Bit
line
Digit
line
Digit
line
Word
line
Word
line
R
REF
= 1/2(R
MAX
+ R
MIN
)

M-RAM M. Bernacki, S. Wsek
1Mb MRAM architecture.
Available modes:
-Active mode
-Sleep mode
-Standby mode
M-RAM M. Bernacki, S. Wsek
Examples and performance
of M-RAM technology.
- Freescale semiconductors 2003/2004.
Technology: 0.18mikrons, 5-level metal CMOS, copper interconnects;
Capacity: 4MB;
Access time: 15-20ns
Technology: 0.6um, 5-level metal CMOS, copper interconnects;
Capacity: 1MB
Access time: 35ns
- Motorola semiconductors 2002.
M-RAM M. Bernacki, S. Wsek
Roadmap to future
storage technologies.
RRAM
with
CMR
M-RAM M. Bernacki, S. Wsek
Bio MRAM,
vision for tomorrow?
MRAM array Biomolecule labeled by magnetic markers
M-RAM M. Bernacki, S. Wsek
References.
Wykad z przedmiotu Magnetyczne noniki pamici, AGH;
Materiay z Uniwersytetu Bielefeld: wykad Thin films and nanostructures;
Materiay seminaryjne z Motorola Labs;
Materiay z sympozjum VLSI symposium 2002;
www.freescale.com
www.motorola.com
M-RAM M. Bernacki, S. Wsek
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