ASIC Design Using HDLs

Boundary Scan, IEEE 1149.1, JTAG

Ahmed Hemani

References: Essentials of Electronic Testing by Michael Bushnell and Vishwani D Agrawal. Published by Kluwer Academic Publishers Boundary Scan Tutorial by Dr R G Bennets, DFT Consultant. www.dft.co.uk The figures used in this lecture are from these references and used with the permission of the authors. However, they remain under the copyright protection of the authors and/or their Publisher.

Bed-of-Nails Tester Concept

Copyright 2001, Agrawal & Bushnell

Motivation for Standard



Bed-of-nails printed circuit board tester gone  We put components on both sides of PCB & replaced DIPs with flat packs to reduce inductance  Nails would hit components  Reduced spacing between PCB wires  Nails would short the wires  PCB Tester must be replaced with built-in test delivery system -- JTAG does that  Need standard System Test Port and Bus  Integrate components from different vendors  Test bus identical for various components  One chip has test hardware for other chips

Copyright 2001, Agrawal & Bushnell

Purpose of Standard


   

Lets test instructions and test data be serially fed into a component-under-test (CUT)  Allows reading out of test results  Allows RUNBIST command as an instruction  Too many shifts to shift in external tests JTAG can operate at chip, PCB, & system levels Allows control of tri-state signals during testing Lets other chips collect responses from CUT Lets system interconnect be tested separately from components Lets components be tested separately from wires

Copyright 2001, Agrawal & Bushnell

Principle of Boundary Scan (BS)

BS makes it possible to decouple the internal IC logic from the pins and allows direct access to any PCB node without backdriving effects
Source: Boundary Scan Tutorial by Dr R G Bennets

Using the Boundary Scan Path

Outputs: Drivers or Transmitters; Inputs: Sensors or Receivers Scan the Stimulus in Update the scanned data so that it appears at the outputs; i.e. apply the Stimulus Capture the data on the connected inputs. If the transmistted data is not the same as received data, we have a problem.
Source: Boundary Scan Tutorial by Dr R G Bennets

The BS Cell Architecture

Transparency Controllability Observability

Source: Boundary Scan Tutorial by Dr R G Bennets

Defect Coverage
Bed of Nails

Extest Major Application of BST Detect Opens, Shorts and Damage to the Periphery of Devices

Intest Not a major Application of BST Detect problems in internal functionality of Devices
Source: Boundary Scan Tutorial by Dr R G Bennets

The BS Chip Architecture

A set of four dedicated test pins Test Data In (TDI), Test Mode Select (TMS), Test Clock (TCK), Test Data Out (TDO) and one optional test pin Test Reset (TRST*). These pins are collectively referred to as the Test Access Port (TAP). A boundary-scan cell on each device primary input and primary output pin, connected internally to form a serial boundary-scan register (Boundary Scan). A finite-state machine TAP controller with inputs TCK, TMS, and TRST*. An n-bit (n >= 2) Instruction register, holding the current instruction. A 1-bit Bypass register (Bypass). An optional 32-bit Identification register capable of being loaded with a permanent device identification code.

Source: Boundary Scan Tutorial by Dr R G Bennets

Mandatory Instructions and Reset Modes

Source: Boundary Scan Tutorial by Dr R G Bennets

Open Circuit TDI, TMS and TRST

Source: Boundary Scan Tutorial by Dr R G Bennets

Instruction Register

Source: Boundary Scan Tutorial by Dr R G Bennets

Standard Instructions

Source: Boundary Scan Tutorial by Dr R G Bennets

Tap Controller State Diagram

State transitions occur on +ve edge of TCK Controller output Change on ve edge of TCK

Source: Boundary Scan Tutorial by Dr R G Bennets

Copyright 2001, Agrawal & Bushnell

SAMPLE / PRELOAD Instruction -- SAMPLE

Purpose: 1. Get snapshot of normal chip output signals 2. Put data on bound. scan chain before next instr.

Copyright 2001, Agrawal & Bushnell

SAMPLE / PRELOAD Instruction -- PRELOAD

Copyright 2001, Agrawal & Bushnell

EXTEST Instruction


Purpose: Test off-chip circuits and board-level interconnections

Copyright 2001, Agrawal & Bushnell

INTEST Instruction


Purpose: 1. Shifts external test patterns onto component 2. External tester shifts component responses out

Copyright 2001, Agrawal & Bushnell

RUNBIST Instruction


 

Purpose: Allows you to issue BIST command to component through JTAG hardware Optional instruction Lets test logic control state of output pins 1. Can be determined by pin boundary scan cell 2. Can be forced into high impedance state BIST result (success or failure) can be left in boundary scan cell or internal cell  Shift out through boundary scan chain May leave chip pins in an indeterminate state (reset required before normal operation resumes)

Copyright 2001, Agrawal & Bushnell

CLAMP Instruction


 

Purpose: Forces component output signals to be driven by boundary-scan register Bypasses the boundary scan chain by using the onebit Bypass Register Optional instruction May have to add RESET hardware to control on-chip logic so that it does not get damaged (by shorting 0s and 1s onto an internal bus, etc.)

Copyright 2001, Agrawal & Bushnell

IDCODE Instruction


Purpose: Connects the component device identification register serially between TDI and TDO  In the Shift-DR TAP controller state Allows board-level test controller or external tester to read out component ID Required whenever a JEDEC identification register is included in the design

Copyright 2001, Agrawal & Bushnell

Device ID Register --JEDEC Code

MSB 31 28 Version (4 bits)

27 12 Part Number (16 bits)

11 1 Manufacturer Identity (11 bits)

LSB 0 1 (1 bit)

Copyright 2001, Agrawal & Bushnell

USERCODE Instruction
 Purpose: Intended for user-programmable components (FPGAs, EEPROMs, etc.)


Allows external tester to determine user programming of component

 Selects the device identification register as serially connected between TDI and TDO  User-programmable ID code loaded into device identification register


On rising TCK edge

 Switches component test hardware to its system function  Required when Device ID register included on userprogrammable component
Copyright 2001, Agrawal & Bushnell

HIGHZ Instruction


  

Purpose: Puts all component output pin signals into highimpedance state Control chip logic to avoid damage in this mode May have to reset component after HIGHZ runs Optional instruction

Copyright 2001, Agrawal & Bushnell

BYPASS Instruction


Purpose: Bypasses scan chain with 1-bit register

Copyright 2001, Agrawal & Bushnell

Application at Board Level

Select IR Cycle Capture_IR, Shift_IR to load and shift the 01 checkerboard pattern
Source: Boundary Scan Tutorial by Dr R G Bennets

Extest

??? Use processors to access memories

How Many Tests are Needed ?

Source: Boundary Scan Tutorial by Dr R G Bennets

Building the Tests

ceil log2(k + 2), k = number of interconnects

To ensure that each net is tested for a stuck-at-1 and stuck-at-0 fault, there must be at least one 1 and at least one 0 in the code. If stuck-at-1, stuck-at-0 coverage were the only requirements, any code except the all-0s and all-1s codes would be sufficient. This means that there are two forbidden codes: all-0s and all-1s. To ensure that two nets, net i and net j, are tested for a short circuit, there must be at least one bit different between the two codes allocated to net i and net j in order to apply complementary logic values across the two nets. Complementary logic values are a necessary and sufficient condition to detect a short circuit, assuming logical behaviour of the short. Given that we are targeting all possible 2-net combinations, this generalizes into a requirement that says that the same code can never be allocated to two separate nets i.e. each code assignment is unique.
Source: Boundary Scan Tutorial by Dr R G Bennets