UNIT-III

I/O interface with 8255-PPI, 8255-various modes of

operation and interfacing to 8086, interrupt structure
of 8086, serial communication standards, 8251
USART architectures and its interfacing to 8086, RS-
232C. 8257 DMA controller and its interfacing to
8086, memory interfacing to 8086.

1
I/O Interface
 INTRO TO I/O INTERFACE
• I/O instructions are IN, INS, OUT, and OUTS

• Also isolated (direct I/O or mapped I/O) and

memory-mapped I/O, the basic input and output
interfaces, and handshaking.

• Knowledge of these topics makes it easier to

understand the connection and operation of the
programmable interface components
and I/O techniques.
 The I/O Instructions
• One type of instruction transfers information
to an I/O device (OUT).

• Another reads from an I/O device (IN).

• Instructions are also provided to transfer strings of

data between memory and I/O.
– INS and OUTS, found except the 8086/8088
Input port: Output port:
Personal Computer I/O Map

– the PC uses part of I/O map for

dedicated functions, as shown here

– I/O space between ports 0000H and 03FFH is

normally reserved for the system and ISA bus
(Industry Standard Architecture bus)

– ports at 0400H–FFFFH are generally available

for user applications, main-board functions, and
the PCI bus (Peripheral Controller Interconnect)
PROGRAMMABLE
PERIPHERAL
INTERFACE -8255
 Introduction
• It is a programmable device.

• It is an I/O port chip used for interfacing I/O

devices with microprocessor

• Very commonly used peripheral chip

• Knowledge of 8255 essential for students in the

Microprocessors lab for Interfacing experiments
 8255 Ports
• 8255 PPI has three 8-bit ports.
• Port A (PA)
• Port B (PB)
• Port C (PC)

• Port C composed of two independent 4-bit ports: PC7-4

(PC Upper) and PC3-0 (PC Lower)

• Port A, Port B, Port C and Control port will have the

addresses as 7CH, 7DH, 7EH, and 7FH respectively.
Block Diagram
Data Bus buffer:

• It is a 8-bit bidirectional Data bus.

• Used to interface between 8255 data bus with

system bus.

• The internal data bus and Outer pins D 0-D7 pins

are connected in internally.

• The direction of data buffer is decided by

Read/Control Logic.
Read/Write Control Logic:

• This is getting the input signals from control bus

and Address bus

• Control signal are RD and WR.

• Address signals are A0,A1,and CS.

• 8255 operation is enabled or disabled by CS.

Group A and Group B control:
• Group A and B get the Control Signal from
CPU and send the command to the individual
control blocks.
• Group A send the control signal to port A and
Port C (Upper) PC7-PC4.
• Group B send the control signal to port B and
Port C (Lower) PC3-PC0.
PORT A:
• This is a 8-bit buffered I/O latch.
• It can be programmed by mode 0 , mode 1,
mode 2 .
PORT B:
• This is a 8-bit buffer I/O latch.
• It can be programmed by mode 0 and mode 1.

PORT C:
• This is a 8-bit Unlatched buffer Input and an
Output latch.
• It is spitted into two parts.
• It can be programmed by bit set/reset operation.
Pin Diagram
 Pin Description
• PA7-PA0 : These are eight port A lines that acts as either
latched output or buffered input lines
depending upon the control word loaded into the
control word register.

• PC7-PC4 : Upper nibble of port C lines. They may act as

either output latches or input buffers lines.
This port also can be used for generation of
handshake lines in mode 1 or mode 2.

• PC3-PC0 : These are the lower port C lines, other details

are the same as PC7-PC4 lines.

• PB0-PB7 : These are the eight port B lines which are used
as latched output lines or buffered input lines in the
same way as port A.
 Pin Description(Contd…)
• RD : This is the input line driven by the
microprocessor and should be low to indicate read
operation to 8255.

• WR : This is an input line driven by the

microprocessor. A low on this line indicates write
operation.

• CS : This is a chip select line. If this line goes low, it

enables the 8255 to respond to RD and WR
signals, otherwise RD and WR signal are
neglected.

• A1-A0 : These are the address input lines and are driven
by the microprocessor.

• RESET : The 8255 is placed into its reset state if this

input line is a logical 1. All peripheral ports are set to
 8255 Operations
• The lines A1-A0 with RD, WR and CS form the
following operations for 8255.
 Programming 8255
• 8255 has three operation modes: mode 0, mode 1,
and mode 2

Mode 0 - Simple Input or Output mode

Mode 1 - Input or Output with Handshake mode

Mode 2 - Bidirectional Data Transfer mode

 Mode 0 - Simple Input or Output
• In this mode, ports A, B are used as two simple 8-
bit I/O ports & port C as two independent 4-bit
ports.
• Each port can be programmed to function as simply
an input port or an output port.
• The input/output features in Mode 0 are as follows.

1. Outputs are latched.

2. Inputs are not latched.
3. Ports don’t have handshake or interrupt capability.
 Handshaking

• Many I/O devices accept or release information

slower than the microprocessor.

• A method of I/O control called handshaking or

polling, synchronizes the I/O device with the
microprocessor.

• An example is a parallel printer that prints a few

hundred characters per second (CPS).
 Mode 1 - Input or Output with Handshake
• In this mode, handshake signals are exchanged
between the MPU and peripherals prior to data
transfer.
• The features of the mode include the following:
1. Two ports (A and B) function as 8-bit I/O ports.
They can be configured as either as input or output ports.

2. Each port uses three lines from port C as handshake

signals.
The remaining two lines of Port C can be used for simple I/O
operations.
3. Input and Output data are latched.
4. Interrupt logic is supported.
 Example:
• The computer send the data to the printer large
speed compared to the printer.
• When computer send the data according to the
printer speed at the time only, printer can accept.
• If printer is not ready to accept the data then after
sending the data bus , computer uses another
handshaking signal to tell printer that valid data is
available on the data bus.
• Each port uses three lines from port C as
handshake signals
Mode 1 - Input or Output with Handshake
Mode 2 - Bidirectional Data Transfer
• This mode is used primarily in applications such as
data transfer between two computers.

• In this mode, Port A can be configured as the

bidirectional port, Port B either in Mode 0 or Mode 1.

• Port A uses five signals from Port C as

handshake signals for data transfer.

• The remaining three signals from Port C can be

used either as simple I/O or as handshake for port B.
 8255 Modes Summary
• Port A can work in Mode 0, Mode 1, or Mode 2

• Port B can work in Mode 0, or Mode 1

• Port C can work in Mode 0 only, if at all

• Port A, Port B and Port C can work in Mode 0

• Port A and Port B can work in Mode 1

• Only Port A can work in Mode 2

 8255 Control Words
• There are 2 control words in 8255.
1. Mode Definition (MD) Control word and
2. Bit Set / Reset (BSR) Control Word

• MD control word configures the ports of 8255 as input or

output in Mode 0, 1, or 2.

• PCBSR control word is used to set to 1 or reset to 0 any one

selected bit of Port C
1.Mode Definition (MD) Control word
8255 Control words
2. Bit Set / Reset (BSR) Control Word
 Interfacing with
Advanced Devices
 Interrupts
• Definition: The meaning of ‘interrupts’ is to break the
sequence of operation. While the CPU is executing a
program, on ‘interrupt’ breaks the normal sequence of
execution of instructions, diverts its execution to some other
program called Interrupt Service Routine (ISR).After
executing ISR , the control is transferred back again to the
main program. Interrupt processing is an alternative to
polling.
• Need for Interrupt: Interrupts are particularly useful when
interfacing I/O devices that provide or require data at
relatively low data transfer rate.
 Different Types of Interrupts

INTERRUPTS

HARDWARE INTERRUPTS SOFTWARE INTERRUPTS

EXTERNAL INTERNAL SYSTEM USER-DEFINED

MASKABLE NON-MASKABLE

DOS INTERRUPTS BIOS INTERRUPTS

 Classification 8086 INTERRUPTS
256 INTERRUPTS OF 8086 ARE DIVIDED IN TO 3 GROUPS

1. TYPE 0 TO TYPE 4 INTERRUPTS-

THESE ARE USED FOR FIXED OPERATIONS AND
HENCE ARE CALLED DEDICATED INTERRUPTS

2. TYPE 5 TO TYPE 31 INTERRUPTS

NOT USED BY 8086,RESERVED FOR HIGHER PROCESSORS LIKE
80286 ,80386 ETC

3. TYPE 32 TO 255 INTERRUPTS

AVAILABLE FOR USER,CALLED USER DEFINED INTERRUPTS
THESE CAN BE H/W INTERRUPTS AND ACTIVATED THROUGH
INTR
LINE OR CAN BE S/W INTERRUPTS
TYPE – 0 DIVIDE ERROR INTERRUPT
QUOTIENT IS LARGE CANT BE FIT IN AL/AX OR DIVIDE BY ZERO

TYPE –1 SINGLE STEP INTERRUPT

USED FOR EXECUTING THE PROGRAM IN SINGLE STEP MODE BY
SETTING TRAP FLAG
TO SET TRAP FLAG PUSHF
MOV BP,SP
OR [BP+0],0100H;SET BIT8
POPF

TYPE – 2 NON MASKABLE INTERRUPT

THIS INTERRUPT IS USED FOR EXECUTING ISR OF NMI PIN
(POSITIVE EGDE SIGNAL). NMI CANT BE MASKED BY S/W

TYPE – 3 BREAK POINT INTERRUPT

USED FOR PROVIDING BREAK POINTS IN THE PROGRAM

TYPE – 4 OVER FLOW INTERRUPT

USED TO HANDLE ANY OVERFLOW ERROR AFTER SIGNED ARITHMETIC
PRIORITY OF INTERRUPTS
INTERRUPT TYPE PRIORITY
INT0,INT3-INT 255,INTO
HIGHEST
NMI(INT2)

INTR

SINGLE STEP
LOWEST
Interrupt Vector Table – IVT (in memory)
• x86 has 256 interrupts, specified by Type Number or Vector
• 1 byte of data must accompany each interrupt; specifies Type
Vector is a pointer (address) into Interrupt Vector Table, IVT
– IVT is stored in memory from 0000:0000 to 0000:03ffh

• IVT contains 256 far pointer values (addresses)

– Far pointer is CS:IP values

• Each far pointer is address of Interrupt Service Routine, ISR

– Also referred to as Interrupt Handler
 IVT Format
0000:0000
0000:0001
Offset
0000:0002
Interrupt 0 IP LSB

0000:0003
Segment IP MSB

0000:0004 CS LSB

0000:0005
Offset CS MSB
Interrupt 1
0000:0006
0000:0007
Segment

Given a Vector, where is the

ISR address stored in memory ?

Offset Type 4
0000:03fc
0000:03fd
Offset Example: int 36h
0000:03fe
Interrupt 255
Segment Offset = (544) = 216
0000:03ff
= 00d8h
Structure of Interrupt Vector Table 8086/88
Interrupt Service Routine (ISR)
• Similar to a subroutine
• Attends to the request of an interrupting source
– Clears the interrupt flag
– Should save register contents that may be affected by
the code in the ISR
– Must be terminated with the instruction RETFIE
• When an interrupt occurs, the MPU:
– Completes the instruction being executed
– Disables global interrupt enable
– Places the return address on the stack
Interrupt Service Routine (ISR)
• High-priority interrupts
– The contents of W, STATUS, and BSR registers are
automatically saved into respective shadow registers.
• Low-priority interrupts
– These registers must be saved as a part of the ISR
• If they are affected

• RETFIE [s] ;Return from interrupt

• RETFIE FAST ;FAST equivalent to s = 1
– If s =1: MPU also retrieves the contents of W,
BSR, and
STATUS registers