Electronics-> reliability, low power dissipation, low weight and volume, low cost etc.

1950s->vacuum tubes Early in 1947s->invented transistors. Transistors invented by->William B.Shockley, Walter H.Brattain & John Bardeen. The 1st IC(integrated circuit)->1960s. 4 generations of IC->1. SSI 2.MSI 3.LSI 4. VLSI 5TH generation -> ULSI(ultra large scale integration) CMOS technology used ->for high performance and cost effective VLSI circuits.

Recent products->RISC chips can process 35 million instructions per sec. To improve scaling and processing ->new tech BiCMOS. Emerging technology->GaAs(Gallilium Arsenide) (MOS)Metal-Oxide-Semiconductor -> circuits are based on pMOS,nMOS&CMOS ->measure of effectiveness is the speed of the basic logic gate circuit of the tech. ->for nMOS-NOR gate ->for CMOS- NAND & NOR gates. ->speed power pdt is mgaeasured in picojoules(pJ) ->pdt of the gate switching delay is measured in ns ->gate power dissipation in milliwatts.

metal polysilicon n substrate p substrate oxide depletion p-diffusion n-diffusion

BASIC MOS TRANSISTORS (fig(a))

Source Vs Gate Vgs Drain VD

P Sub

nMOS enhancement mode transistor

Definition of doping? The process of changing the conductive properties of silicon by adding trace amounts of other elements. Learn more about doping in the class "Electronic Semiconductor Devices 350" below.

->nMOS devices are formed in a p-type substrate f modern doping level -> source &drain regions are formed by diffusing ntype impurities thru suitable mask- into the areas -> to give n-purity concentration & give rise to depletion regions -> source & drain are isolated from one another by 2 diodes. ->connections to the source & drain are made by a deposited metal layer ->from fig(a) A polysilicon gate is deposited on layer Of insulation over the region b/w source & drain

->in fig (a) is the enhancement mode in which channel is not established & device is in a nonconducting condition VD=VS=Vgs=0 ->if this gate is connected to +ve voltage w.r.to source, then the electric field established b/w the gate & the substrate give rise to charge inversion region in the substrate under the gate insulation & a conducting path or channel is formed b/w source & drain. -> channel can also be established under the condition Vgs=0 & by implanting suitable impurities in the region b/w source & drain. this is shown in fig(b)

nMOS depletion mode transistor FIG(b) Source Gate

Drain

P Sub

implant

->Under this condition source & drain are connected by a conducting channel, but the channel may now be closed by applying a ve voltage to the gate. ->in both cases variations of the gate voltage allow ctrl of any current flow b/w source & drain.

fig(c)
Source Gate

pMOS enhancement mode transistor Drain

n
Sub

->here substrate is of n-type , source & drain diffusions are p-type ->pMOS transistors are slower than nMOS -> -ve voltage is applied b/w gate & source give rise to form p-type channel b/w source drain & current may flow if the drain is ve with respect to source.