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Peripheral devices
Input devices Output devices
8 bit / 16-bit IO
8255 modes
16-bit data bus to 8-bit peripherals or memory devices
DCSE CEG, Anna University
Peripheral
is an input and/or output device like a memory chip, it is mapped to a certain location (called the port address)
Output Device
like a memory chip, you can write to an output device You can write to a memory chip using the command mov [bx], al
You can write to an output device using the command out dx, al
Input Device
like a memory chip, you can read from an input device You can read from a memory chip using the command mov al, [bx] You can read from an input device using the command in al, dx
Same instruction vs. independent instruction Entire address bus vs. part of address bus Same control signals vs. independent
8bit vs 16bit IO
8088 case: MOV DX, 648H OUT DX, AX ;AX = 76A9H Address bus and ALE Low byte (A9), IOW Setup time Address (649) and ALE High byte (76), IOW Setup time 8086 case: MOV DX, 648H OUT DX, AX ;AX = 76A9H Address bus and ALE Word (76A9), IOW Setup time
Use 8 LEDs
A19 A18
: A0
D7 D6 D5 D4
D3 D2 D1 D0
IOR IOW
A18 : A0
D7 D6 D5 A0 A1 A2 B0 B1 B2
D4 D3 D2 D1 D0
A3 B3 A4 B4 74LS245 B5 A5 A6 B6 A7 B7
E DIR 5V
IOR IOW
: A0
D7 D6 D5 D4 D0 D1 D2 D3 D4 D5 D6 D7 LE IOR IOW Q0 Q1 Q2 Q3 Q4 Q6 Q7 OE
D3 D2 D1 D0
74LS373 Q5
: mov al, 55 mov dx, F000 out dx, al : DCSE CEG, Anna University
: A0
D7 D6 D5 D4 A0 A1 A2 A3 A4 A5 A6 A7 E IOR IOW B0 B1 B2 B3 B4 B6 B7 DIR
D3 D2 D1 D0
74LS245 B5
Polling
A19 A18 : A0 D7 D6 D5 D4 D3 A0 A1 A2 A3 A4 A5 A6 A7 E IOR IOW B0 B1 B2 B3 B4 B6 B7 DIR 5V
D2 D1 D0
74LS245 B5
mov in cmp je
T1 T4 of OUT 99H, AL ?
DCSE CEG, Anna University
T1 T4 of IN AL, 5FH ?
DCSE CEG, Anna University
8255 PPI
Control word
Modes of Operation
Mode 0 simple input or output Mode 1 input or output with handshaking Mode 2 bideirectional IO with handshaking
Solution
Solution
BSR mode
Solution A)
MOV AL, 00000101B OUT 93H,AL
B)
MOV AL, 0xxx1101 OUT 93H, AL CALL Delay CALL Delay MOV AL, 0xxx1100 OUT 93H, AL CALL Delay JMP AGAIN
DCSE CEG, Anna University
#ACKa:
Data has been picked up by receiving device
INTRa:
After rising edge of #ACKa
Solution
IBF (out):
Data has been latched by 8255
INTR (out):
After activation of IBF
MODE 2 Operation
IBM PC IO MAP
Decoding by 74138
8255 Address in PC
80x86 family
16-bit Processors
8088 (8-bit data / 20-bit address)
32-bit Processors
80386 (16/24 or 32/32 common)
8088
Data is organized into byte widths The 1MB memory is organized as 1M x 8-bits
8086/80186
Data is organized into word widths
The 1MB memory is organized as 512kB x 16-bits
80286/80386SX
Data is organized into word widths The 16MB memory is organized as 8MB x 16-bits
80386DX/80486
Data is organized into double word widths The 4GB memory is organized as 1GB x 32-bits
; load AX (16 bits), with the value 513 ; store AX into memory 4
8086 has BHE Control Signal (Bank High Enable) Can Use Combination of A0 and BHE to Determine Type of Access
BHE 0 0 1 1 A0 0 1 0 1 Access Type 1 word (16-bits) Odd Byte (D15-D8) Even Byte (D7-D0) No Access
DI
IP
XXXX
XXXX
A18
: A0 D7
7FFFE
7FFFD : 20023 20022 20021 20020 : 00001 00000
98
2C : 33 45 92 A3 : D4 97
:
D0 RD WR CS
Interfacing two 512KB Memory to the 8086 Microprocessor How to connect data lines? How to connect address What about chip select? lines?
AX BX CX DX CS SS DS ES BP SP SI 3F1C 0023 0000 FCA1 XXXX XXXX 4000 XXXX XXXX XXXX XXXX 7FFFF 12 A0 A19 : A1 D7 : D0 MEMR MEMW A18 : A0 D7 : D0 RD WR CS 7FFFF 7FFFE 7FFFD : 20023 20022 20021 20020 : 00001 00000 36 25 19 : 13 7D 12
1C 29
: 95 23
DI
IP
XXXX
XXXX D15 :
A18
: A0 D7 :
7FFFE
7FFFD : 20023 20022 20021 20020 : 00001 00000
98
2C : 33 45 92 A3 3F : D4 97
D8
D0
RD WR
BHE#
CS
Hi/Lo Copier in PC
PC Interface Card
From BitPardaz
ouportb(port Out port#, #, byte) byte var=inportb( port#) Var = INP (port#) Out port#, word ??
Example
A19 A18 :
5V
The Circuit
A0
D7 D6 D5 D4 D3 A0 B0 A1 B1 A2 B2 A3 B3 A4 B4 74LS245 B5 A5 A6 A7 E IOR IOW B6 B7 DIR D0 Q0 D1 Q1 D2 Q2 D3 Q3 D4 Q4 D574LS373 Q5 D6 Q6 D7 Q7 A A A A A A A A A A A A A A A A IOR 1111119876543210 543210 LE OE
D2 D1 D0
L1: L2:
00
L5:
1 01 L6: L7: 1 80
80
bl
L3:
L5:
L6: L7:
80
bl
L3: ror
Interrupt
The microprocessor does not check if data is available. The peripheral will interrupt the processor when data is available
P POLLING
DCSE CEG, Anna University