Final Design Review Flash / EEPROM parallel interface

12/13/04 Jim Brandt, Team Leader Jeff Nault

Project Objectives

Project Objectives
100 MHz system clock interface 45 ns (Flash Read Time) interface 0 latency system interface Develop on and off chip testing methodologies to enable accurate testing of chip post- fabrication Keep design small and minimize power consumption

Project Definition

Project Definition
EEPROM template memory interface for fingerprint recognition system:

Will allow 0 latency for system memory by buffering data transfers between each. 16 bit parallel input from EEPROM and 2 bit serial output from interface to system. System side of interface runs at 100 MHz, EEPROM side of interface runs at 1/8 system clock 12.5 MHz. Templates for fingerprint recognition are located on EEPROM for long term storage.

AT49BV/LV1024A Read Timing Diagram

Project Definition

Project Definition
Generalized System Block Diagram
External System System Clock

Data out bits 1 and 0

Data Request Data Ready Reset

INTERFACE System Clock Reset Control Signal Generation Shift / Load Mux Select 1/8 System Clock Data PathShifters

Last Address Signal Address Load EEPROM Address Generation 16 16 16 bit Data Line

Chip Enable (CE)

16 bit Address Line Output Enable (OE)

EEPROM

Sub-Modules
For design purposes, the system is divided into three sub-modules:
Datapath: 1. Shifter Logic. Control Logic: 2. Control Signal Generation. 3. EEPROM Address Generation.

Sub-Modules: Datapath
Block Diagram of Shifters
Data out bits 1 and 0

Control Inputs
Clock Reset Self Test Load

Data Inputs Data Outputs

16 data bits 2 bit output: from even shift EEPROM: register output first shifter has even bits, contains D0, second has odd contains D1. odd bits.

System Clock Reset Shift / Load Mux Select 1/8 System Clock Data PathShifters

16 bit Data Line 16

Sub-Modules: Datapath
The Datapath consists of two 9 bit shift registers with parallel load. The first shift register contains the data for the even bits (i.e. 0, 2, , 14), and the second contains the data for the odd bits. While the word length is 16 bits, the two shift registers have a combined capacity of 18 bits. This is to facilitate zero latency output of the shifted data during a parallel load. Only the first 8 bits of each shift register are parallel loaded.

Sub-Modules: Datapath
Schematic of Datapath

Sub-Modules: Datapath

Eldo Simulation results for selected signals from a Shift Register

Sub-Modules - Control Logic

Block Diagram of Control Logic
System Clock Data Request Data Ready Reset

Control Inputs
System Clock Reset Data Request
System Clock Reset

Control Outputs
Data Ready System Clock Clock Divider signals (1/2, 1/4 and 1/8). Shift / Load Select

Self Test Last Address Signal Self Test Output Enable (OE) Chip Enable (CE)

Control Signal Generation

Shift / Load Mux Select 1/8 System Clock

Output Enable (OE) System Clock Divided: Chip Enable (CE)

Last Address Signal

Sub-Modules - Control Logic

This module creates all of the signals that control the datapath and addressing modules. Design for Test (DFT) features are also implemented in this module of the design. Several of the control state signals are also exported to the external system for additional testing and verification.

Sub-Modules - Control Logic

Schematic of Control Logic

Sub-Modules - Control Logic

Eldo Simulation results of selected signals for Control Logic module

Sub-Modules - Addressing
Block Diagram of Addressing Module
1/8 System Clock Last Address Signal

Control Inputs Control Outputs

System Clock (1, 1/2, 1/4, and 1/8)
EEPROM Address Generation

16 bit Address Last Address Signal

Reset

16 bit Address Line

16

Sub-Modules - Addressing
This module outputs the EEPROM address, incrementing it sequentially on every eighth clock pulse (if system is requesting data). The module will send a last address signal when the last address is reached. Currently this is set at 0x000F. The self test functionality of the chip is derived from the address generation. The data is diverted from the address out bus to the data in bus when the self test signal is enabled.

Sub-Modules - Addressing
Schematic of Addressing Module and Self Test

Eldo Simulation results of selected signals for Addressing module

Sub-Modules - Addressing

Full System Schematic

Physical Layout of Entire System

Physical Layout of Entire System with Pad Frame

Mach TA results of selected data and address lines for entire system

Complete System

Mach TA results of selected control signals for entire system

Complete System

Complete System
Characteristics of System (excluding pad frame):
2392 Transistors (1196 NMOS, 1196 PMOS) 40 external pins; 24 inputs, 16 outputs. Physical Dimensions: 1862.5 X 1707.5

( = 0.3 m) 512.25 m

558.75 m X

Progress

Progress
System Design is completed:
o Logic design and functionality fully tested and implemented o Physical layout completed and interfaced with pad frame. o Mach TA simulation of system design completed successfully. o Post fabrication testing and verification plans are being developed, including DFT features.

Plan of Action

Plan of Action
Prepare the data files necessary for fabrication. Continue investigating the apparent inability of Mentor Graphics to simulate the entire system (including the pad frame) using MachTA. Finish the written report with final design specifications. Develop testing algorithms for post fabrication testing and verification.

Testing and Verification

Testing and Verification

Three different methods to test and verify the chip design have been developed:
1. DFT on chip self test mechanism. 2. 9 pins have been assigned for diagnostic purposes. 3. An EEPROM flash memory has been acquired which will be programmed with known data and interfaced with the fabricated chip.

Self Test
The on chip self test connects the generated EEPROM addresses to the data input lines. This will allow the system to function without having an EEPROM connected. This will allow verification of the functionality of all three sub modules.

Additional Testing and Verification

The 9 pins assigned for verification will enable us to verify the current state of the chip during operation. If any errors do occur, will be able to identify where and when they happen. This greatly increases the observability of any potential errors. Post fabrication testing will be done with the STM-4100 using a variety of test vectors to verify chip performance, with the use of an external EEPROM programmed with known data.

Evaluation

Evaluation / Status
Eldo and Mach-TA simulations of all subsystems and the system as a whole are showing that the timing and logic are functioning as designed. System passes all DRC and LVS checks. The design phase of the project is done.

Bar Chart Schedule of Tasks

References
Atmel Flash memory data sheet

http://www.atmel.com/dyn/resources/prod_docume

Weste, Neil H.E. CMOS VLSI Design.3rd edition. Addison Wesley, 2005. Mano, M. Morris Logic and Computer Design Fundamentals, 2nd edition updated. Prentice-Hall, 2001.