ECT312 Digital System Design
Module 1
Sangeetha Gopan G S
Assistant Professor
Dept. of ECE,CET
• Preamble: This course aims to design hazard
free synchronous and asynchronous
sequential circuits and implement the same in
the appropriate hardware device
• Prerequisite: ECT203 Logic Circuit Design
• Course Outcomes: After the completion of the course the
student will be able to
• CO 1 K4 Analyze clocked synchronous sequential circuits
• CO 2 K4 Analyze asynchronous sequential circuits
• CO 3 K3 Design hazard free circuits
• CO 4 K3 Diagnose faults in digital circuits
• CO 5 K2 Summarize the architecture of FPGA and CPLDs
SYLLABUS
• Module 1: Clocked Synchronous Networks Analysis of clocked Synchronous
Sequential Networks (CSSN), Modelling of CSSN – State assignment and reduction,
Design of CSSN, ASM Chart and its realization
• Module 2: Asynchronous Sequential Circuits Analysis of Asynchronous Sequential
Circuits (ASC), Flow table reduction- Races in ASC, State assignment problem and the
transition table- Design of AS, Design of ALU
• Module 3: Hazards – static and dynamic hazards – essential, Design of Hazard free
circuits – Data synchronizers, Mixed operating mode asynchronous circuits, Practical
issues- clock skew and jitter, Synchronous and asynchronous inputs – switch
bouncing
• Module 4: Faults - Fault table method – path sensitization method – Boolean
difference method, Kohavi algorithm, Automatic test pattern generation – Built in
Self Test (BIST)
• Module 5: CPLDs and FPGA CPLDs and FPGAs - Xilinx XC 9500 CPLD family, functional
block diagram– input output block architecture - switch matrix, FPGAs – Xilinx XC
4000 FPGA family – configurable logic block - input output block, Programmable
interconnect
Module 1
Sequential Circuit
It consists of a combinational circuit to which storage elements are
connected to form a feedback path.
The storage elements are devices capable of storing binary
information. The binary information stored in these elements at any
given time defines the state of the sequential circuit at that time.
The sequential circuit receives binary information from external
inputs that, together with the present state of the storage elements,
determine the binary value of the outputs.
Thus, a sequential circuit is specified by a time sequence of
inputs, outputs, and internal states
Clocked Synchronous Sequential Networks
• Network behavior is defined at
specific instants of time
associated with a clock signal.
• Usually a master clock that
appears at the control inputs of
all the flip-flops.
• Combinational logic is used to
generate the next-state and
output signals.
Clocked Synchronous Sequential Networks
• Input and new present state signals are applied to the
combinational logic.
• Effects of the signals must propagate through the
network.
– Final values at the flip-flop inputs occur at different times
depending upon the number of gates involved in the signal
paths.
• Only after final values are reached, active time of the
clock signal is allowed to occur and cause any state
changes.
• All state changes of the flip-flops occur at the same time.
Clocked Synchronous Sequential Networks
• Next state of the network:
– denotes the collective external input signals
– denotes the collective present states of the flip-
flops.
• denotes the collective output signals of the
network:
STORAGE ELEMENTS: FLIP-FLOPS
SR Flip-Flop
Truth table
Characteristic Table
D Flip-Flop
Logic Symbol Truth table
Characteristic Table
JK Flip-Flop
Logic Symbol Truth table
Characteristic Table
T Flip-Flop
Logic Symbol Truth table
Characteristic Table
EXCITATION TABLE OF A FLIP-FLOP
• The truth table of a flip-fl op is also referred to as the
characteristic table of a flip-fl op, since this table refers
to the operational characteristics of the flip-fl op.
• But in designing sequential circuits, we often face
situations where the present state and the next state of
the flip-fl op is specified, and we have to find out the
input conditions that must prevail for the desired
output condition.
• By present and next states we mean to say the
conditions before and after the clock pulse respectively.
Mealy model
• The output is a function of both present state
and input
Moore Model
• Variation of Mealy model when the outputs
are only a function of the present state and
not of the external inputs: .
Analysis of clocked Synchronous Sequential
Network
Analysis describes what a given circuit will do
under certain operating conditions.
The analysis of a sequential circuit consists of
obtaining a table or a diagram for the time
sequence of inputs, outputs, and internal states.
CSSN Analysis Steps
1. Excitation and Output Expressions
2. Transition Equations
3. Transition Tables
4. State table(State Assignment)
5. State Diagrams
Two Examples
Figure 1: Mealy network
Two Examples
Figure 2: Moore network
Excitation and Output Expressions
• Assign variables to flip flop-states
• Assign excitation variables to flip-flop inputs
Excitation and output expressions for Fig. 1:
Excitation and output expressions for Fig 2:
Transition Equations
Transition Equations for Figure 1:
• =
• =
Transition Equations for Figure 2:
Transition Tables
Rather than using algebraic descriptions can express the information in tabular form.
• Table consists of three sections
– Present state variables
– Next-state variables
– Output variables
• Present state variables:
– Lists all the possible combinations of values for the state variables.
– If there are state variables, then rows.
• Next-state section
– One column for each combination of values of the external input variables.
– If there are external input variables, then columns.
– Each entry is a -tuple corresponding to the next state for each combination of present state
and external input.
• Mealy network outputs:
– One column for each combination of values of the external input variables.
– Entries within the section indicate the outputs for each present-state/input combination.
• Moore network outputs:
– Output section has only a single column.
Transition Tables
Excitation Tables
• The transition table is constructed as the result of
substituting excitation expressions into the flip-flop
characteristic equations.
• An alternative approach:
– First construct the excitation table directly from the
excitation and output expressions.
• Excitation table consists of three parts:
– Present-state section
– Excitation section
– Output section
Excitation Tables
Constructing Transition Tables from
Excitation Tables
• Consider entry in fourth column, first row of
second table:
– Present state:
– So due to behavior of JK-flip-flop next state is:
State Tables
• State table consists of three sections:
– Present state
– Next state
– Output
• Actual binary codes used to represent the states are
not important.
• Alphanumeric symbols can be assigned to represent
these states.
• State table is essentially a relabeling of the
transition table.
State Tables
State Tables
State Diagrams
• Graphical representation of the state table.
– Each state is represented by a labeled node.
– Directed branches connect the nodes to indicate transitions between
states.
– Directed branches are labeled according to the values of the external
input variables.
– Outputs of the sequential network are also entered on a state diagram.
• Mealy network:
– Outputs appear on the directed branches along with the external inputs.
• Moore network:
– Outputs are included within the nodes along with their associated
states.
State Diagrams
Network Terminal Behavior
• Consider example from Figure 1:
– Assume flip-flops are both in 0-states (state A)
– Input sequence is applied
Input sequence = 0 0 1 1 0 1 1 1 0 1
State sequence = A C C A B D A B D A B
Output sequence = 0 1 0 1 0 0 1 0 1 1
• Note: For mealy sequential network, although outputs are shown on
directed branches, this does not mean that the outputs are produced
during the transition.
– Outputs appearing on the branches are continuously available while in a present
state and the indicated inputs are applied.
False Outputs in a Mealy network
• The values of the external input variables may
change at any time during the clock period.
• Although these input changes can
continuously affect the network outpus, the
consequences of these input changes do not
appear in the listing of the output sequence.
Timing Diagrams to Illustrate
False Outputs
Design of clocked Synchronous Sequential
Network
Design procedures or methodologies specify
hardware that will implement a desired
behavior.
The design effort for small circuits may be
manual, but industry relies on automated
synthesis tools for designing massive
integrated circuits
CSSN Design Steps
1. From the word description and specifications
of the desired operation, derive a state
diagram for the circuit.
2. Reduce the number of states if necessary.
3. Assign binary values to the states.
4. Obtain the binary-coded state table.
5. Choose the type of flip-flops to be used.
6. Derive the simplified flip-flop input equations
and output equations.
7. Draw the logic diagram.
Qn. Design a circuit that detects a sequence of
three or more consecutive 1’s in a string of bits
coming through an input line
• Step 1: State diagram
2. Reduce the number of states if necessary.
3. Assign binary values to the states.
4. Obtain the binary-coded state table.
5. Choose the type of flip-flop: We choose two D flip-
flops to represent the four states, and we label their outputs
A and B . There is one input x and one output y . The
characteristic equation of the D flip-flop is Q(t + 1) = DQ
6. Derive the simplified flip-flop input equations
and output equations.
• Q
• 7. Draw the logic diagram.
Synthesis Using JK and T Flip-Flops
The manual synthesis procedure for sequential
circuits with JK,T flip-flops are the same as with D
flip-flops, except that the input equations must be
evaluated from the present state to the next-state
transition derived from the excitation table.
Synthesis Using JK Flip-Flops
Qn. Design a three-bit binary counter using T flip flops
• Step 1:state diagram
Algorithmic State Machines -
ASM
Partition the system into two parts:
Controller - ASM.
Controlled architecture – data processor.
ASM
Algorithm is a well defined procedure
consisting of a finite number of steps
to the solution of a problem.
Controller
is a hardware algorithm or
Algorithmic State Machine.
ASMscan serve as stand-alone
sequential network model.
ASM
Conditional outputs – Mealy model.
State outputs – Moore model.
State time:
Transition period.
Stable period.
ASM
State box.
Represents one
state in the ASM.
May have an
optional state
output list.
Single entry.
Single exit to state
or decision boxes.
ASM
Decision box.
Provides for next
alternatives and
conditional outputs.
Conditional output based on
logic value of Boolean
expression involving external
input variables and status
information.
Single entry.
Dual exit, denoting if
Boolean expression is true
or false.
Exits to decision, state or
conditional boxes.
ASM
Conditional output box
Provides a listing of
output variables that
are to have a value
logic-1, i.e., those
output variables being
asserted.
Single entry from
decision box.
Single exit to decision
or state box.
ASM
Blocks
Consists of the interconnection of a single
state box along with one or more decision
and/or conditional boxes.
It has one entry path which leads directly
to its state box, and one or more exit
pathes.
Each exit path must lead directly to a state,
including the state box in itself.
A path through an ASM block from its state
box to an exit path is called a link path.
ASM Block Example
ASM
An ASM block
Blocks
describes the operation of the
system during the state time in which it is in the
state associated with the block.
The outputs listed in the state box are
asserted.
The conditions indicated in the decision boxes are
evaluated simultaneously to determine which link
path is to be followed.
If a conditional box is found in the selected path
then the outputs found in its output list are
asserted.
Boolean expression may be written for each link
path. The selected link paths are those that
evaluate to logic-1.
ASM Blocks
ASM Block : An Example
Each block in the ASM chart describes the state of the system
during one clock‐pulse interval
Associated with state S_0 are two decision boxes and one
conditional box
The operations within the state and conditional boxes are initiated
by a common clock pulse when the state of the controller transitions
from S_0 to its next state
The same clock pulse transfers the system controller to one of the
next states, S_1, S_2, or S_3, as dictated by the binary values of E
and F
The Moore‐type signal incr_A is asserted unconditionally while
the machine is in S_0 ; the Mealy‐type signal Clear_R is generated
conditionally when the state is S_0 and E is asserted
In general, the Moore‐type outputs of the controller are generated
unconditionally and are indicated within a state box; the Mealy‐type
outputs are generated conditionally and are indicated in the
conditional boxes connected to the edges that leave a decision box.
Development of ASM chart from state
diagram
T h e r e a r e two t y p e s of m a c h i n e s
1 . M EA LY MA C H I N E 2 . M O O R E MAC H I N E
1. M EA LY MA C H I N E : O u t p u t is f u n c t i o n of b o t h i n p u t & p r e s e n t s
tate
S t e p s f o r m a k i n g AS M c h a r t
i ) R e p r e s e n t s t a t e by s t a t e b o x e s .
ii) A f t e r e a c h b o x p u t i n p u t in e a c h b o x .
iii) D e p e n d i n g on v a l u e s of o u t p u t place t h e c o n d i t i o n a l
b o x in p a t h s wh e re it will be “ 1 ” .
i v ) D e p en d i n g on v a l u e s of i n p u t c o n n e c t t h e p a t h to n e x t s t a te bo x .
Example of development of ASM chart from Mealy
Machine Consider the Mealy state graph of 111
detector.
2. MOORE MACHINE : Output depends on present state
Steps
1. For each state draw state box put output in state box if it is 1.
2. Put input in decision box after each state box.
3. Connect next state link by inspecting state graph.
Example: Consider 111 sequence detector.
Iterative circuits
An iterative comparator circuit
