CSIS 3510 Computer Organization and Architecture

Topics covered in this lecture: Review of DeMorgans Theorem Using DeMorgans Theorem Building a 2-bit decoder Algebraic Reduction of Boolean Expressions 7-segment decoder

DeMorgans Theorem On of the most useful principles in boolean algebra is DeMorgans Theorem, which allows one to switch between ANDs and NORs and ORs and NANDs. Remember, we want to design circuits using AND and OR, but then implement them using NAND and NOR (AND transistor bleedthrough problem, and manufacturing layering minimization) NOT terms or Inverted terms are represented with a line over the terms

AB = A + B A + B = AB
We demonstrated the validity of DeMorgans by Perfect Induction, using a truth table.

Using DeMorgans Theorem To convert A+B into a form that can be implemented using a NAND gate follow these steps: 1. Double Complement the term A+B = A+B 2. Use DeMorgans to distribute one of the complements A+B = A B The equation is now a NAND of the complemented inputs. To convert AB into a form that can be implemented using a NOR gate follow these steps: 1. Double Complement the term AB = AB 2. Use DeMorgans to distribute one of the complements AB = A + B The equation is now a NOR of the complemented inputs.

Extracting a function from a truth table and converting A 0 0 1 1 B 0 1 0 1 Output 0 1 0 Out = A B 0 DoubleC A B DeM A+B Simplify A + B

Two-Bit Decoder A 0 0 1 1 B 0 1 0 1 F0 1 0 0 0 F1 0 1 0 0 F2 0 0 1 0 F3 0 0 0 1

F0 = A B = A B = A+B = A+B
F1 = A B = A B = A+B = A+B F2 = A B = A B = A+B = A+B F3 = A B = A B = A+B

Two-Bit Decoder Diagram

A A B B
F0 F1 F2 F3

Algebraic Reduction of Boolean Functions Algebraic reduction is used to minimize a function extracted from a truth table or other source. Principle is to look for terms where a single variable is present in both complemented and positive form. Those variables can be deleted from those terms. Note: terms can be used over in multiple minimizations. Examples

A B + A B = B, AB+AB=A ABC+ABC=AB ABC+ABC+ABC+ABC AB AB A

7-Segment Display Decoder 7 Segment Display:

0 6 1

5
4 3

Displaying 0, 1, 2, 3

7-Segment Display Truth Table (Displaying values from 0-3 only)

AB 0 0 0 1 1 0 1 1

F0 1 0 1 1

F1 1 1 1 1

F2 1 1 0 1

F3 1 0 1 1

F4 1 0 1 0

F5 1 0 0 0

F6 0 0 1 1

Extracting and Minimizing Segment Functions

F0 = F1 =

F2 =
F3 = F4 = F5 = F6 =

Extracting and Minimizing Segment Functions

F0 = F1 =

F2 =
F3 = F4 = F5 = F6 =

Extracting and Minimizing Segment Functions

F0 = F1 =

F2 =
F3 = F4 = F5 = F6 =

7-Segment Display Decoder Diagram

Conclusion

Topics covered in this lecture: Review of DeMorgans Theorem Using DeMorgans Theorem Building a 2-bit decoder Algebraic Reduction 7-segment decoder Questions?