Programmable ASIC logic cells

Rohan Kelkar

Xilinx LCA

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Rohan Kelkar

XC3000 CLB
A 32-bit look-up table (LUT), stored in 32 bits of SRAM, provides the ability to implement combinational logic. To implement the function F=A.B.C.D.E, set the contents of LUT cell number 31 (address 11111) to a 1 and all others 0. CLB propagation delay is fixed (the LUT access time) and independent of the logic function
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 7 inputs to the XC3000 CLB: 5 CLB inputs (A-E), and 2 flipflop outputs (QX and QY) 2 outputs from the LUT (F and G). Since a 32-bit LUT requires only five variables to form a unique address (32=25), there are several ways to use the LUT: Use 5 of the 7 possible inputs (A-E,QX, QY) with the entire 32-bit LUT (the CLB outputs (F and G) are then identical) Split the 32-bit LUT in half to implement 2 functions of 4 variables eaach; choose 4 input variables from the 7 inputs (A-E, QX, QY). You have to choose 2 of the inputs from the 5 CLB inputs (a-E); then one function output connects to F and the other output connects to G. You can split the 32-bit LUT in half, using one of the 7 input variables as a select input to a 2:1 MUX that switches between F and G to implement some functions of 6 and & variables).
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XC4000 Logic Block

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Rohan Kelkar

XC5200 Logic Block

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Rohan Kelkar

Xilinx CLB Analysis

The use of LUT has advantages and disadvantages:
An inverter is as slow as a five-input NAND A LUT simplifies timing of synchronous logic Matched to large SRAM programming technology

Xilinx uses two speed-grade systems:

Maximum guaranteed toggle rate of a CLB flip-flop (in MHz) as a suffix higher is faster Example: Xilinx XC3020-125 has a toggle frequency of 125MHz Delay time of the combinational logic in a CLB in ns-lower is faster Example: XC4010-6 has tILO=0.6ns Correspondence between grade and tILO is fairly accurate for the XC2000, XC4000, and XC5200 but not for the XC3000
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Xilinx LCA Timing Model (XC5210-6)

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Rohan Kelkar

Altera FLEX

a) Chip floorplan b) LAB (Logic Array Block)

14-02-2012 Rohan Kelkar

c) Details of Logic Element (LE)

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Altera MAX

A registered PAL with i inputs, j product terms,and k macrocells

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a) Organization of logic and interconnect b) A MAX family LAB c) A MAX family macrocell 14-02-2012 Rohan Kelkar

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Characteristics
A typical MAX 5000 chip has : 8 dedicated inputs (with both true and complement forms); 24 inputs from the chipwide interconnect; and either 32 or 64 shared expander terms MAX 7000 LAB has 36 inputs from the chipwide interconnect and shared expander terms MAX 9000 LAB has 33 inputs from the chipwide interconnect and 16 local feedback inputs

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Rohan Kelkar

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Features
Logic expanders and expander terms (helper terms) increase term efficiency Shared logic expander (shared expander, intranet) and parallel expander (internet) Deterministic architechure allows deterministic timing before logic assignment Any use of two-pass logic breaks deterministic timing Programmable inversion increases term efficiency
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Timing model
a) a) A direct path through the logic array and a register b) Using a parallel expander

b)

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Rohan Kelkar

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Power dissipation in Complex PLDs

A programmable-AND array in an y PLD built using EPROM or EEPROM transistors uses a passive pull-up and these macrocells consume static power. Altera uses a switch called the Turbo Bit to control the current in the Pragrammable-AND array in each macrocell.

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Rohan Kelkar

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AC Input
Eg. An A/D converter running at 100 KHz connected to FPGA running at 10 MHz If we change the data input to a flip-flop (or a latch) too close to the clock edge (called a setup or hold-time violation), we run into a problem called metastability If the flip-flop makes a decision, at a time tr after the clock edge, as to whether its output is a 1 or a 0, there is a small, but finite, probability that the flip-flop will decide the output is a 1 when it should have been a 0 or vice versa. This situation is called Upset

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Rohan Kelkar

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 Experimentally probability of upset, p, is

p = T0 exp

(per data event, per clock edge, in one second, with units Hz-1.Hz-1.s-1) where is the time a sampler have to resolve the sampler output; T0 and are constants of the sampler circuit design.
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 The mean time between upsets (MTBU) is

T0

Where fclock is the clock frequency and fdata is the data frequency. Eg. If =5ns, =0.1ns, fclock =100 MHz and fdata =1 MHz, then MTBU=5.2 x 108seconds 16 years For 64-bit input bus using 64 flip-flops, our system level MTBF is three months. For 1000 systems shipped an average of 10 systems will fail everyday
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 is the inverse of the gain-bandwidth product of the sampler at the instant of sampling Independent of positive or negative data edge Determined by small-signal analysis T0, function of process technology and circuit design Cannot be changed Only parameter that can be changed is by connecting two flip-flops in series Synchronizer, built from two flip-flops in cascade, greatly reduce the effective values of and T0 over a single flipflop. The penalty is an extra clock cycle of latency.

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