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Internal mode
An external crystal oscillator is connected
between pin X1 and X2.
The mode select pins are provided with +VDD [1]. X1 Crystal
The internal oscillator generates the clock signal DSP Chip
X2
Oscillator
X1 No Connection
DSP Chip
X2 External Clock input
Timer programming
For the divide down count value less than 16, first set of counter is used and for divide
down count more than 16, either second set of counter or both counters can be used.
Dr. M. Bhaskar, Professor, ECE, NIT, Trichy-15
10
Serial port
Serial port interfaces provide full duplex, bidirectional, communication with
serial devices such as codecs, serial analog to digital (A/D) converters, and
other serial systems.
The serial port interface signals are directly compatible with many industry-
standard codecs and other serial devices.
The serial port may also be used for inter-processor communication in
multiprocessing applications
Both receive and transmit operations are double-buffered, thus allowing a
continuous communications stream with either 8- or 16-bit data packets.
The maximum operating frequency for the standard serial port of one-fourth
of CLKOUT (10 Mbit/s at 25 ns, 12.5 Mbit/s at 20 ns) is achieved when using
internal serial port clocks.
Serial port pins
CLKR CLKR - Receive clock signal
CLKX CLKX - Transmit clock signal
FSR FSR - Receive frame synchronization signal
DSP chip FSX FSX - Transmit frame synchronization signal
DR DR - Receive serial data
DX DX - Transmit serial data
Dr. M. Bhaskar, Professor, ECE, NIT, Trichy-15
11
Serial port cont…
Serial port registers
• Serial port operates through three MMREGs (SPC, DXR, and DRR) and
• Two other registers (RSR and XSR),are not directly accessible to the program
• All the registers are 16-bit size
SPC – Serial Port Control register
DXR – Data Transmit register
DRR – Data receive register
XSR – Data transmit shift register
RSR – Data receive shift register
Serial port modes of operation
• Burst mode
There are periods of serial port inactivity between packet transmits.
The data packet is marked by the frame sync pulse occurring on FSX
• Continuous mode
In continuous mode, a frame sync on FSX/FSR is not necessary for consecutive packet
transfers at maximum packet frequency after the initial pulse.
Memory pins
CS - Chip select
EN - Data bus direction enable
A15-A0 - Address lines
D15-D0 - Data lines
RD - Read enable
WE - Write enable
For 64K x 16 bit memory DSP and memory buses are directly connected.
If the speed of memory is slower, then software programmable wait state generator is
used to introduce wait states to a maximum of 7 clock cycles for PM, DM and I/OM
spaces.
For 64K x 8 bit memory two 64K x 8 bit memory chips are connected in parallel, with 8
LSB bits of data line connected to chip 1 & MSB 8 bits of data line connected to chip 2.
For memory space less than 64Kx 16 bits, memory chip select is signal is activated with
the help of decoding gates, designed with inputs from MSB bits of address lines and
PS/DS/IS signals
End of Part-6