What is Digital Computer?

 It is a programmable electronics machine

that processes binary data.
 It consists of four sections- Input ,
CPU(Central processing unit) , memory and
output
Memory

Input CPU Output

 What is Micro-Computer?
 CPU of a digital computer is replaced by µP .
It is called as µComputer.

Memory

Input Microprocessor Output

 Types of processors
1. Microprocessors: 4004, 8008, 8085, 8086…P-I, P-II……Itanium-I, I-
II…
2. Micro-controllers:
8051: Intel, Dallas Semiconductor, Phillips, Atmel…
PIC: Peripheral Interface Controller (PIC) developed by a
Microchip Pvt Ltd
AVR: Alf-Egil Bogen and Vegard Wollan/Advanced Virtual
RISC(reduced instruction set computer) by Atmel
Corporation(AVR based Arduino board)
ARM: Advanced RISC Machine developed by Advanced RISC
Machines (ARM) Pvt Ltd.
3. DSP: TMS320, Digital Signal Processor by Texas Instrument Pvt Ltd
4. CPLD/FPGA: Complex Programmable logic devices/Field
Programmable Gate Arrays developed by Xilinx Pvt Ltd
 Micro-controller
Definition:-
It is a microprocessor unit that includes
memory, Input, output, interfacing lines, A/D
convertor, Timer etc on a single chip.
It is highly integrated circuit that includes CPU,
memory, Input, output, interfacing lines, A/D
convertor, Timers etc on a single chip.
Examples:- in video games, VCRs, microwave
ovens etc.
• 8085
 Year of introduction:- 1976 to1977
 No. of transistor :- 6500
 No. of pins :-40
 Data bus (word length):-8
 Address bus:-16
 Memory addressing:-64 KB
 Clock speed:-3/5 MHZ
• Itanium II:-
 Year of introduction:- 2002
 No. of transistor :- 325M
 No. of pins :-423 PGA
 Data bus (word length):- 64
 Memory addressing:-64GB
 Clock speed:-1.3-1.5 GHZ
Architecture of 8085
 Architecture of 8085
• Memory and I/O control Lines:
 R/W, IO/M, Ready/Wait, ALE
 Status Lines, Address Lines, Data Lines

• CPU and Bus Control Lines:

 Reset, Interrupts,
 Bus Request

• Utility Lines:
 Clock, I/O Lines
 Power Supply Lines.
Bus structure of Microprocessor(µ.p)
 Clock speed:- Determines how many instructions per
second the processor can execute.

 Bus:- A set of parallel connecting lines is called as bus.

It is bidirectional bus.

 Address bus:- The bus over which the cpu sends out
the address of the memory location is called as
Address bus. If there are N address lines then it can
directly address 2N Memory locations. It is
unidirectional bus.
 Data bus:-The bus which is used to transfer the data
from cpu to memory and vice versa. The number of
data lines used in the data bus is equal to the size of
the data word .It is bidirectional bus.
 Control bus :- used for sending control signals to the
memory and Input/output devices.
Arithmetic logic unit(ALU)
 Operations performed by ALU
• Addition
• Subtraction
• Logical AND
• Logical OR
• Logical Exclusive OR
• Complement
• Increment/decrement by 1
• Rotate left, rotate right
 Registers
• Flag Register: It indicates arithmetic
conditions such as carry bit, called status
register.
CY/CS:
• This flag bit is effected after an 8-bit addition or subtraction.
• It is used to detect errors in unsigned arithmetic operations.

AC:
• This bit is set, if there is a carry from D3 to D4 during an ADD or SUB operation.
.
P:
• It reflects the no. of 1’s in the Accumulator register only.
• If A contains an even no. of 1’s, then P=0 vice versa.

S: It reflects sign bit(MSB) of the result

• For minus(-) sign= 1
• For plus(+) sign =0
Z: It reflects zero flag if result of accumulator is zero, then z=1 and if result is not zero,
then z=0.
8 Bit registers:
A, B,C,D,E,H,L
Temporary 8 bit registers: W,Z
16 bit registers:
B-C, D-E, H-L
Special type 16 bit registers:
PC(Program counter): Microprocessor uses the PC register to sequence the
execution of the instructions. The function of the program counter to be
point to the memory address from which the next byte is to be fetched.
When a byte is being fetched, the program is incremented by one to point
to the next location.
SP(Stack pointer): The stack pointer is also 16 bit register used as a
memory pointer. It points to a memory location in R/W memory, called the
stack.
Fetch Cycle
Fetch Execution
 Interrupt
Interrupt:

• It means interrupting the normal execution of the

microprocessor.

• When microprocessor receives interrupt signal, it discontinues

whatever it was executing.

• It starts executing new program indicated by the interrupt

signal.

• Interrupt signals are generated by external peripheral devices.

• After execution of the new program, microprocessor goes

back to the previous program.

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 Classification of Interrupts
• Maskable and Non-Maskable

• Vectored and Non-Vectored

• Edge Triggered and Level Triggered

• Priority Based Interrupts

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 Maskable Interrupts
• Maskable interrupts are those interrupts
which can be enabled or disabled.

• Enabling and Disabling is done by

software instructions.

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 Maskable Interrupts
• List of Maskable Interrupts:

• RST 7.5

• RST 6.5

• RST 5.5

• INTR
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 Non-Maskable Interrupts
• The interrupts which are always in
enabled mode are called non-maskable
interrupts.

• These interrupts can never be disabled

by any software instruction.

• TRAP is a non-maskable interrupt.

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 Vectored Interrupts
• List of vectored interrupts:

• RST 7.5

• RST 6.5

• RST 5.5

• TRAP
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 Vectored Interrupts
The addresses to which program control
goes:
Name Vectored Address
RST 7.5 003C H (7.5 x 0008 H)
RST 6.5 0034 H (6.5 x 0008 H)
RST 5.5 002C H (5.5 x 0008 H)
TRAP(RST4.5) 0024 H (4.5 x 0008 H)

Absolute address is calculated by

multiplying the RST value with 0008 H.
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 Non-Vectored Interrupts
• The interrupts which don't have fixed
memory location for transfer of control
from normal execution.

• The address of the memory location is

sent along with the interrupt.

• INTR is a non-vectored interrupt.

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 Edge Triggered Interrupts
• The interrupts which are triggered at
leading or trailing edge are called edge
triggered interrupts.

• RST 7.5 is an edge triggered interrupt.

• It is triggered during the leading

(positive) edge.

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 Level Triggered Interrupts
The interrupts which are triggered at high
or low level are called level triggered
interrupts.

RST 6.5
RST 5.5
INTR

TRAP is edge and level triggered interrupt.

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 Priority Based Interrupts
• Whenever there exists a simultaneous
request at two or more pins then the pin
with higher priority is selected by the
microprocessor.

• Priority is considered only when there

are simultaneous requests.

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 Priority Based Interrupts
• Priority of interrupts:

Interrupt Priority
TRAP 1
RST 7.5 2
RST 6.5 3
RST 5.5 4
INTR 5

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 Instruction Format
• Instruction word size

• The 8085 instruction set is classified into the

following three groups according to word size:

• 1. One-word or 1-byte instructions

• 2. Two-word or 2-byte instructions
•  3. Three-word or 3-byte instructions
One-Byte Instructions
Two-Byte Instructions
Three-Byte Instructions
OCR( Operation code register): The OCR is used to hold the op-code of the instruction currently being executed. The control unit
uses the contents of the OCR to determine the action required.
TAR(Temporary address register) : The TAR is used to hold the operand of the instruction if it is to be treated as an address. It
outputs to the address bus.
TDR(Temporary data register): The TDR is used to hold data, which are to be operand on by the ALU, its output is therefore to an
input of the ALU.