ALGORITHM FOR ASYMMETRIC SOURCE

CONFIGURATION IN A NEWLY CONSTRUCTED

MULTISTRING MULTILEVEL INVERTER TOPOLOGY
Krishna Kumar Gupta*, Shailendra Jain

Maulana Azad National Institute of Technology Bhopal, India,

*
kk_mact@rediffmail.com,

sjain68@gmail.com



Keywords: Multilevel inverters, cascaded H-bridge topology,
reduced device count, symmetric and asymmetric source
configurations.
Abstract
This paper proposes an algorithm to configure asymmetric
sources for a recently proposed topology for multilevel
inverters. Since the topology proposed by Yi-Hung Liao et. al
[8] is incapable of synthesising all additive and subtractive
combinations of input DC levels (as happens in cascaded H-
bridge inverter), various popular asymmetric configurations
cannot be employed for it. The proposed algorithm is
described in detail and it is shown that it helps to synthesise
multilevel waveform with equal sized steps.

1 Introduction

Multilevel voltage source inverters are considered cost-
effective and efficient solution especially for high
power/medium voltage DC to AC conversion. A multilevel
inverter (MLI) utilises multiple input DC sources to
synthesise a staircase waveform. As a result of this approach,
voltage stresses across the power switches are lower as
compared to the output voltage level. Moreover, the stepped
waveform exhibits a better harmonic profile as compared to a
two level waveform produced by the conventional inverters.
Other advantages oI using MLI`s are higher eIIiciency,
reduced dv/dt stresses on the load and possibility of fault
tolerant operation [1, 2].
An important limitation oI MLI`s is requirement oI increased
number of power semiconductor devices (and accompanying
gate driver circuits) for increased number of output levels [3].
This makes the overall system expensive and complex.
ThereIore, practical implementation oI MLI`s demands
reduction in number of switches and gate driver circuits. As a
result, attempts have been made by researchers to propose
newer topologies with reduction in device count [4-8].
Focus of work presented here is a recently proposed MLI
topology Ior distributed energy resources (DER`s) |8|. Yi-
Hung Liao et. al [8] have proposed a newly-constructed five-
level multistring inverter topology for DERs. As shown in
Fig.1 (a), the aforesaid topology requires only six active
switches instead of the eight required in the conventional
cascaded H-bridge (CHB) multilevel inverter (Fig.1 (b)). It
was established in [8] that the newly-constructed inverter
topology offers advantages such as improved output
waveforms, smaller filter size, lower EMI and lesser total
harmonic distortion (THD). However, in literature [8], the
treatment of the aforesaid topology was limited to a five level
output with symmetrical input DC sources.
In this paper, a generalised structure of the topology is
presented in Section 2. This section also discusses the concept
of symmetric and asymmetric source conIigurations in MLI`s.
In Section 3 an algorithm is proposed for asymmetric source
configuration for the proposed topology. Simulation results
for the proposed algorithm are shown in Section 4.
Conclusions are presented in Section 5.

2 Generalised Structure of Topology Proposed
in [8]

As shown in Fig.1 (a), the topology in question contains six
active switches and two isolated DC sources for a five level
output. An alternative structure of this topology is shown in
Fig.2. It can be noted that the consecutive sources are cross-
connected i.e. the higher potential terminal of source V
s1
is
connected to the lower potential terminal of the source V
s2

through a power switch. Similarly, the higher potential
terminal of source V
s2
is connected to the lower potential
terminal of source V
s1
through a power switch. A similar
scheme of connections can be extended for increased number
of input DC sources. For n number of DC sources, the
generalised structure of the topology is shown in Fig. 3. It
would need 2n 2` power switches. For the same number oI
DC sources, a CHB topology would require 4n` power
switches [9].
The DC sources V
sk
(k = 1 to n) can be configured as
symmetric or asymmetric. A brief description of source
configuration is made below.

2.1 Source Configurations in MLIs
The concept behind a multilevel waveform synthesis is to
utilise multiple input DC sources. Multiple input DC sources
can be obtained mainly in two ways:
(i) using electrically isolated DC sources.
(ii) using multiple capacitors in series so as to sub-divide the
input voltage from a single DC source.
The first approach leads to requirement of large number of
sources. Also, equal load sharing among them is a desirable
and challenging task. On the positive side, there are no
voltage balancing problems. The second approach does not
need many DC sources but capacitor voltage balancing
remains an important issue especially for increased number of
levels in the output.

Vs1
+
Vs2
_
vo

(a)

Vdc
+
Vdc
_
vo

(b)
Fig.1. (a) Five level inverter as proposed in [8]
(b) CHB topology for five level output

Vs1
Vs2
S1 S1'
SU
SU
SL SL
AC
LOAD

N
1
2
+
_
vN
iL

Fig.2. Alternative form for the structure shown in Fig.1 (a)

The topology discussed in this paper uses the first approach,
namely, using multiple isolated input DC sources. Based on
their values, the source configuration are categorised as:



Vs1
AC
LOAD
+
_
v
O
iL
Vs2
Vs n-1
Vs n

Fig.3. Generalised structure for the topology proposed in [8]

(a) Symmetric Source Configuration:
When all the input DC sources have equal values, the
configuration is designated as a symmetric source
configuration. That is,

V
s1
= V
s2
= ... = V
sk
= ... = V
DC
(1)

Based on the topology, such configuration may offer
advantages like modularity and possibility of equal load
sharing amongst the sources. However, for a given number of
output levels, such configuration needs more power switches
as compared to an asymmetric configuration.

(b) Asymmetric Source Configuration
When two or more of the input DC sources have unequal
values, the configuration is designated as an asymmetric
source configuration. Such a configuration enables lesser
number of power switches to be used for the same number of
output levels as compared to a symmetric configuration.
However, it may lead to loss of modularity (if any) in the
structure. Also, it may not always be possible to achieve equal
load sharing amongst the sources [10]. Some of popular
asymmetric source configurations are [10,11]:

(i) Binary configuration: It consists of DC sources having a
geometric progression with a Iactor oI 1/2` i.e.

2
=

3
= =

(1)

= 2 (2)
Binary configuration does not permit equal load sharing
amongst the sources.

(ii) Trinary configuration: It consists of DC sources having a
geometric progression with a Iactor oI 1/3` i.e.

2
=

3
= =

(1)

= 3 (3)
Trinary configuration does not permit equal load sharing
amongst the sources.

(iii) As proposed in [10]: In this configuration, one source has
voltage V
DC
while all other sources have values 3V
DC
, that is,

V
s1
= V
s2
=... = V
sk
=...=V
sn-1
= 3V
DC
; and V
sn
= V
DC
(4)

Such a configuration partially incorporates the advantages of
trinary configuration along with the possibility of equal load
sharing.

(iv) As proposed in [11]: In this configuration, one source
has voltage V
DC
while all other sources have values 2V
DC
, that
is,

V
s1
= V
s2
=... = V
sk
=...=V
sn-1
= 2V
DC
; and V
sn
= V
DC
(5)

Such a configuration partially incorporates the advantages of
binary configuration along with the possibility of equal load
sharing.

3 Proposed Algorithm for Source Configuration

As mentioned in the previous section, using an asymmetric
configuration leads to further reduction in number of switches
in a given topology with separate DC sources. However, for
the proposed topology, the asymmetric configurations
discussed in previous section cannot be implemented
satisfactorily. For example, if the multistring topology is
simulated using a trinary source configuration with V
s1
= 100
V and V
s2
= 300V, all expected nine levels (-400V to 400V, in
steps of 100V each) are not synthesised. For a nine-level
inverter, carrier and reference signals are shown in Fig 4.
Such a configuration in CHB would synthesise nine levels
shown in Fig 5. However the multistring topology synthesises
seven levels with unequal step-sizes as shown in the
simulated waveform in Fig. 6.


Fig.4. Reference and carrier waveforms for a 9-level inverter


Fig.5. Output voltage waveform for a two-cell CHB inverter
with trinary configuration (V
s1
= 100 V and V
s2
= 300 V)



Fig.6. Output voltage waveform for the multistring inverter
with trinary configuration (V
s1
= 100 V and V
s2
= 300 V)


Similarly, if the multistring topology is implemented using
trinary configuration with three sources, the source values
would be: V
s1
= 100 V, V
s2
= 300V and V
s3
= 900V. Such a
configurations offers possibility of twenty-seven levels (-
1300V to 1300 V in steps of 100V each) which is achieved
with the CHB topology. However, the multistring topology
generates only fifteen levels viz. 0, 100, 300, 400, 800,
900, 1200 and 1300 V.

The aforesaid discussion indicates that the commonly used
asymmetric configurations cannot be implemented for the
multistring topology. The reason is that it does not synthesise
all additive and subtractive combinations of the input DC
levels. This can be inferred from Table 1. There are some
voltage levels which are skipped`. ThereIore, an appropriate
algorithm for asymmetric source configuration is required
which can synthesise maximum number of steps with equal
step size.


In order to obtain a multilevel waveform with equal step-size,
the aforesaid topology needs to use a natural number
sequence of sources i.e. V
DC
, 2V
DC
, 3 V
DC
, .... , nV
DC
.
Moreover, placing the sources at the correct positions is
equally important. It is determined that the position of sources
has to be as shown in Table 2, shown for up to ten DC
sources.

0.1 0.105 0.11 0.115 0.12 0.125 0.13 0.135 0.14
-4
-3
-2
-1
0
1
2
3
4
Time [sec]
R
e
f
e
r
e
n
c
e

a
n
d

C
a
r
r
ie
r

W
a
v
e
f
o
r
m
s
0.1 0.11 0.12 0.13 0.14 0.15 0.16
-400
-300
-200
-100
0
100
200
300
400
Time [sec]
O
u
t
p
u
t

V
o
l
t
a
g
e

[
V
]
0.1 0.11 0.12 0.13 0.14 0.15 0.16
-400
-300
-200
-100
0
100
200
300
400
Time [Sec]
O
u
p
u
t

V
o
l
t
a
g
e

[
V
]








Number
of Sources
Source
Designation
Possible Voltage
Levels
Presence of
Voltage Level in
the Multistring
Topology
Total number of
possible
combinations
Total number of
possibilities offered
by the Multistring
Topology
1 V
s1
0 Present 3 3
(V
s1
) Present
2 V
s1
, V
s2
0 Present 9 7
V
s1
Present
V
s2
Present
(V
s1
- V
s2
) Missing
(V
s1
+ V
s2
) Present
3 V
s1
, V
s2
, V
s3
0 Present 27 15
V
s1
Present
V
s2
Present
V
s3
Present
(V
s1
+ V
s2
) Present
(V
s1
V
s2
) Missing
(V
s1
+ V
s3
) Missing
(V
s1
V
s3
) Present
(V
s2
+ V
s3
) Present
(V
s2
V
s3
) Missing
(V
s1
+ V
s2
+ V
s3
) Present
(V
s1
+ V
s2
V
s3
) Missing
(V
s1
V
s2
+ V
s3
) Missing
(V
s1
V
s2
V
s3
) Missing
Table 1. Additive and subtractive combinations of input values and their presence/absence in the multistring topology






Number
of
Sources
Source Designation and their Values
V
s1
V
s2
V
s3
V
s4
V
s5
V
s6
V
s7
V
s8
V
s9
V
s10

1 V
DC

2 V
DC
2V
DC

3 V
DC
3V
DC
2V
DC

4 V
DC
3V
DC
4V
DC
2V
DC

5 V
DC
3V
DC
5V
DC
4V
DC
2V
DC

6 V
DC
3V
DC
5V
DC
6V
DC
4V
DC
2V
DC

7 V
DC
3V
DC
5V
DC
7V
DC
6V
DC
4V
DC
2V
DC

8 V
DC
3V
DC
5V
DC
7V
DC
8V
DC
6V
DC
4V
DC
2V
DC

9 V
DC
3V
DC
5V
DC
7V
DC
9V
DC
8V
DC
6V
DC
4V
DC
2V
DC

10 V
DC
3V
DC
5V
DC
7V
DC
9V
DC
10V
DC
8V
DC
6V
DC
4V
DC
2V
DC

Table 2 Proposed placement of voltage sources in the proposed topology for up to ten number of input sources








Accordingly, the proposed algorithm for asymmetric source
configuration in the multistring structure is:

(i) For even number of sources:

V
sj
= (2j - 1) V
DC
, for 1 _ j _ (n/2),

= 2(n +1 j) V
DC
, for [( n 2 )/2| _ j _ n (6)

(ii) For odd number of sources:

V
sj
= (2j - 1) V
DC,
Ior 1 _ j _ |(n + 1)/2],

= 2(n +1- j) V
DC
, for [(n 3)/2| _ j _ n (7)


4 Simulation Results and Comparison with
Symmetric Configuration

In order to substantiate the algorithm proposed in the previous
section, some simulation studies are carried out using
MATLAB/Simulink.

(i) Simulation Study I
Two sources with V
s1
= 100V and V
s2
= 200V are used for the
multistring structure and it is expected that it can synthesise
seven levels in equal steps of 100V. Simulation is carried out
with these values and the results are shown in Fig.7. The
results indicate that a seven level waveform is obtained with a
peak value of 300V and in equal steps of 100V.




Fig.7. Voltage waveform for Simulation Study I

(ii) Simulation Study II

Another inverter is simulated based on the multistring
topology with the following source values: V
s1
= 100V, V
s2
=
300V, V
s3
= 400V and V
s4
= 200V as shown in Fig. 8.

The output waveform is expected to consist of twenty-one
levels with an amplitude 1000V and in equal steps of 100V.
The simulated voltage waveform is shown in Fig.9. It is seen
that the output waveform achieves amplitude of 1000V in
equal steps of 100V.
V
s1
= 100V
i
o
(t)
v
o
(t)
AC
Load
+
_
+
_
+
_
+
_
V
s2
= 300V
V
s3
= 400V
V
s4
= 200V


Fig. 8 Multistring topology with four asymmetric sources



Fig.9. Voltage waveform for Simulation Study II


It can also be noted that for a seven level output, the topology
would require eight switches with symmetric source
configuration and six switches with the proposed algorithm
for asymmetric configuration. Also, for a twenty-one level
output, the topology would need twenty-two switches with
symmetric source configuration and ten switches with
asymmetric source configuration as proposed in the paper.
Thus, asymmetric source configuration would further reduce
the device count. A general comparison between number of
switches and number of voltage levels produced by the
multistring topology for the symmetric and the proposed
asymmetric configurations are shown in Fig.10.


0.1 0.11 0.12 0.13 0.14 0.15 0.16
-300
-200
-100
0
100
200
300
Time [sec]
O
u
p
u
t

v
o
l
t
a
g
e

[
V
]
0.1 0.11 0.12 0.13 0.14 0.15 0.16
-1000
-500
0
500
1000
Time [sec]
O
u
p
u
t

V
o
l
t
a
g
e

[
V
]


Fig 10. Number of power switches versus number of levels synthesized in the multistring topology with symmetric source
configuration and with proposed configuration


5 Conclusion

This paper presents a newly formed algorithm for asymmetric
source configuration in a recently proposed multistring
topology by Yi-Hung Liao et. al [8]. A generalized structure
of the multistring topology is formulated. It is shown that the
popular asymmetric configurations are not employable for the
multistring topology since it does not synthesize all additive
and subtractive combinations of the input DC values. The
proposed algorithm is shown to satisfactorily synthesize all
voltage levels with equal sized steps. It is shown that the
proposed algorithm significantly reduces the number of
power switches (and associated gate driver circuits).

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4 6 8 10 12 14 16 18 20
0
20
40
60
80
100
Number of Power Switches
N
u
m
b
e
r

o
f

L
e
v
e
l
s

i
n

O
u
t
p
u
t

W
a
v
e
f
o
r
m
With proposed
asymmetric configuration
With symmetric
configuration