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A new Hetero-material Stepped Gate (HSG) SOI LDMOS for RF Power Amplifier Applications

A new Hetero-material Stepped Gate (HSG) SOI LDMOS for RF Power Amplifier Applications

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23rd International Conference on VLSI Design, January 3 - 7, 2010, NIMHANS Convention Centre Bangalore, INDIA.
23rd International Conference on VLSI Design, January 3 - 7, 2010, NIMHANS Convention Centre Bangalore, INDIA.

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Published by: Mamidala Jagadesh Kumar on Feb 01, 2010
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A new Hetero-material Stepped Gate (HSG) SOI LDMOS for RF PowerAmplifier Applications
Radhakrishnan Sithanandam and M. Jagadesh Kumar,
Senior Member, IEEE 
 
 Department of Electrical Engineering  Indian Institute of Technology Delhi New Delhi, India 110016  E-mail: radhakrishnansj@gmail.com; mamidala@ieee.org 
Abstract
 In this paper, we propose a new hetero-material  stepped gate (HSG) SOI LDMOS in which the gate isdivided into three sections - an n
+
gate sandwiched between two p
+
gates and the gate oxide thicknessincreases from source to drain. This new device structure improves the inversion layer charge densityin the channel, results in uniform electric field distribution in the drift region and reduces the gate todrain capacitance. Using two-dimensional simulation,the HSG LDMOS is designed and compared with theconventional LDMOS. We demonstrate that the proposed device exhibits 28% improvement inbreakdown voltage, 32% reduction in on-resistance,13% improvement in transconductance, 9% reductionin gate to drain charge and 38% reduction in switching delay. HSG LDMOS may be effectivelydeployed in RF power amplifier applications.
1. Introduction
Laterally double diffused metal oxidesemiconductor (LDMOS) technology is one of themost attractive technologies deployed in RF power amplifier applications because of its ease in integrationto standard CMOS technology, high input impedanceat high drive current and thermal stability [1].Especially, silicon on insulator (SOI) LDMOS is moreattractive due to its inherent dielectric isolation, highfrequency performance and reduced parasitics [2].However, achieving enhancement in all performance parameters like breakdown voltage, on-resistance,transconductance, drive current, gate to drain chargeand switching characteristics is still an active area of research due to its tradeoffs [3]. For example, when weincrease the breakdown voltage of the LDMOS, on-resistance also increases [4]. Similarly, when gateoxide thickness is scaled down for improvingtransconductance, gate to drain charge increases andreliability of gate oxide becomes questionable [5].Therefore, the motivation of this work is to explorestructural changes in SOI LDMOS to improve thedevice parameters.In this paper, therefore, we propose a new
h
etero-material
s
tepped
g
ate (HSG) LDMOS to improve the breakdown voltage and transconductance, and reducethe on-resistance, gate-charge and switching delays.We demonstrate using two dimensional devicesimulations [6] that the hetero-material stepped gateresults in significant improvement in all the abovedevice parameters when compared with theconventional LDMOS.In section 2, the proposed device structure and itsfabrication procedure are explained. In section 3, weexplain the expected enhancements with the TCADsimulation results.
2. Device Structure and ProposedFabrication Procedure
The HSG LDMOS and the conventional LDMOSused for simulation are shown in Fig. 1. As shown inthe figure, in the case of HSG LDMOS, there are threesteps of gate oxide with thickness, 25 nm, 50 nm and150 nm from source end to drift region endrespectively. The first and third gates are made of p
+
  poly while middle gate uses n
+
poly. The physicaldimensions and doping profiles are same for theconventional and the proposed device except that in thecase of the conventional device, we have used a singlen
+
poly gate and the gate oxide is chosen to be 50 nm.The gate oxide thickness and gate work function (n
+
 and p
+
poly) combination of the proposed device ischosen such that the threshold voltage is approximatelysame as the reference device. The physical and doping parameters are shown in Table 1.
Conference Proceedings: 23rd VLSI Design - 9th Embedded Systems, January 2010. Copyright © 2010 IEEE. All rights Reserved.
 
 
Fig. 1. Cross sectional view of (a) conventionalLDMOS (b) HSG LDMOS.Table.1. Device parameters used insimulation
.Gate length,(L
G1
, L
G2
and L
G3
)0.3 µm, 0.7 µm and 0.4µmGate oxide thickness,(t
ox1
, t
ox2
and t
ox3
)25 nm, 50 nm and 150nmChannel length, L 0.5 µmBuried oxide thickness 400 nmSilicon thickness 1 µmDrift region length 2.3 µmSource/Drain doping 1×10 cm
-
 Drift region doping 2×10 cm
-
 Channel doping 10 cm
-
 Threshold voltage
1.85 V
Fig. 2. Process steps to fabricate HSG LDMOS.
Fig. 2 shows the proposed fabrication procedure of HSG gate LDMOS. This process is similar to themethod proposed by Xing et al [7]. The fabrication process begins with an SOI wafer with an n-siliconlayer with a doping of 2×10
16
cm
-3
. The first 0.3 µmlong p
+
poly gate is formed on a 25 nm thermallygrown gate oxide using standard photolithography asshown in Fig. 2 (a). Subsequently, a 50 nm lowtemperature oxide (LTO) and over that n
+
poly isdeposited. Using blanket reactive ion etching (RIE),the polysilicon layer is etched leaving a sidewall polysilicon layer as shown in Fig. 2(b) which will nowact as the second gate of 0.7
μ
m length. Now, wedeposit 100 nm LTO and over that p
+
poly is depositedand etched back to form 0.4 µm long third gate asshown in Fig. 2 (c). A chemical-mechanical polishing(CMP) process will planarize the gate as shown in Fig.2(d). Once the gate is defined, rest of the fabrication process is similar to the conventional LDMOSfabrication. After metallization process, source, drainand gate contacts are formed and all the three gatesshorted resulting in the final HSG LDMOS structureshown in Fig. 1(b).
3. Simulation results and discussion
We have created the conventional and proposeddevice structure in ATLAS, a two dimensional devicesimulator. The design of the LDMOS is doneaccording to RESURF principle [8]. The effect of hetero-material stepped gate on breakdown voltage,DC characteristics, gate charge transients andswitching characteristics are discussed below.
 
 
Fig. 3. Breakdown voltage of conventional andHSG LDMOS.Fig. 4. Electric field distribution along thesurface of conventional and HSG LDMOS at adrain voltage of 40 V.
3.1. Breakdown Voltage
Breakdown voltage of LDMOS is the drain voltage atwhich the off state current rises abruptly with theincrease in drain voltage (we have taken this draincurrent as 1 pA/µm). The breakdown voltagecharacteristics of the HSG LDMOS and theconventional device are shown in Fig. 3. It can be seenthat the proposed device exhibits an enhanced breakdown voltage by about 29% compared to theconventional LDMOS.The stepped gate in the drift region enhances RESURFand introduces additional electric field peaks as shownin Fig. 4. These additional peaks reduce the mainelectric field peak from 7.1 ×10
5
V/cm to 4 ×10
5
V/cmand also smear the electric field uniformly resulting inimproved breakdown voltage.
Fig. 5. Output characteristics of conventionaland HSG LDMOS.Fig. 6. On-resistance of conventional and HSGLDMOS.
3.2. DC Characteristics
The output characteristics of the HSG LDMOS and theconventional LDMOS are shown in Fig. 5, it can beobserved that the proposed device has higher draincurrent than the conventional device. The reduced gateoxide at the source end improves the channel chargedensity thereby increasing the drain current. Theimprovement in drain current is approximately 60% atV
GS
= 4 V and V
DS
= 20 V. Due to the improved draincurrent, specific on-resistance also decreases as shownin Fig. 6. The improvement in on-resistance is 32% atV
GS
= 6 V. Here, the specific on-resistance iscalculated as the ratio of drain current by drain voltage per unit area at the gate potential of 6 V. Furthermore,the HSG LDMOS shows 13% enhancement in peak transconductance than the conventional device asshown in Fig. 7. This improvement is again due to theimproved channel charge density.

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