This document lists various VLSI project topics related to digital design and FPGA implementation. Topics include an area-efficient cryptography processor, CSI multimedia architecture, software defined radio channelizer, orthogonal code convolution using FPGA, IEEE 1451.2 smart sensor modeling in VHDL, fuzzy PID controller in VHDL/Verilog, IEEE 802.11 WLAN baseband processor, lossless data compression algorithm and hardware, UART design with BIST capability, robust UART architecture, USB transceiver interface, digital watermarking architecture, low-power multiplier, reconfigurable coprocessor, low power dynamic memory, wireless OFDM timing synchronization, multi-mode RFIC digital front-end
This document lists various VLSI project topics related to digital design and FPGA implementation. Topics include an area-efficient cryptography processor, CSI multimedia architecture, software defined radio channelizer, orthogonal code convolution using FPGA, IEEE 1451.2 smart sensor modeling in VHDL, fuzzy PID controller in VHDL/Verilog, IEEE 802.11 WLAN baseband processor, lossless data compression algorithm and hardware, UART design with BIST capability, robust UART architecture, USB transceiver interface, digital watermarking architecture, low-power multiplier, reconfigurable coprocessor, low power dynamic memory, wireless OFDM timing synchronization, multi-mode RFIC digital front-end
This document lists various VLSI project topics related to digital design and FPGA implementation. Topics include an area-efficient cryptography processor, CSI multimedia architecture, software defined radio channelizer, orthogonal code convolution using FPGA, IEEE 1451.2 smart sensor modeling in VHDL, fuzzy PID controller in VHDL/Verilog, IEEE 802.11 WLAN baseband processor, lossless data compression algorithm and hardware, UART design with BIST capability, robust UART architecture, USB transceiver interface, digital watermarking architecture, low-power multiplier, reconfigurable coprocessor, low power dynamic memory, wireless OFDM timing synchronization, multi-mode RFIC digital front-end
• An Area-Efficient Universal Cryptography Processor for Smart Cards
• The CSI Multimedia Architecture • Fpga Based Power Efficient Channelizer for Software Defined Radio • Improvement Of The Orthogonal Code Convolution Capabilities Using Fpga Implementation • A Vhdl Model of a IEEE1451.2 Smart Sensor:Characterization And Applications • Fuzzy Based PID Controller Using VHDL/VERILOG for transportation Application • Implementation of IEEE 802.11 a Wlan Baseband Processor • A Lossless Data Compression and Decompression Algorithm and its Hardware Architecture • A Verilog Implementation of UART Design with Bist Capability • A Robust Uart Architecture Based On Recursive Running Sum Filter For Better Noise Performance • Fpga Implementation of USB Transceiver Macrocell Interface With Usb2.0 Specifications • A Vlsi Architecture For Visible Watermarking In A Secure Still Digital Camera (S2dc) Design (Corrected) • A Low-Power Multiplier With The Spurious Power Suppression Technique • Design Of Reconfigurable Coprocessor for Communication Systems • Block-Based Multiperiod Dynamic Memory Design For Low Data- Retention Power • A Symbol-Rate Timing Synchronization Method for Low Power Wireless Ofdm Systems • On The Design Of A Multi-Mode Receive Digital-Front-End For Cellular Terminal Rfics • Design Exploration of A Spurious Power Suppression Technique (Spst) And Its Applications • Implementation of A Multi-Channel Uart Controller Based On FIFO Technique and FPGA • Optimized Software Implementation of a Full-Rate IEEE 802.11a Compliant Digital Baseband Transmitter on a Digital Signal Processor
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Where Technology and Creativity Meet • An Fpga-Based Architecture for Real Time Image Feature Extraction • Fpga Based Generation of High Frequency Carrier for Pulse Compression Using Cordic Algorithm • Vlsi Architecture and Fpga Prototyping of a Digital Camera for Image Security and Authentication
Students can also send their Ideas/Journal Papers/IEEE papers to
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