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QBank_DPSD_cs2202

# QBank_DPSD_cs2202

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03/28/2013

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B.E./B.Tech. DEGREE EXAMINATION, November - 2009
Second Year - Third Semester
CS2202
–
DIGITAL PRINCIPLES AND SYSTEM DESIGN
Model Question Paper - I(Common to CSE and IT)(Regulation 2008)Time: Three Hours Maximum Marks: 100ANSWER ALL QUESTIONSPart
–
A (10 x 2 = 20 marks)
1. Convert the following number from one base to other.(354.52)
16
= ( )
10
(100)
10
= ( )
16.
2. What are the different ways to represent a negative number?3. What is logic synthesis?4. What is the need for code conversion? Give two commonly used codes.5. What is decoder? Draw the block diagram and the truth table for 2 to 4 decoder6. Give some applications of multiplexer.7. Convert a JK flip flop to T flip flop.8. What is the maximum range of a memory that can be accessed using 10 address lines?9. What is a hazard?10. What are the assumptions that must be made for fundamental mode circuit?
Part
–
B (5 x 16 = 80 marks)
11 (a) What is the advantage of using Tabulation method? Determine the prime implicantsof the following function using Tabulation method. (16)
F(w, x, y, z) = ∑ (1, 4, 6, 7, 8, 9, 10, 11, 15)
(or)(b) (i) Explain about common postulates used to formulate various algebraicstructures. (12)(ii) Given the following Boolean function
F = A’C + A’B + AB’C + BC
Express it in sum of minterms and find the minimal SOP expression. (4)
Reg.No:

12 (a) Design a BCD to 7 segment decoder. (16)(or)(b) With suitable block diagram explain the operation of BCD adder. (16)13 (a) Define decoder. Design a 3 to 8 decoder. With suitable block diagram explain how a4 to 16 decoder can be formed by using the same. (16)(or)(b) Construct a Full adder and write a HDL program module for the same. (16)14 (a) Explain the different types of shift registers with neat diagram. (16)(or)(b) Design a sequence detector to detect the sequence 101011. (16)15 (a) An asynchronous sequential circuit is described by the following excitation andoutput function.X = (Y
1
Z
1
’W
2
) + (Y
1
Z
1
W
2
)
S = X’
(i) Draw the logic diagram of the circuit.(ii) Derive the transition table and output map.(iii) Describe the behavior of the circuit (16)(or)(b) Explain essential, static and dynamic hazards in digital circuit. Give hazard-freerealization for the Boolean function.
F(I, J, K, L) = ∑(1, 3, 4, 5, 6, 7, 9, 11, 15) (16)

B.E./B.Tech. DEGREE EXAMINATION, November - 2009
Second Year - Third Semester
CS2202
–
DIGITAL PRINCIPLES AND SYSTEM DESIGN
Model Question Paper - II(Common to CSE and IT)(Regulation 2008)Time: Three Hours Maximum Marks: 100ANSWER ALL QUESTIONSPart
–
A (10 x 2 = 20 marks)
1. Simplify the following Boolean expression to a minimum number of literals:
A’B’+A’C’D’+A’B’D+ (AB)’CD’
2. Simplify the following Boolean function by Karnaugh map method:F (
A, B, C, D) = ∑
m (1, 5, 9, 12, 13, 15).3. Define combinational circuit.4. Draw a 2 to 1 multiplexer circuit.5. What is a priority encoder?6. State a limitation of RS flip flop.7. What is a binary counter?8. What are the models used to represent clocked sequential circuits?9. What are difference between PLA and PAL?10. What are assumptions made for pulse mode circuit?
Part
–
B (5 x 16 = 80 marks)
11 (a) Simplify the following Boolean Function F together with don’t care condition using
Karnaugh map method.
(i) F(A, B, C, D) = ∑m(0, 6, 8,13, 14), d(A, B, C, D) = ∑m(2, 4, 10) (6)

(ii) F(A, B, C, D) = ∑m(0, 2, 4, 5, 8, 14, 15), d(A, B, C, D) = ∑m(7, 10, 13) (5)

(iii) F(A, B, C, D) = ∑m(4, 6, 7, 8, 12, 15), d(A, B, C, D) = ∑m(2, 3, 5, 10, 11, 14) (5)
(or)(b) Simplify the following Boolean expressions to a minimum number of literals.
(i) ABC+ABC’+A’B (3)

(ii) A’BC+AC’+B’
(3)
(iii) (A+B)’(A’+B’) (
3)
Reg.No:

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