EXEPRIMENT NO: - 7(a)

OBJECTIVE: -To Design RS flip-flop using VHDL.

APPARATUS/TOOL REQUIRED: Xilinx ISE 10.1 synthesis and simulation tool.

LOGIC DIAGRAM:-

TRUTH TABLE:-

PROGRAM:-

Library IEEE;
Use IEEE.STD_LOGIC_1164.ALL;
Use IEEE.STD_LOGIC_ARITH.ALL;
Use IEEE.STD_LOGIC_UNSIGNED.ALL;

Entity srff is
Port (s,r.clk:in bit;
Q,qbar:out bit);
End srff;
Architecture behavioral of srff is
Begin
Process (s,r)
Begin
Assert (s=’1’ nand r=’1’)
Report “undefined o/p”;

1
If s=’1’ then
Q<=’1’;
Elsif r=’1’ then
Q<=’0’;
Else
Q<=’x’;
End if

end process;
Qbar<=not q;
End behavioral;

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