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EXPERIMENT-7

Aim Write a VHDL program for a FLIP-FLOP and check the waveforms and the hardware generated.

VHDL Code:library IEEE; use IEEE.STD_LOGIC_1164.all; entity SR_FF is port( S : in STD_LOGIC; R : in STD_LOGIC; PR : in STD_LOGIC; CLR : in STD_LOGIC; CLK : in STD_LOGIC; Q : buffer STD_LOGIC:='1' ); end SR_FF;

architecture SR_FF_BEHAVIOR of SR_FF is begin process(S,R,CLK,PR,CLR) begin if(PR='1' and CLR='0')then Q<='0'; elsif(PR='0' and CLR='1')then Q<='1'; elsif(PR='1' and CLR='1' and S='0' and R='0' and CLK='0' and CLK' event)then Q<=Q;

elsif(PR='1' and CLR='1' and S='0' and R='1' and CLK='0' and CLK' event)then Q<='0'; elsif(PR='1' and CLR='1' and S='1' and R='0' and CLK='0' and CLK' event)then Q<='1'; elsif(PR='1' and CLR='1' and S='1' and R='0' and CLK='0' and CLK' event)then Q<='U'; end if; end process; end SR_FF_BEHAVIOR;

WAVEFORM

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