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FPGA Implementation of Discrete Fractional Fourier Transform

FPGA Implementation of Discrete Fractional Fourier Transform

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Published by M V N V Prasad

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Published by: M V N V Prasad on May 16, 2011
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12/26/2012

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FPGA implementation of Discrete Fractional Fourier Transform
M.V.N.V.Prasad
†1
, K. C. Ray
†2
and A. S. Dhar 
Department of Electronics andCommunication Engineering,Indian Institute of Information Technology, Allahabad,Uttar Pradesh, India.Email:
1
mvnvprasad@gmail.com,
2
kcr@iiita.ac.in
Department of Electronics andElectrical Communication Engineering,Indian Institute of Technology, Kharagpur,West Bengal, India.Email: asd@ece.iitkgp.ernet.in
 Abstract– 
Since decades, fractional Fourier transform hastaken a considerable attention for various applications insignal and image processing domain. On the evolution of fractional Fourier transform and its discrete form, the realtime computation of discrete fractional Fourier transformis essential in those applications. On this context, we haveproposed new hardware architecture for implementing aDiscrete Fractional Fourier Transform (DFrFT) whichrequires hardware complexity of O(4N), where N istransform order. This proposed architecture has beensimulated and synthesized using verilogHDL, targeting aFPGA device (XLV5LX110T). The simulation results arevery close to the results obtained by using MATLAB. Theresult shows that, this architecture can be operated on amaximum frequency of 217MHz.
 Keywords– 
Discrete Fractional Fourier Transform,Hardware Architecture, CORDIC and FPGA.
I.
 
I
 NTRODUCTION
 ractional Fourier transform [1], [2],[3] has been anemerging mathematical tool, having wide area of signal [4], Image processing applications likeBiomedical signal detection[6], Image registration[7],Image Encryption[5], Security of registration data of fingerprint image[8], Broadband beam forming of LFMsignals[9] and Moving target detection and location inspace borne SAR.Unlike Discrete Fourier Transform (DFT), DiscreteFractional Fourier Transform (DFrFT) has manydefinitions, such as direct form, improved sampling-type,linear combination-type, eigenvectors decomposition-type [10], group theory-type and impulse train-typeDFrFT. Among these definitions, eigen vector decomposition type is to be a legitimate definition [11]to satisfy all the properties such as unitary, indexadditive, reduction to DFT when fractional value is one,approximation of continuous fractional Fourier transform.To the knowledge of authors on the evolution of Fractional Fourier transform and its application, nohardware architecture is available except [12] for realtime implementation of DFrFT. In our paper newhardware architecture for implementing DFrFT based oneigen vector decomposition have been proposed andimplemented on FPGA device for real time applications.The rest of this paper has been organized as fallows;Section II presents brief review on Fractional Fourier Transform and its discrete form. Section III describes the proposed hardware architecture. Results and discussionof this proposed implementation has been highlighted insection IV. Finally, section V concludes the paper withfuture scope of this work.II.
 
F
RACTIONAL
F
OURIER 
T
RANSFORM
 
 A.
 
Continuous Fractional Fourier Transform.
The generalized Fourier transform rotates the signalf(
u
) in time-frequency plane [1] on the rotation angle of (‘a’ is fractional value) and is given in fallowingequationHere ‘
v’ 
is the variable in a
th
order fractional domain and
u
’ is variable in fractional domain in order of zero.The kernel
 K 
α
(
u,v
) is decomposed as given in equation(2) in terms of Hermite-Gaussian function [2] which areeigen functions of the Fourier transform.The decomposed kernel is
ψ 
(u)
is the
th
order Hermite-Gaussian function,
 H 
is the
th
order Hermite polynomial.
 B.
 
 Discrete Fractional Fourier Transform
The discrete fractional Fourier transform has been proposed in [10] using discrete Hermite-Gaussianfunctions, for N-point as given in equation (3).Where u
[n] is
th
discrete Hermite-Gaussian function.The discrete values of continuous Hermite-Gaussianfunction
ψ 
(v)
are approximated by using eigen vectors of commuting matrix
S
in [10]. The N point DFrFT Matrixfor rotation angle
α
is defined [3] as
F
2
a
π
α
=
2
1/4
-
π
u
2
 
ψ 
(u)= H 
2
π 
u) e
2
k!
and
u
[m]e
-
 j
α
u
[n]F
α
[m,n] =
Σ
 N-1
 
k=0
(3)
-
α
(
v
) = f(
u
)
 K 
α
(
u,v
)
du
 
(1)
 K 
α
 
(
u,v
) =
Σ
k=0
ψ 
(v)
e
-
 j
α
 
ψ 
(u)
 (2)e
δ
(
u–v
)
δ
(
u+v
)where
 K 
α
(
u,v
)
=
if 
α
is not a multiple of 
π
 if 
α
is a multiple of 2
π
 if 
α
+
π
is a multiple of 2
π
 
2
π
1-cot
α
j
cot
α
– 
 j
 
u v
csc
α
 
u
2
+
v
2
 
2
 
 
 =
U E U
T
Where
U
is discrete Hermite-Gaussian matrix consists of discrete Hermite-Gaussian functions as in the fallowingequationand
‘E’
is a diagonal matrix which contains the eigenvalues e
-
 j
0
α
, e
-
 j
1
α
, e
-
 j
2
α
,..... e
-
 j
(
 N 
-2)
α
, e
-
 j
M
α
of DFrFT matrix
F
α
 
as diagonal elements.The response of an N-point DFrFT ‘f 
α
[n]’, for Ninput samples f[n] with rotation angle
α
can be calculated by f 
α
[n]=
F
α
f[n]. i.e.
α
 N×1
=
U
 N×N
*(
E
 N×N
*(
U
T
 N×N
*f 
 N×1
)).Here * indicates matrix multiplication operation. For the proposed architecture the matrix
E
is replaced with acolumn matrix
C
that contains the Eigen values of DFrFT for given input angle
α
and middle matrixmultiplication is replaced by an array multiplication. Themodified expression is f 
α
 N×1
=
U
 N×N
*(
C
 N×1
×(
U
T
 N×N
*f 
 N×1
)),Where‘×’ indicates the array multiplication operation.III.
 
P
ROPOSAL OF
DF
FT
 
A
RCHITECTURE
 The proposed architecture is composed of threelevels. The input data to be process is flow through allthe three serially connected levels as shown in Fig.1.The level-I performs two mathematical operations,one is calculation of eigen values for given input rotationangle and another is calculation of the response of matrix
U
T
for input samples f. these two operations are carriedout by two blocks of level-I named as C and U1. Thislevel passes two computed results that are matrix
C
and
U
T
*f to the level-II, which execute the multiplication of eigen values with the response of U1 block and feeds the product
C
×
U
T
*f to the level-III. In this level we get therotated input samples f 
α
 
=
U
*
C
×
U
T
*f as an output, by theact of matrix multiplication between level-III input andHermite-Gaussian matrix
U
.If input samples are complex values (f=a+
 j
 b), wehave to calculate the response of U1 block separately for  both real and imaginary parts, so that we need two U1 blocks. Similarly for any type of input samples f, two U2 blocks are required to process Level-III real andimaginary inputs separately. For this reason in Fig.1 the blocks U1 and U2 are denoted as multi-blocks. In Fig. 4the data flow between these blocks is given in detail. Thetime period between two successive input samples f andthe time period between two successive output results f 
α
 are same. The rest of this section presents the detaildescription of each level of proposed architecture.
 Level-I:
In an N-point DFrFT, this level-I is partitioned intotwo parts. The first part performs the calculation of eigenvalues for given rotation angle (
α
) using a block namedas C in the architecture as shown in Fig.2. This block receives an angle for every N clock cycles and itcomputes corresponding N complex conjugated eigenvalues. The results of block C for given angle
α
are e
 j
0
α
,e
 j
1
α
, e
 j
2
α
,….e
 j
(N-2)
α
, e
 j
M
α
, where
M=N-1, for N odd andM=N, for N even.
The architecture for calculation of eigen valuesrequires two clocks, i.e. clock1 (Clk) having thefrequency same as sampling frequency and another clock2 (Clkn) having 1/N
th
of frequency of clock1. Withactive high enable signal, the counter counts in sequence…0, 1, 2,…N-2, M, 0, 1, 2... . This counter output isconnected to a multiplier which took rotation angle asanother input through a register ‘
R1’
that receives clock2.The results of multiplier 0,
α
, 2
α
… (N-2)
α
, M
α
; M=N-1for N odd, M=N for N even are fed to the pipelinedCORDIC (
CO-
ordinate
otation
DI
gital
C
omputer) byanother register ‘
R2’
.The CORDIC [15] calculates the cosine and sinevalues of its input angles, which are real and imaginary parts of complex conjugated eigen values for givenrotation angle. The real and imaginary parts of computedresults pass to the output real part port and outputimaginary part port respectively through a set of registersas shown in fig.2. The requirement of these registers has been presented at the end of 
 Level-I 
explanation.The block ‘U1’ of second part of level-I multipliesinput values f with the matrix
U
T
. This part consist of amod-N counter, ‘N’ number of ROMs with N addresslocations per each ROM, N Multipliers, N accumulators,one N to1 Multiplexer and set of buffers. The data flowin this part is shown in Fig.3. As in block ‘C’ this‘U1’block also operates with two clocks named clock1(clk) and clock2 (clkn). The N rows of the matrix
U
T
 
arestored in N ROMs. The arrangement of rows of matrix
U
T
in ROM is shown in Table-I.(4)
 
 
 N 
, for 
 N 
odd
 
 
 N 
-1, for 
 N 
even
F
α
=u
[n]
 
e
-j
α
u
T
[n]
Σ
 
 N k=0
 
(5)
U=
u
0
[1] u
1
[1] . . u
 N 
-2
[1] u
M
[1]u
0
[2] u
1
[2] . . u
 N 
-2
[2] u
M
[2]. . . .. . . .. . . .u
0
[
 N 
] u
1
[
 N 
] . . u
 N 
-2
[
 N 
] u
M
[
 N 
]
hereM=
 N 
-1; for 
 N 
odd
 
M=
 N 
; for 
 N 
even
 
Fig.1: Block diagram of the DFrFTLevel-IILevel-ILevel-IIIRotated input ‘f 
α
 
E
Input ‘f ’Rotation angle (
α
)
CU1U2
Counter
Counts (0 – N-1); If N OddCounts (0 – N-2, N); If N Even
Rotationangle (
α
)
C.ER1
Clkn
 
Clk 
Clk
Fig. 2: Calculation of Eigen values.Output(Real Part)Output(Imaginary Part)Enable
C
*
R2
ImaginaryPartReal PartClk
Pipelined CORDIC
(Calculates Sin & Cos Values)
 
R31R41RN1ClkClkClkR32R42RN2ClkClkClkClkn
 
Clk

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