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The window detector output is formed by the OR-function of combining both Q outputs of comparators B and C. Outputs which have an ECL (Emitter Coupled Logic) structure can be wired together to form an OR function. The overall truth table is shown in Table 2: TABLE 2. Truth Table VIN High In Window Low Con1 0 1 1 Con3 1 0 1 Con4 1 1 0
Basic Operation
REFERENCE LEVELS The circuit is built around the four comparators of one LMH7324. Two reference levels are created using four resisters and two capacitors (R3, R6, R7, R9 and C9, C12 see Figure 7) The ref high level is a positive voltage referred to the ground level and the ref low level is a negative voltage referred to ground. The input connector (con2) is also referenced to ground which means that any AC signal at the input will vary around the ground level, which is in the center of the reference levels. COMPARATORS The comparators B and C form the window detector, while the comparator A is a level detector indicating that the input voltage exceeds the ref high voltage in the positive direction. The comparator D is a level detector indicating that the input signal exceeds the ref low voltage in the negative direction. The outputs are connected to a 50 connector via a 50 track. All three outputs are active low as can be seen in Table 1. TABLE 1. Four Comparators Output VIN High In Window Low QA 0 1 1 QB 1 0 0 QC 0 0 1 QD 1 1 0
OUTPUTS Every output has a Q and Q connection and both outputs have been made active by a resistor connected to the VEE terminal. An ECL output becomes active when current flows out of the emitters of the output stage. This can be done by connecting a resistor to a termination voltage (VT) which is 2V below the VCCO. When using the VT solution every output resistor has to be 50 (R1, R2, R4, R5, R10, R11, R12). Another possibility is to connect a resistor to the most negative supply voltage. In case of a connection to VEE, the resistor must have a value which causes a current that complies with the Normal Operating conditions as mentioned in the datasheet. This demo board is designed for a supply voltage of 5V for the VCCO with a resistor to VEE with a value of 240 (R4 = 360 while R1, R2, R5, R10, R11, R12 = 240). In case the VCCO is raised to 12V all output resistors to VEE should be replaced with 500 resistors except R4 which should be 750. All three output signals are connected via a 50 track and a combined capacitor and jumper which are connected in parallel. A customer can now make a choice between a DC or an AC coupled output signal. In the case of a DC coupled output be aware of the offset voltage which causes an extra DC current into a connected scope or analyzer with 50 input impedance. SUPPLY VOLTAGES This demo board can operate with a simple dual supply of 2.5V. The output voltages are now about 1.35V and 1.0V and comply with LVDS and RSPECL levels. In the case of a single supply voltage of +5V the output levels are 3.85V and 3.5V, which is only RSPECL level compliant. In a single supply configuration be aware that the detection window starts at VEE level, which is actually the ground level. The LMH7324 is ground sensing but in this configuration the input signals cannot extend more than 200 mV below the ground level. Every comparator has a separate connection for the VCCI, VCCO and the VEE. The supply pins are decoupled with a small capacitance of 10 nF to the ground plane. Since the outputs are referenced to the VCCO the output resistors are decoupled to this supply pin. For better low frequency decoupling a 47 F capacitor is placed at the supply connector (con5). The supplies VCCI and VCCO can be shortened by a jumper (J1) in case both positive supply voltages are the same value.
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Layout Considerations
The layout is done with a four layer board which makes it easy to keep the design compact with small 50 tracks. The advantage of this is that such tracks route easily and connect perfectly to small components. At the same time the length and number of supply lines are reduced, while decoupling to these supplies is easy and direct. Signals are routed on the top and bottom layer, making it easy to measure them.
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Higher frequencies will make the pulses much shorter, especially when a sine wave is used and the signal rises far above the window levels. This situation would make the time that the signal crosses the window levels very short, because a sine wave has the highest dV/dt at the transition points. Figures 5, 4 and Figure 6 show the measurements taken when a sine wave is used. In Figure 4 a sine wave of 10 MHz is used and it just crosses both levels of the window. This creates a reasonable pulse width for both the detection signals above window and below window and for the detection signal in window. The added hysteresis works since no oscillations can be seen although the input signal crosses the levels very slowly and with low overdrive. When using a signal with the same frequency but with a much greater amplitude, the time it takes for the signal to cross the window becomes much shorter as can be seen in Figure 5. Note that the frequency of the detection signal in window doubles compared to the input frequency. Also the crossing time through the window levels is very short and, for this example, it is equal to one period of a frequency of 227 MHz (see marker indication in plot). This means that the detection signal in window is the most critical of the three detection signals and will be the first to incur problems due to frequency limits. The setup of Figure 6 uses an input frequency of 100 MHz with a big overdrive at the window levels. This results in a very small pulse for the detection signal in window which is equal to one period of a 1.05 GHz signal (see markers indication in plot). All signals are measured using a cable with a length of 1 meter connected to a four channel oscilloscope. All channels are AC coupled and terminated with 50.
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Board Schematic
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Board Layout
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Notes
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Notes
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