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  • Boundary-Scan DFT Strategy For Multi-Chip Module Targeted Designs

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    Shiva Kumar
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    This document is an abstract for a Master's thesis on developing a boundary-scan design for test (DFT) strategy for multi-chip modules. The strategy aims to make multi-chip modules compliant with the IEEE 1149.1 JTAG standard through a methodology for generating a single boundary-scan description language file. The methodology is presented and applied to a two-core and four-core multi-chip module and issues are examined and addressed. Finally, a generic boundary-scan insertion methodology is developed to make multi-chip modules boundary-scan compatible devices regardless of the number of cores.

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    This document is an abstract for a Master's thesis on developing a boundary-scan design for test (DFT) strategy for multi-chip modules. The strategy aims to make multi-chip modules compliant with the IEEE 1149.1 JTAG standard through a methodology for generating a single boundary-scan description language file. The methodology is presented and applied to a two-core and four-core multi-chip module and issues are examined and addressed. Finally, a generic boundary-scan insertion methodology is developed to make multi-chip modules boundary-scan compatible devices regardless of the number of cores.

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    Attribution Non-Commercial (BY-NC)
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    20 views1 page

    Boundary-Scan DFT Strategy For Multi-Chip Module Targeted Designs

    Uploaded by

    Shiva Kumar
    This document is an abstract for a Master's thesis on developing a boundary-scan design for test (DFT) strategy for multi-chip modules. The strategy aims to make multi-chip modules compliant with the IEEE 1149.1 JTAG standard through a methodology for generating a single boundary-scan description language file. The methodology is presented and applied to a two-core and four-core multi-chip module and issues are examined and addressed. Finally, a generic boundary-scan insertion methodology is developed to make multi-chip modules boundary-scan compatible devices regardless of the number of cores.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as DOCX, PDF, TXT or read online from Scribd
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    Boundary-Scan DFT Strategy for Multi-Chip Module Targeted Designs by Shiva Kumar K

    in partial fulfillment of the requirements for the degree of Master of Technology in VLSI and Embedded systems Design

    Abstract
    With the limited accessibility in the Multi Chip Module (MCM) based design circuitry, Boundary-Scan plays a key role in testing of Interconnects and I/Os of MCM at Printed Circuit Board (PCB) level. With advances in MCM technology, more and more JTAG compatible cores with Boundary-Scan Description Language (BSDL) file describing its Boundary-Scan test logic are being integrated in MCM.This poses challenge in making the MCM as a single IEEE 1149.1 JTAG standard compliant device with single BSDL file. This necessitates in developing a generic Boundary-Scan insertion methodology for MCM based designs making it a Boundary-Scan compatible device. In this thesis, a Boundary-Scan insertion methodology is presented for two cores MCM which includes generating BSDL file with less manual intervention. The methodology is then extended to four cores MCM and verified for Boundary-Scan compliancy. Several issues encountered were examined and solution to overcome the issues with the proposed methodology was developed. Finally a Generic Boundary-scan insertion methodology is developed for MCM based designs making it a Boundary-Scan compatible device with a single BSDL file. This methodology can be implemented for any number of cores in the MCM environment.

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