Efficient On-Chip Crosstalk Avoidance CODEC Design

Project Guide: Ms. G. Vijaya Lakshmi. Team members: Ch.Balaji (09D91A0423),

Komal Shiradkar (09D91A0456).

Batch no: B5.

ABSTRACT
This work presents guidelines for the CODEC design of the forbidden pattern free crosstalk avoidance code (FPF-CAC). We analyze the properties of the FPF-CAC and show that mathematically, a mapping scheme exists based on the representation of numbers in the Fibonacci numeral system. Interconnect delay has become a limiting factor for circuit performance in deep sub-micrometer designs. As the crosstalk in an onchip bus is highly dependent on the data patterns transmitted on the bus, different crosstalk avoidance coding schemes have been proposed to boost the bus speed and/or reduce the overall energy consumption. Despite the availability of the codes, no systematic mapping of data words to code words has been proposed for CODEC design. The lack of practical CODEC construction schemes has hampered the use of such codes in practical designs. Our first proposed CODEC design offers a near-optimal area overhead performance. An improved version of the CODEC is then presented, which achieves theoretical optimal performance. We also investigate the implementation details of the CODECs, including design complexity and the speed. Optimization schemes are provided to reduce the size of the CODEC and improve its speed. The proposed CODEC design is highly efficient, modular and can be easily combined with a bus partitioning technique. A high speed design can be achieved through pipelining.