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Some of the advantages of CPLDs are Ease of design: CPLD offers the simplest way to implement a design. Once a design has been described by schematic and/or HDL entry, one have to simply use CPLD development tools to optimize, fit, and simulate the design. This provides an instant hardware. Lower development costs: Their development cost is very low, as they can be reprogrammed. Furthermore, one can easily and very inexpensively changes its design. This allows optimizing designs and continuous addition of new features to enhance the products. Product revenue: CPLDs offer more product revenue because the development cycles are very short. The product get into the market quicker and begin generating revenue sooner. Since, these are reprogrammable, any modification and new features can be introduced very quickly. Reduced board area: A high level of integration, that is large number of system gates per unit area, and availability in a very small form factor packages is possible with CPLD. This provides the perfect fitting to the product into a limited amount of circuit board. Ownership cost: Since CPLDs are reprogrammable, requiring no hardware rework, it costs much less to make changes to designs implemented using them. Therefore, cost of ownership, defined to maintain, fix, or warranty a product, is dramatically reduced.

10.3 Field Programmable Gate Arrays

These were introduced in 1985 by world known company Xilinx. Since then many different FPGAs have been developed by a number of companies. Some of them are Actel, Altera, Plessey, Algotronix, Quick logic, AMD, Plus, Crosspoint solution, Concurrent logic among others. Similar to MPGAs, FPGAs consist of an array of uncommitted elements that can be interconnected in a general way. The interconnection between the elements is user programmable.

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Figure 10.10

Block level FPGA representation

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Figure 10.11

Basic FPGA configuration

Block level FPGA representation, shown in the Fig. 10.10, consists of a two-dimensional array of logic blocks that can be connected by any resource of interconnection. These logic blocks are connected through wire segments of different lengths as shown in Fig. 10.11. These interconnects are programmable switches which connect wire segment to the logic blocks. Logic circuits are partitioned for the implementation in logic blocks of any FPGAs and then logic blocks are interconnected via switches. It is therefore required that the FPGAs should be capable enough of implementing digital design of various size, also called as density of the circuit. There can be trade-off between complexity and flexibility of both the logic blocks and the interconnection resource to design an FPGA.

10.3.1 Applications of FPGAs

FPGAs have a wide area of applications and can replace MASK programmable Gate Arrays, PLDs, and small-scale integration logic chips. Few of the applications of FPGAs are as follows: Prototyping: FPGAs are almost ideally suited for different prototyping applications. It is low in cost and requires a short time for the physical realization of any digital design and gives tremendous advantages over conventional method of hardware realization. These prototypes can be changed in less time and inexpensively. ASIC design: FPGAs are the wonderful medium for implementing digital logic and particularly suited for application specific integrated circuits (ASIC) design. Random logic implementation: Programmable array logic (PLA) is generally used for the implementation of random logics. But FPGAs are suitable alternative for the random logic realization, if the speed is not a constraint. PLA are usually faster than FPGAs because PLAs can be implemented with lesser number of gates. In an FGPA we can implement as many as 20 or more PLAs. This number is growing day by day and we may be able to achieve higher speed with FPGAs.

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Implementation of SSI chips: FPGAs can realize large combinational and sequential digital circuits. These can vastly be used as a replacement for the SSI chips whose density is very small and acquire large area on PCB. On-site re-reconfiguration: Since the interconnections of different logic gates and logic blocks present in FPGAs can be redone as required time to time without much cost and less time, FPGAs can be reconfigured on the site of applications. Thus, by doing the reprogramming of interconnections we can change the functionality of the system where it is applied.

10.3.2 FPGA-Based Design Flow

FPGA-based design is basically CAD system design and therefore an efficient computer aid is essential for good use of FPGAs.

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Figure 10.12

Design flow of FPGA

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The starting point of the design process is the initial logic entry of the circuit that has to be implemented as shown in Fig. 10.12. This typically involves the drawing of a schematic using a schematic capture tool, entering an HDL description, specifying Boolean expression, or state machine entry. All the methods are finally expressed in standard form of Boolean functions. The Boolean functions are then processed by logic optimization tool which manipulates the expressions to obtain a logic circuit which is optimized in area or speed. Next the Boolean expressions are transformed into a circuit of FPGA logic blocks. This is called as technology mapping. This mapping phase transforms the optimized logic network into a circuit that consists of restricted set of circuit elements. These circuit elements can be logic blocks or other hardware such as multiplexers or look-up tables (LUT), also known as programming technology, available in that FPGA. Technology mapping is done with software available for synthesis. Mapper can also optimize the total number of logical blocks or MUXs or LUT required, which is known as area optimization. Alternatively, the objective may be to minimize the number of logic block stages in critical paths, which is called delay optimization. After mapping the circuit into the logic blocks, placement is to be done, that is location is decided for each logic block to be placed in the FPGA. This is performed by a software program That employs placement algorithms specially developed to derive placement having minimum length of interconnect required between each logic blocks. The input is a structural description of a logic circuit that may be in the form of submodules and their interconnection patterns. The last step in the flowchart of Fig. 10.12 is to perform the routing of logic blocks. This is accomplished by routing software. Routing software assigns wire segments and chooses programmable switches to establish the required interconnections among the logic blocks and confirms that all the connections are done. It also estimates for those routing channel which have minimum propagation delay and reduced critical time connections. This software uses different routing algorithms for different FPGA architecture. After successful compilation of all the above steps, the output is fed to a programming unit which finally configure FPGA chip.

10.3.3 FPGA Architecture

In the past few years, many companies have introduced different FPGAs. These FPGAs differ in architecture and features depending on their applications. The classification of FPGA architecture can be done on the basis of different companies which have introduced them. Different manufacturers have different technology for logic implementation. The structure of an FPGA consists of several logic blocks and interconnected resources as shown in Fig. 10.13. There are numerous ways of defining a logic block because it vary from a simple AND gate to a much complex structure consisting of multiplexes or look-up tables, some may have a PLA kind of structure. This also varies from manufacturer to manufacturer and different applications. To implement sequential circuits, it also consists of flip-flops. In an FPGA, the structure and content of interconnects are also called its routing architecture. A routing architecture consists of both wire segments and programmable switches. Routing of FPGAs is itself a very wide area and is beyond the scope of present text.

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