CHAPTER 6

HARDWARE IMPLEMENTATION

6.1 FPGA
The software code is equipped with a field-programmable gate array (FPGA). FPGA
is an integrated circuit which can be designed and deployed after configuring it to the
requirements of the developers. After manufacturing the field programmable gate array, the
IC is deployed in the real time applications with great ease. The configuration is declared
using hardware description language (HDL) which is specific to ICs, and configurations for
the applications are performed using an application-specific integrated circuit (ASIC). Huge
number logic gates and RAM blocks are used to build the Contemporary circuits with FPGAs
to enable them to perform complex digital computations. FPGA designed architectures are
built withswift IOs and bidirectional data buses, the system is expected to verify correct
timing of data and time validityalong with setup time and hold time. FPGA is backed up with
floor planning activities which enables resources allocation to adhere to these time
constraints. FPGAs can be deployed as an alternative used to apply any logical function
which can be implemented with ASIC.The benefits of FPGA range with an ability to
reconfigure the functionality after deployment, minimal re-configuration of a particular
segment of the design andcheaper non-recurring engineering costs associated with an ASIC
design, and much more with respect to design and implementations.
FPGA is fundamentally built with programmable logic components known as “logic
blocks”. These blocks constitute a hierarchy of reconfigurable interconnects to compose
different logic blocks to be “wired together”. Many designs are changed with adding or
removing changeable logic gatesin different configurations with simplicity. Logic blocks
from simple AND, OR, XOR gates performing simple mathematical operations to complex
combinational functions. In most FPGAs, memory blocks made with flip flops or even higher
configurations are merged together to increase the functionality.
FPGAs are enabled with the combined functionalities of analog features and digital
functions together with some designated variants. Programmable slew rate and drive strength
are available on every output pin, which permits the developers to define slow rates on lightly
loaded pins to preserve overloads causing the unaccepted rings. The extended design of
FPGAs can be implemented toset stronger, quicker rates when pins are heavily allocated over
high-speed channels, these channels will be comparatively slower in usual cases if they
would not have been defined accordingly. A relatively general features with analog attributes
arethe differential comparators implemented on input pins. These pins are usually designed to
connect with multiple differential signaling channels.Digital signal processing, digital image
processing, prototyping, software-defined ratio, ASIC prototyping, medical image analytics,
computer vision, speech recognition, cryptography, biomedical and bioinformatics, computer
hardware emulation, radio astronomy, metal detection are some of the applications of FPGA
and they are extensively researched in many other domains.
6.1.1 FPGA ARCHITECTURE

An FPGA is composed of multiple logic gates which can be programmed according to

the requirements of users, with interconnecting abilities with other resources, to build
complex digital circuits.When dedicated multipliers are merged into FPGA architectures
during the 90s decade, applications mandating digital signal processing applications are
upgraded with FPGAs instead.FPGAs are proven to implement parallelism when an
algorithm or application has to perform in a particular domain.Xilinx, Altera, Actel, Lattice,
Quick Logic and Atmel are renowned manufacturers of FPGA devices which produce
semiconductors.
 Figure 6.1 - FPGA Prototype

The core and programmable functional elements of FPGA architecture are described as
follows:

 Configurable Logic Blocks (CLBs) are known as look up tables which functions like
Random Access Memories to store and order the instructions for executions. Flip flops or
latches constitute the CLB components. CLBs are capable of executing a diverse range of
logical functions beyond storing and retrieving data.Based on the functionality of FPGAs,
they can be grouped into either category being fine grained or coarse grained.Fine grained FPGAs
are built with transistors, includes a couple of logic gates,3-input LUT. On the other hand, more
complex units define the functional elements of a coarse grained FPGA such as a 4-input LUT to
implement better operations compared to that of a fine grained FPGA.

 Input/ Output Blocks (IOBs) are responsible for controlling the input and output pins
and thus regulate the flow of data between these pins. The internal logic of the devices is
also monitored with IOBs. Bidirectional data flow along with threestately operations are
facilitated by IOB supports. Such supports are used to monitor the operations of various
signal standards, subjecting four high-performance standards, Double Data-Rate (DDR)
registers.

 Block RAMutilizes 18-Kbit dual- port blocks for facilitating data storage.

 Interconnect defines the interface of a hub of between the inputs and outputs, with other
functional elements alongside the FPGA, such as IOBs, CLBs, DCMs, and block RAM.
Interconnect can also function as routing, and segmentation is performed for optimal
connectivity between different components of FPGA.

The most common FPGA architecture consists of an array of logic blocks(called

Configurable Logic Block, CLB, or Logic Array Block, LAB, depending on vendor), I/O
pads, and routing channels. Generally, all the routing channels have the same width (number
of wires). Multiple I/O pads may fit into the height of one row or the width of one column in
the array.An application circuit must be mapped into an FPGA with adequate resources.
While the number of CLBs/LABs and I/Os required is easily determined from the design, the
number of routing tracks needed may vary considerably even among designs with the same
amount of logic. Since unused routing tracks increase the cost (and decrease the performance)
of the part without providing any benefit, FPGA manufacturers try to provide just enough
tracks so that most designs that will fit in terms of Lookup tables (LUTs) and IOs can be
routed. Since clock signals are generally moved through some special-purpose networking
tools with dedicated routing protocols. Commercial versions of FPGAs will manage the
networking signals separately and other signals are separately managed.The latest
FPGAsbuilt with SRAM are found to consist of highest densities, yet deficient in terms of
power consumptions and memory requirements. SRAM-based FPGAs are available with in-
built flash modules where the external blocks of memory are not necessary to be added.
SRAM-based FPGAs are found to consume more energy compared to Flash-based and
Antifuse-based FPGAs designs. Antifuse-modeled FPGAs have another drawback that it can
be configured with a program only once and cannot be reconfigured.

6.2FPGA EMBEDDED PROCESSORS

Embedded systems are a combination of both hardware and software components
built together for solving a specific problem with an application. There are various design
considerations during the design and implementation of embedded systems such as area
usage, size, power consumption and performance. With all these considerations, the design
cannot be simply derived to form a solution. There is a notable delay, cost considerations,
tight time to market issues when embedded systems are developed into applications.
Embedded systems when emphasizing on the hardware based implementation, they
are found to promise better performance, accuracy and cost management. The size of
memory blocks can be optimized with hardware based specialization. These designs are
implemented over a general purpose application. Designers will be finding it difficult to put
the hardware and software components together when complexity of embedded systems
designs is increased considerably over time. Designing the system with multiple components
from very basics can be difficult at times, impractical and costly for developers in most cases.
Having said this, the systems can incorporate existing modules which are pre-designed
intellectual property (IP) cores to simplify the process of building an application.
A processor has to be built into the FPGA to deliver better outcomes and has many
advantages than ordinary built up. Depending on the functionality of the application, required
peripherals can be opted from a list of peripherals, selections are immediately attached to the
system design. The applications can demand a list of controllers to be opted again by the
developers and hence the same can be attached to the system with FPGA embedded processor
system’s interface capabilities. General purpose applications are built with FPGA logic to
build the components with suitable internal memory blocks, processor communication
busses, internal and external peripherals, their respective controllers (including external
memory controllers).Large banks of external memory are used for enriched computational
capacity to the processors along with suitable memory controllers. When FPGA is backed up
with large memory blocks, the embeddedprocessor system is equipped with advanced
functionalities and powerful systems.
Processors embedded with FPGA components are hence categorized into hard-core
and soft-core processors based on their functionalities.A hard-core processor is equipped with
a dedicated silicon chip in its integrations. On the contrary, a soft-core processor uses existing
configurable logic elements from the FPGA to implement the processor. Only specific high
performances FPGAs integrate a hard-core; however, a soft-core processor can be
implemented in any FPGA as long as there are enough configurable logic resources available.
Although a hard processor can offer better performance than an equivalent soft processor,
they are inflexible and cannot be tailored to suit the needs of different applications.
Furthermore, their fixed position in the fabric can complicate floorplanning, and a large
amount of supporting infrastructure is required in logic. Meanwhile soft processors have been
widely adopted in many applications due to their relative simplicity, customizability, and
good tool-chain support. Soft processors can be tailored to the specific needs of an
application, and since they are implemented entirely in the logic fabric, additional features
can be easily added or removed at design time.
Commercial soft processors include the Xilinx MicroBlaze, Altera Nios II, ARM
Cortex-M1 and LatticeMico32 in addition to the open-source Leon3.
An FPGA embedded processor system offers many exceptional advantages compared
to an off-the-shelf processor including
 Customization: FPGA embedded processor system offers complete flexibility to
select any combination of peripherals and controllers. In fact, new unique peripherals can be
design and connected directly to the processor’s bus with the assumption that there are no
standard requirements for the peripherals.
 Hardware acceleration: The most compelling reason to choose FPGA embedded
processor is the ability to make tradeoffs between hardware and software to maximize
efficiency and performance. If an algorithm is identified as a software bottleneck, a custom
co-processing engine can be designed in the FPGA specifically for that algorithm. This co-
processor can be attached to the FPGA embedded processor through special, low-latency
channels, and custom instructions can be defined to exercise the co-processor.
  Obsolescence mitigation: Obsolescence mitigation is a difficult issue when a design
requirement must ensure that a product lifespan be much longer than the typical lifespan of a
standard electronics product. In this case, FPGA embedded soft-processors could be an
excellent solution since the HDL source code for the soft-processor can be purchased and
owned thereby guaranteeing the lifespan of the product.
 Component and cost reduction: With the versatility of the FPGA embedded processor,
a previous system that required multiple components can be replaced with a single FPGA
such as in the case when an auxiliary input/output chip or a co-processor is required next to
an off-the-shelf processor. By reducing the components count in the design, a company can
reduce board size and inventory management, both of which can save design time-to-market
and cost.

6.3 MICROBLAZE
The microprocessors available for use in Xilinx Field Programmable Gate Arrays
(FPGAs) with Xilinx EDK software tools can be broken down into two broad categories.
There are soft-core microprocessors (MicroBlaze) and the hard-core embedded
microprocessor (PowerPC).Soft-core MicroBlaze microprocessor, is present in most of the
Spartan-II, Spartan-3 and Virtex FPGA families. The hard-core embedded microprocessor
mentioned is an IBM PowerPC 405 processor, which is only available in the Virtex-II Pro
and Virtex-4 FX FPGA’s.The MicroBlaze is a virtual microprocessor that is built by
combining blocks of code called cores inside a Xilinx Field Programmable Gate Array
(FPGA). The user can also tailor the project according to his or her specific needs (for
example Flash, UART, General Purpose Input/Output peripherals and etc.).Soft core
processors are more flexible than hard core processors.Because MicroBlaze is a soft-core
microprocessor, any optional features not used will not be implemented and will not take up
any of the FPGAs resources.
MicroBlaze processor present in the FPGA is as depicted:
 Figure 6.2- Microblaze Based Embedded Processor in a FPGA

The MicroBlaze processor is a 32-bit Harvard Reduced Instruction Set Computer

(RISC) architecture optimized for implementation in Xilinx FPGAs with separate 32-bit
instruction and data buses running at full speed to execute programs and access data from
both on-chip and external memory at the same time. The backbone of the architecture is a
single-issue, 3-stage pipeline with 32 general-purpose registers,an Arithmetic Logic Unit
(ALU), a shift unit, and two levels of interrupt.The MicroBlaze pipeline is a parallel pipeline,
divided into three stages: Fetch, Decode, and Execute. In general, each stage takes one clock
cycle to complete. Consequently, it takes three clock cycles (ignoring delays or stalls) for the
instruction to complete. Each stage is active on each clock cycle so three instructions can be
executed simultaneously, one at each of the three pipeline stages. MicroBlaze implements an
instruction prefetch buffer that reduces the impact of multi-cycle instruction memory latency.
While the pipeline is stalled by a multi-cycle instruction in the execution stage the instruction
prefetch buffer continues to load sequential instructions. Once the pipeline resumes execution
the fetch stage can load new instructions directly from the instruction prefetch buffer rather
than having to wait for the instruction memory access to complete. The instruction prefetch
buffer is part of the backbone of the MicroBlaze architecture and is not the same thing as the
optional instruction cache.
The core block diagram of MicroBlaze processor is as shown:
 Figure 6.3- MicroBlaze Core Block Diagram

MicroBlaze is a load/store type of processor meaning that it can only load/store data
from/to memory. It cannot do any operations on data in memory directly; instead the data in
memory must be brought inside the MicroBlaze processor and placed into the general-
purpose registers to do any operations. Both instruction and data interfaces of MicroBlaze are
32 bit wide and uses big-endian, bit-reversed format to represent data.
In general, while making use of a FPGA embedded processor the following two
memories should be taken into consideration:
 Local Memory
The local memory provides the fastest option in accessing memory. Xilinx FPGA
local memory is made up of large FPGA memory blocks called BlockRAM (BRAM). The
Block RAM (BRAM) is a configurable memory module that attaches to a variety of BRAM
Interface Controllers.The Block RAM controllers for MicroBlaze include
–PLB block RAM controller (xps_bram_if_cntlr)
–OPB block RAM controller (opb_bram_if_cntlr)
–LMB block RAM controller (lmb_bram_if_cntlr)
The BRAM Block structural HDL is generated by the Embedded Development Kit
(EDK) design tools based on the configuration of the BRAM interface controller IP. All
BRAM Block parameters are automatically calculated and assigned by the EDK tools Platgen
and Simgen.
 Embedded processor accesses BRAM in a single bus cycle.Since the processor and
the bus run at the same frequency in MicroBlaze, instructions stored in BRAM are executed
at the full MicroBlaze processor frequency.
 External Memory
Xilinx FPGAs provides several memory controllers that interface with a variety of
external memory devices. These memory controllers are connected to the processor’s
peripheral bus. The three types of volatile memory are supported by Xilinx FPGAs are static
RAM (SRAM), single-data-rate RAM (SDRAM), and the double-data-rate RAM (DDR)
SRAM. The SRAM controller is the smallest and simplest inside the FPGA while the
SDRAM is the most expensive of the three memory types. The DDR SDRAM controller is
the largest and most expensive inside the FPGA, but requires fewer FPGA input-output (I/O)
ports and is least expensive per megabyte.
The Microblaze processor has up to three interfaces for memory accesses:
 Local Memory Bus (LMB)
 IBM’s Processor Local Bus (PLB) or On-chip Peripheral Bus (OPB)
 Xilinx CacheLink (XCL)
The MicroBlaze processor has a 32-bit LMB that provides single-cycle access to on-
chip dual-port block RAM (BRAM) and is split into instruction-side LMB and data-side
LMB. The OPB interface provides a connection to both on-chip and off-chip peripherals and
memory.The MicroBlaze processor includes a tightly coupled, off-chip Flash/SRAM/DDR2
memory controller interface. The CacheLink interface is intended for use with specialized
external memory controllers.The LMB memory address range must not overlap with PLB,
OPB or XCL ranges.
MicroBlaze is a system which is established with 8 Fast Simplex Link (FSL) ports,
FSL interface are categorized into master and slave ports. The FSL is proven to be minimal
but powerful interface with point-to-point accessibility. The interface is connected with user
components, hardware accelerators co-processors to the MicroBlaze and hence the processes
are pipelined to limit the time taken for processing algorithms. Certain algorithms cannot be
consuming higher time and hence optimized with MicroBlaze systems.
The MicroBlaze implements a stack based convention to operate from a
greatermemory location and reduced downward to lower memory locations. The items are
stored one over the other as the storage mechanism is implemented with stacksand a
function call. The elements are pushed on top of stack and items are popped off the stack
from the top. The elements are accessed on the reverse order, the order in which they were
added. The MicroBlaze processor is constituted with a number of special purpose registers
namely Program Counter (PC) to store the list of instructions in the order of executions, the
order cannot bewritten but only read. The next register is the Machine Status Register (MSR)
which holds the status of processor represented by the operations like indicating arithmetic
carry, divide by zero error, a Fast Simplex Link (FSL) error and enabling/disabling interrupts
to name a few. The purpose ofan Exception Address Register (EAR) is to store the complete
addresses that resulted in an exception. An indication of the type of exception occurred is
also noted in the register. The next register is to identify the invalid operations such
asinvalid operation, divide by zero error, overflow, underflow and
denormalized operand errorand named to be Floating Point Status Register (FSR).

EDK Interface

Writing a software code to control the MicroBlaze processor accepts only the C/C++
programming language. Since the possible method is implementing C/C++ programs, it is
also known to be a standard language for programming with hardware. Known to be a
preferred method by most people, the format that the Xilinx Embedded Development Kit
(EDK) software tools expects as the default programming language. Necessary compilers of
C/C++ are in built within the EDK tools to translate the given code into necessary machine
code to be understood by the MicroBlaze processor.The MicroBlaze processor is simply a
processor which can work only with supporting peripherals and EDKs. Without the
supporting toolkits, the functions are almost zero. The On-chip Peripheral Bus (OPB) and/or
Processor Local Bus (PLB) are the supporting toolkits which are used to connect with
processor system developed by EDK. This defines the necessity of the custom peripherals
and its needs to be either of OPB or PLB compliance. The system denotes that the top-
level module must contain a set of bus ports adhering to the variants of OPB or PLB protocol
in order to accustom to newly defined peripherals. The system can ensure that they can
beapplied with systematic approach using the OPB or PLB bus.

6.4 SPARTAN- 3E FPGA

The Spartan-3E is known to be a group of Field-Programmable Gate Arrays (FPGAs).
All these FPGAs are intended to accommodate the applications demanding high volume of
data, cost-effective solutions in form of consumer electronic applications. There are nearly
100,000 to 1.6 million system gates in the five-member family of SPARTEN series. The
Spartan-3E family has a successive family followed by the successful solutions built with its
predecessors Spartan-3 family. The latest family is built with abundant amount of logic to
every I/O, in order to limit the cost incurred per logic cell.Sparatan-3E is seventh member in
the family low-cost and efficient Spartan Series and the third member of Xilinx family. This
family of systems are manufactured with advanced 90nm process technology. New features
are integrated into the improved and thus the overall system performance is increased. The
same configuration has reduced the cost of configuration. The Spartan-3E are enhancements
which promise better functionality than the previous versions, defining advanced and new
standards in the programmable logic gates industry. The Spartan-3E FPGAs are of low costs,
which can be implemented in a futuristic domain of consumer electronics applications, with
numerousapplications such as broadband devices, automation and home networking,
secondary display/projection devices, and digital television mother boards. The family of
Spartan-3E devices have proven to be asignificant alternative to cover the applications which
are programmed in ASICs. FPGAs tend to control the highly incurred initial cost, the time
consumed for building huge applications, lengthy development cycles, and level of flexibility
provided over traditional ASICs designs. Also, upgrades in the FPGA programmability
design defines a system with limited or no hardware replacements.
 Figure 6.4 - Spartan 3E FPGA

The key features of the Spartan-3E Starter Kit board are:

 Xilinx XC3S500E Spartan-3E FPGA
♦ Up to 232 user-I/O pins
♦ 320-pin FBGA package
♦ Over 10,000 logic cells
 Xilinx 4 Mbit Platform Flash configuration PROM
 Xilinx 64-macrocell XC2C64A CoolRunner CPLD
 64 MByte (512 Mbit) of DDR SDRAM, x16 data interface, 100+ MHz
 16 MByte (128 Mbit) of parallel NOR Flash (Intel StrataFlash)
♦ FPGA configuration storage
♦ MicroBlaze code storage/shadowing
 16 Mbits of SPI serial Flash (STMicro)
♦ FPGA configuration storage
 ♦ MicroBlaze code shadowing
 2-line, 16-character LCD screen
 PS/2 mouse or keyboard port
 VGA display port
 10/100 Ethernet PHY (requires Ethernet MAC in FPGA)
 Two 9-pin RS-232 ports (DTE- and DCE-style)
 On-board USB-based FPGA/CPLD download/debug interface
 50 MHz clock oscillator
 Three Digilent 6-pin expansion connectors
 Four-output, SPI-based Digital-to-Analog Converter (DAC)
 Two-input, SPI-based Analog-to-Digital Converter (ADC) with programmable-gain
pre-amplifier
 ChipScop SoftTouch debugging port
 Rotary-encoder with push-button shaft
 Eight discrete LEDs
 Four slide switches

6.4.1 SERIAL PORT

The Spartan-3E Starter Kit board is equipped with a couple of RS-232 serial ports
namely a male DTE connector and a female DB9 DCE. DCE-style port has the capability of
connecting directly whenever a serial port connector is readily available. The serial ports are
commonly found on most personal computers and workstations. They can be connected
through atypical straight-through serial cable. The figure 6.5 illustrates the different
components and their connectivity between the FPGA and two DB9 connectors mentioned in
the architecture. The LVTTL and LVCMOS are the components which are used to connect
with FPGA serial output. The transferred information, in turn, is thus transformed into its
logic value appropriate to RS-232 voltage level. The Maxim device transforms the input
values in form of RS-232 data into LVTTL levels to be processed by the FPGA. A series
resistor is added between the Maxim output pin to conserve the FPGA’s RXD pin before any
accidental logic conflicts with the actual source codes.
 Figure 6.5- RS-232 Serial Ports

6.5 XILINX EMBEDDED DEVELOPMENT KIT

Xilinx is equipped with a wide range of tools for developing new systems, technically
known as the ISE DesignSuite. Xilinx offers the Embedded Edition of the ISEDesign Suite
for designing and implementing embedded systemswith the following components.
• Integrated Software Environment (ISE) toolkits
• PlanAhead™ software for design analysis
• ChipScope™ professional version
• Embedded Development Kit (EDK)
The Embedded Development Kit (EDK) is a collective framework with required tools
and Intellectual Property that an end userrequires for building and completing the design of
an embedded processor system. The whole system is implemented in a Xilinx FPGA device.
6.6IMPLEMENTATION FLOW

6.6.1 XILINX PLATFORM STUDIO

 Xilinx Platform Studio (XPS) is an interface with an integrated environment for
designing and implementing embedded processor systems, primarily with MicroBlaze and
PowerPC processors. XPS is also facilitated with an editor and an interface for project
management. The editor is used for editing and storing codes and interface with all necessary
toolkits to create and edit source code.XPS is a Graphical User Interface that assists the users
to specify the type of system, that is based out on
 type of processors,
 types of memory blocks and other FPGA IPs (peripherals) to use
 connectivity protocols through network IPs
 the memory map,
XPS is full of features to select from
 Project management in a single window
 Create a system block
 View a system block diagram and design report.
 Project management support.
 Process and tool flow dependency management.
 Figure 6.6 – XPS Project Window
The XPS defines the following areas within its main window

1. Project Information Area (1)

2. System Assembly View (2)
3. Console Window (3)

The XPS is assisted with multiple labels in the main window, identifying the following areas
as shown in the Figure 6.6
1. Connectivity Panel (4)
2. View Buttons (5)
3. Filters Pane (6)

6.6.1.1 The Base System Builder (BSB) Wizard

When a new XPS project is to be created, the Base System Builder is prepared and
invoked for facilitating the build operations. The Base System Builder (BSB) defines the
usage and implementation of prerequisite hardware and software components necessary for
configuration tasks which are generic to most processor designs. If the user intends to
utilizeone among the sustained embedded processor development boards available in the list
of machinesin Xilinx, the BSB furnishes the list of peripherals available on that board, for the
end users to opt and automatically match them with the FPGA pinout with the board. This
selection will in turn, create a completed platform. The completed and tested application will
soon be downloaded and executed on the board. If the user develops a new design with a
customized model over a custom board, the BSB still permits the user to select and
interconnect the new components with existing processor cores. The newly formed model
with a variety of compatible peripheral cores from the library can be derived and achieved
better outcomes based on the applications. The users are provided with a list of hardware
platforms as the commencing point of the solution to be built with processors and peripherals
and new components if needed, where the custom peripherals can also be implemented using
the tools provided in XPS.
BSB allows the users to configure their applications with options to select from the
following system attributes:
 Intended Processor type either MicroBlaze or PowerPC, based on the FPGA
device to be implemented
 Clock frequencies of reference and processor-bus
 Default buses
 List of Peripherals
 Cache blocks
 Type and size of Memory block
 Common peripherals
When embedded processor development boards is decided and development
commences, BSB lists the possible peripherals which can be connected with control off-chip
devices. These devices are furnished to accommodate the new features defined by the users
provided on the board. The peripherals which are not preferred by the users are removed from
the entire system to limit the functionalities and reduce the usage of FPGA.
The BSB is furnished with the following board-specific services:
 On-board FPGA selection
 Selection of clock
 Selection of on-board oscillators
  Reset polarity definitions
 Definition of FPGA pinout to adhere to the board connections, for the
preferred components

A functional default values are pre-defined in XPS for every valued option available
in the architecture. Microprocessor Hardware Specification (MHS) file is generated and
uploaded into the XPS project during the initializations.One or multiple software
contributions are generated by the BSB Wizard, every individual application denotes a
sample fully functional software with its equivalent script. All such coding scripts will be
compiled and executed on a hardware designated with a target development board.

6.6.1.2 Hardware Flow

The flow of communication between the hardware components is shown in figure 6.6
 Figure 6.6 – Hardware Flow []

6.6.1.2.1 Microprocessor Hardware Specification (MHS)

The MHS is a text file with edit rights to the users, which can be used as the principal
source file listing the various hardware components used in the embedded system. An MHS
also holds the configuration details of respectiveembedded processor system, and may
include the following details:

 Bus Layout
 List of Peripherals
 Processor Configurations
 Connectivity within the system
 The MHS file is usually an automatically generated text file with potential
information about the IO Port declarations, peripherals like memory blocks, Microblaze port
connections, bus organization and parameters, Local Memory Bus/On-chip Peripheral Bus
and Bus specifications.

6.6.1.2.2Microprocessor Peripheral Definition (MPD)

The template is a document specifying the list of ports, various parameters of

peripherals and other protocols. The available list of ports and predefined connectivity for bus
interfaces, parameters and default values are mentioned in the template. The available MPD
parameters can be overwritten with similar values of MHS assignment.

6.6.1.2.3 Platform Generator (Plat Gen)

Platform Generator (Platgen) is a document which compiles the high-level description

of embedded processor system. The details are translated into HDL netlists thatare supposed
to be implemented in an intended FPGA device. Platform Generator builds the architecture
with required memory blocks,initialization files forRAM block,BRAMS. PlatGen lists out the
details in MHS and MPD files respectively and they are as follows:

i) Hardware components
ii) List of Netlist docs
iii) List of downstream toolkits
iv) Wrappers of HDL

6.6.1.2.4 Xilinx Implementation Flow (XFlow)

Xilinx Implementation Flow is used for batch mode place and route.

6.6.1.3Software Flow

Once the hardware components and their functionalities are defined in the system,
control flow, software flow and intercommunications are defined. It is to be noted that
software communication is independent of the hardware flow.The software flow is illustrated
in figure 6.7.

6.6.1.3.1 Microprocessor Software Specification (MSS)

 MSS is a detailed specification the components of a microprocessor which is an auto-
generated/user modifiable file. The list of software options can be found in the same file. It
contains information such as versions, compilers, options and driver information.

Figure 6.7 –Software Flow

6.6.1.3.2 LibGen

Libgen is the short form for libraries and generations which is composed of various
libraries, drivers for various devices, files and their systems / structures, finally interrupt
handlers. On the whole the grouping is performed for generating a software platform for the
embedded processor system. The definition of a software platform indicates the connectivity
of each processor with its necessary drivers needed for accessing the peripherals, connect
with hardware components namely the board support package, required libraries, standard
input and output devices, interrupt handler routines, and other related software features.
Libgen understands the MSS and MHS components as its primary design inputs. Depending
on the software description files and libraries, Libgen controls the EDK libraries and other
processor core (pcore) with Microprocessor Driver Definition (MDD) and driver code) from
the EDK library and any user IP repository. LibGen configures libraries and device drivers. It
creates
i. Xparameters.h defines the list of files required for driver installations.
ii. libc.a, libm.a, libxil.a: defines the set of libraries which can be accessed by
the processor.

6.6.1.3.3 Compiler
GNU compiler tools are meant for compiling, interpreting and linking the program on
the processors to enable the execution. All user written programs are compiled in all cases,
checked for errors and hence it becomes a mandatory process during the execution.
Compilers are usually different according to the level of processors.
1. MicroBlaze processor utilizes the mb-gcc compiler.
2. Power PC processors utilizes the powerpc-eabi-gcc compilers.
3. XPS can accommodate GNU compiler for MicroBlaze.
6.6.1.3.3.1 Object-File Sections
An executable file takes the input sections from the users, concatenate them with the
object files (.o files) which have to be linked together in further execution stages. The
compiler, as the name intends, translates the code in a machine understandable format and
creates coding components to fit into proper and standard subjects. The following figure
illustrates the sectional layout of an object or an executable file.
 Figure 6.8 –Sectional Layout of an Object or Executable File []

6.6.1.3.4 Linker Scripts

The linker utility is a definition of the list of commands targeted towards the linker
scripts. All these scripts intend to divide the single program intorespective memories blocks.
All sections including the input objects, output objects are mapped with its connectivity
defined as an executable file. All the components are associated to a memory block as the
information is stored and retrieved from such blocks. The output sections, by default, are
mapped to memories in the system.

6.6.1.3.5 Xilinx Microprocessor Debugger (XMD)

An instruction set simulator is considered to be a virtual platform where the programs

can be debugged. The virtual platform is available on a board with Xilinx FPGA which is
also loaded with hardware bit-stream. The application executable ELF file is performed with
the debugger utility (XMD).The Executable and Linkable Format (ELF) is the common file
readable format considered asa standard in computational applications.The file format is a
binary representation of machine understandable instructions written in the perspective of a
specific processor. The same can also be represented in an intermediate form which performs
the operations on an interpreter to be executed.
For debugging the written code over a physical FPGA architecture, XMD will utilize
the same download cable as used to configure the FPGA with a bit-stream.

6.6.1.3.5.1 Bit-stream Initializer (Bitinit)

 The Bit-stream Initializer (Bitinit) is a tool which initializes the on-chip BRAM
memory. The initializer updates the processer with necessary software information. This
initializer is a utility with read-only capability with hardware-only bitstream (system.bit), and
generates the outputs of a new bitstream (download. bit). The information follows the
mandate defined in the embedded application executable (ELF) for every processor. The
utility implements the BMM file, generated by Platgen. The same is loaded onto the BRAM
with physical placement information on each BRAM block in the FPGA. Internally, the
Bitstream Initializer tool uses the Data2MEM utility provided in Integrated Software
Environment (ISE) to update the bitstream file.The flow of control in the complete EDK
program is depicted below is shown in figure 6.9.

Figure 6.9- XPS and EDK Leading to FPGA Configuration with components, links
and control flows
6.7 VISUAL BASIC 6.0
Figure6.10 – Logo of Visual Basic
Visual Basicis a comprehensive framework assisting users to build windows based
applications with convenient Graphic User Interface –GUI. The applications tend to possess
user-friendly appearances to the users. Visual Basic framework is based on events, indicating
that the code remains inactive until the users trigger an activity on the windows. The common
events are clicking by a mouse (left click, right click and scrolling functions) or keyboard
events. Visual Basic is operable through an event processor which allows the system to
respond with actions whenever an event is detected. The actual process code is executed only
when the corresponding event is triggered by the users. After the code is executed, the
Program control is returned to the event processor.

Visual Basic is built with abundant features and some of them are listed below:

 A list ofobjects - to facilitate the design of the application

 Pictures, icons and emoticons
 Capturing mouse and keyboard events
 Access to clipboards and connected printer access
 Mathematical functions
 String handling functions
 Graphical functions
 Variable and dynamic variable access through control arrays
 Files handling support sequentially and randomly
 Default debugger and default error-handling modules
 Comprehensive database access facilities
 ActiveX support

6.8 RESULTS OBTAINED FROM SIMULATED MODEL

The soft core MicroBlaze microprocessor is fitted into the Spartan 3E FPGA
architecture and is defined as a principal component of entire FPGA design
implementation.The following image in figure 6.11 is the input image, subjected to that is
given to the FPGA for tumor detection is as shown:

Figure 6.11 - Brain MRI Image

The MATLAB simulation software is loaded with a number of header files for processing
input images. The Xilinx Platform Studio along with the hardware of FPGA defined
embedded processor are combined together to develop the overall system. The base system
builder is used to define the required peripherals and various interfaces are chosen for
constructing the system.The screen capture is the representation of Xilinx Platform Studio
(XPS) design software. The soft processor MicroBlaze is instantiated along with all the
interfaces that are created for this project. The figure demonstrates the connectivity to the
MicroBlaze with processors, local bus and PLB. The other components are identified to be
the data local memory bus (DLMB) and instruction local memory bus (ILMB) and how they
are connected to Microblaze with their their respective controllers.
 Figure 6.12-System Assembly Viewof an Embedded Processor

The system is assembled and its bit-stream is defined. The processor is powered with
a software development for executing the required operations. From the observations, the size
of BRAM in FPGA is small, and hence we implemented a use off-chip memory known as
DDR SDRAM. The system block diagram is illustrated in Figure 6.13. Since DDR SDRAM
is an external memory segment, MPMC(Multi Port Memory Controller) core is
implementedfor connecting the external memory.The. elf file is written and stored in the right
location, with .bit file loaded to the FPGA. Xilinx Microprocessor Debugger is used toload
the .elf file and is uploaded to the FPGA as illustrated in the following figure 6.14 .
 Figure 6.13 - System Block Diagram

Figure 6.14 - Xilinx Microprocessor Debugger Implementation

The input images are sent into the system which delivers the output image with the detected
tumor. The detected segment is isolated from the input image and shown in a separate
window. The implementation of the system is obtained fromFPGA; interface is illustrated
using the Visual Basic software on the PC as shown below:

Figure 6.15- Detected tumor is isolated

The hardware setup is shown in the following image.

Figure 6.16- FPGA ArchitectureImplementation

According to the following report, device utilization is summarized and shown.

Figure 6.14- Summarized document of device utilization

 CHAPTER 7
CONCLUSION
Detecting brain tumor and segmenting them from the input brain images are
considered to be crucial step planning diagnosis, treatments and even surgery. This project
work, emphasizes on tumor detection from brain MR Imaging devices by implementing an
advancedK-means Clustering algorithm and improved Morphological filtering techniques as
a module of pre-processing. Beyond improving the features quality, enhancing the tumor
detected and classifying them into the right classification are the primary works proposed in
this project work. The results and performance aresimulated using MATLAB, along with
certain hardware components. The regions with tumorous cells are identified and segmented
out from the brain MRI images. Definitely there is a proven need for quality systems to
perform image processing algorithms which are reconfigurable and swift in producing quality
outcomes. The recent trends of medical domains expect the systems to be portable,
convenient to use and provide reliable results. Monitoring devices are continuous and
portable to facilitate real time detections and continuous tracking of patients’ health. This
became the motivation for conducting these project investigations and hence the model
defined a hardware implementation of our proposed algorithm on Field Programmable Gate
Arrays (FPGA) platform. Spartan series of FPGAs are implemented as Hardware
components, improved K-Means algorithm is used for detection and segmentation of brain
tumor detection from MRI image scans in the proposed algorithm.
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