Code No: 54117/MT M.Tech.

I Semester Supplementary Examinations, September, 2008 LOW POWER VLSI DESIGN (Common to Digital Systems & Computer Electronics/ Wireless & Mobile Communication) Time: 3hours Answer any FIVE questions All questions carry equal marks --1.

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Max. Marks:60

Discuss about the limitations of various parameters and constraints with respect to low-power low-voltage design of circuits pertaining to VLSI. How graded drawn structures can be produced? Explain with necessary schematic diagrams. How isolation is achieved in B1 CMOS process? Explain. Give the device structure and describe the fabrication process of Low-voltage/Low-power lateral BJT on SOI. Describe the static characteristics MOS transistor with the help of necessary equations for current-voltage relations. Using necessary equations, explain about the Base-Emitter and Base-collector Depletion capacitances. Draw the circuit for conventional B1 CMOS, Two-input NAND gate and describe its characteristics. Give the comparative evaluation of all the B1 CMOS circuits employing lateral parasitic PnP BJTs. Explain about the Full-swing multi drain/multi collector complimenting B1 CMOS buffers. Explain about the need for Low-power latches and Flip-Flops in VLSI design. Explain about the: i) Optimization theme ii) Performance theme and iii) Pipelining theme of latches and Flip-Flops. Contd2

2.a) b) 3. 4.a) b) 5. 6.a) b) 7.a) b)

Code No: 54117/MT 8. Write a) b) c)

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notes on any TWO: Sub-half Micron Devices Design perspectives of latches and Flip-Flops BSIM Model of MOSFET. *****