LPC 2148

1.2 Tnh nng:

- Vi iu khin 16/32-bit ARM7TDMI-S. - 40K RAM tnh (32K + 8K), 512K Flash. - Tch hp USB 2.0. - 2 b 10-bit ADC. - 1 b 10-bit DAC. - 2 b 32-bit timer, 6 ng iu xung. - ng h thi gian thc vi tn s ng vo 32kHz. - Kh nng thit lp u tin, nh a ch cho ngt. - 45 chn GPIO (ng vo/ra a dng). - 9 chn ngt ngoi (tch cc cnh hoc tch cc mc). - CPU clock t ti a 60MHz thng qua b PLL lp trnh c. - Xung PLCK hot ng c lp.

1.7 On-chip Flash Memory:

LPC 2148 c 512K b nh Flash c th c dng lu tr code v d liu. Trong khi thc thi ng dng, vn c th xa hoc lp trnh Flash thng qua IAP (In Application Programming). Khi trnh loader trn chip c s dng, b nh trng cn li l 500K. B nh Flash c th ghi xa c t nht 100000 ln, lu tr d liu n 20 nm.

1.8 On-chip Static RAM:

LPC 2148 c 32K RAM tnh, c th c truy xut theo n v byte, half word & word. B iu khin SRAM s dng phng thc write-back buffer ngn chn tnh trng treo CPU khi c thao tc ghi. B m lun gi d liu cui cng t chng trnh gi ti b nh. D liu ch c ghi vo SRAM khi c 1 thao tc ghi khc t chng trnh.

3.8 Phase Locked Loop (PLL):

LPC 2148 c 2 b PLL: PLL0 v PLL1. Ng ra PLL0 dng to xung h thng CCLK, ng ra PLL1 dng cung cp xung cho USB vi tn s xc nh l 48MHz. Xung thch anh bn ngoi c gi l Fosc, khi PLL khng c kt ni th CCLK = Fosc. PLL0 v PLL1 nhn tn s xung vo t 10-25MHz, xung ny c nhn ln thnh t 10-60MHz (cho CCLK) v 48MHz (cho USB clock) bng b CCO (Current Controled Oscillators). S nhn (M) c th l 1 s nguyn t 1-32, trn thc t ch ti a l 6 (Fsco = 10MHz & CCLK = 60MHz). B CCO hot ng trong khong tn s t 156-320MHz, do cn c 1 b chia tn s bo m tn s lm vic ca CCO trong khi PLL cung cp tn s mong mun. S chia (P) c th l 2, 4, 8, 16. Ng ra ca PLL l 1 xung c duty cycle l 50%.

Ta c cng thc: CCLK = Fosc x M Fcco = CCLK x 2 x P = Fosc x M x2 x P

PLL c iu khin qua thanh ghi PLLCON. S nhn (M) v s chia (P) ca PLL c iu khin bi thanh ghi PLLCFG. Hai thanh ghi ny c bo v trnh s thay i t ngt hoc tt PLL bi v mi hot ng ca chip u ph thuc vo PLL0 (v b ny cung cp xung h thng). Tng t cho b PLL1 ca USB. C 2 b PLL u tt khi Reset chip hoc khi vo ch Power-down, chng ch c khi ng bng phn mm. Chng trnh phi cu hnh v kch hot b PLL, i PLL lock, sau kt ni vo PLL vi vai tr nh ngun xung h thng. B PLL c iu khin bi cc thanh ghi: PLLCON, PLLCFG, PLLSTAT, PLLFEED. PLL Control Register (PLL0CON & PLL1CON): PLLCON cha cc bit kch hot v kt ni PLL. Kch hot PLL cho php kha cu hnh hin ti (vi 2 s M & P). Kt ni PLL lm chip v ton b cc chc nng chy theo xung nhp t ng ra PLL. Bit 0 K hiu PLLE ngha bit = 1: cho php kch hot PLL v kha ti tn s yu cu. 1 PLLC khi PLLE v PLLC = 1 th PLL c kt ni nh ngun xung cho vi iu khin 7:2 Reserved n/a 0 Gi tr sau Reset 0

PLL Configuration Register (PLL0CFG & PLL1CFG): PLLCFG cha gi tr s nhn M v s chia P ca b PLL. Bit 4:0 6:5 7 K hiu MSEL PSEL ngha s nhn M s chia P Reserved Gi tr sau Reset 0 0 n/a

PLL Status Register (PLL0STAT & PLL1STAT): PLLSTAT l thanh ghi ch c, n cha cc gi tr thc s ca b PLL ti thi im c thanh ghi ny. Bit 4:0 6:5 7 8 9 K hiu MSEL PSEL PLLE PLLC ngha Gi tr sau Reset 0

s nhn hin ti ang c s dng bi b PLL s chia hin ti ang c s dng bi b PLL 0 Reserved bit = 1: b PLL ang c kch hot bit = 1: b PLL ang c kch hot v kt ni.

n/a 0 0

10

PLOCK

bit = 0: PLL cha c kha bit = 1: PLL c kha vi tn s yu cu

15:11

Reserved

n/a

PLL Feed Register (PLL0FEED & PLL1FEED) Sau khi b PLL c kt ni, mi thay i trong 2 thanh ghi PLLCON & PLLCFG s khng c tc dng. thay i cu hnh PLL chn, phi ghi vo thanh ghi PLLFEED theo 1 th t xc nh: Ghi 0xAA vo PLLFEED Ghi 0x55 vo PLLFEED

Thao tc ghi phi theo ng th t, v lin k nhau.

******************************************************* V d: tnh ton tn s PLL: gi s tn s thch anh l 12MHz v tn s chip CCLK l 60MHz, khng s dng USB. Fosc: tn s dao ng thch anh Fcco: tn s dao ng ca PLL CCO CCLK: ng ra PLL, ng thi l xung h thng Ta c:

CCLK = Fosc x M Fcco = CCLK x 2 x P 156 MHz < Fcco < 320 MHz

M=5

1.3 < P < 2.7

P=2

Bng gi tr ca MSEL & PSEL: PSEL bits 6:5 ca PLLCFG 00 01 10 11 P 1 2 4 8

MSEL bits 4:0 PLLCFG 00000 00001 11110 11111

M 1 2 31 32

Vy PSEL = 01 v MSEL = 00100 Gi tr ghi vo thanh ghi PLLCFG s l 0x00000024

3.11 VPB Divider:

B chia VPB (VLSI Peripheral Bus) quyt nh quan h gia clock h thng (CCLK) v clock dng cho cc thit b ngoi vi (PCLK). Gi tr mc nh ca b chia VPB l PCLK = 1/4 CCLK.

VPBDIV Register: Bit 1:0 K hiu VPBDIV ngha 00: PCLK = 1/4 CCLK 01: PCLK = CCLK 10: PCLK = 1/2 CCLK 11: no effect 7:2 Reserved n/a Gi tr sau Reset 00

5.1 Vectored Interrupt Controler (VIC):

Khi iu khin ngt c th nhn 32 yu cu ngt, phn thnh 3 loai: FIQ, vectored IRQ & nonvectored IRQ. Fast Interrupt reQuest (FIQ) c mc u tin cao nht. Vectored IRQs c mc u tin trung bnh. Ch c 16/32 yu cu ngt c th gn vo loi ny ti 1 thi im. Bt k yu cu ngt no cng c th c gn vo 16 khe vectored IRQ (vectored IRQ slot). Trong khe 0 c mc u tin cao nht v khe 15 c mc u tin thp nht. Non-vectored IRQs c mc u tin thp nht.

Khi 1 ngt xy ra, VIC xc nh xem ngt thuc loi no, sau nhy n hm phc v ngt tng ng. FIQ: nhy n trnh phc v ngt dnh cho FIQ. Vectored IRQ: nhy n trnh phc v ngt dnh cho IRQ. Non-vectored IRQ: nhy n trnh phc v ngt mc nh.

Nu c nhiu hn 1 ngt xy ra VIC s xc nh xem ngt no c mc u tin cao nht v nhy n trnh phc v ngt . Trong trng hp vectored IRQ, nu khng tm thy a ch trnh phc v ngt tng ng, trnh phc v ngt mc nh s c gi. VIC Register: Bit K hiu 31 30 29 28 27 26 25 24 -

Bit K hiu

23 -

22 USB

21 AD1

20 BOD

19 I2C1

18 AD0

17

16

EINT3 EINT2

Bit K hiu

15

14

13 RTC

12 PLL

11 SPI1/SSP

10 SPI0

9 I2C0

8 PWM0

EINT1 EINT0

Bit K hiu

1 -

0 WDT

UART1 UART0 TMR1

TMR0 ARMCore1 ARMCore0

** Cc thanh ghi co k hiu (1) u c cu trc bit nh trn. Gi tr sau khi Reset ca cc thanh ghi ny l 0x00000000. VICIRQStatus(1): Truy cp: c. Bit 31:0 IRQ. Mc logic 1 ch ngt t ngun ngt ti bit tng ng c cho php v l

VICFIQStatus(1): Truy cp: c. Bit 31:0 Mc logic 1 ch ngt t ngun ngt ti bit tng ng c cho php v l

FIQ. VICRawIntr(1): Truy cp: c. VICIntSelect(1): Truy cp: c, ghi. Bit 31:0 - Mc logic 0: ngt t ngun ngt ti bit tng ng c xp vo IRQ. - Mc logic 1: ngt t ngun ngt ti bit tng ng c xp vo FIQ. VICIntEnable(1): Truy cp: c, ghi. Bit 31:0 - Khi c c: mc 1 ch ngun ngt ti bit tng ng c cho php. - Khi c ghi: mc 0: no effect. mc 1: cho php ngt t ngun ngt ti bit tng ng. VICIntEnClr(1): Truy cp: ghi. Bit 31:0 - Ghi mc 0: no effect. - Ghi mc 1: xa bit tng ng trong VICIntEnable, khng cho php ngt t ngun ngt ti bit tng ng.

VICSoftInt(1): Truy cp: c, ghi. Bit 31:0 - Ghi mc logic 0: no effect. - Ghi mc logic 1: yu cu 1 ngt t ngun ngt ti bit tng ng bng phn mm.

VICSoftIntClear(1): Truy cp: ghi. Bit 31:0 - Ghi mc logic 0: no effect. - Ghi mc logic 1: xa bit tng ng trong VICSoftInt.

VICProtection: Kim sot quyn truy cp vo VIC registers bng phn mm trong User mode.

VICVectAdrr: Khi ngt xy ra, trnh phc v ngt c thanh ghi ny v nhy ti a ch trong .

VICDefVectAdrr: Thanh ghi ny gi a ch trnh phc v ngt cho cc ngt thuc non-vectored IRQ. Khi trnh phc v ngt c thanh ghi VICVectAdrr v khng c IRQ slot no m nhn ngt ny th a ch tr v l gi tr trong thanh ghi ny.

VICVectAdrr0 VICVectAddr15: Cc thanh ghi ny gi a ch ca trnh phc v ngt (ISR) cho 16 IRQ slots. Khi xy ra ngt, gi tr ca 1 trong cc thanh ghi ny s c a n trnh phc v ngt khi trnh ny c thanh ghi VICVectAdrr.

VICVectCntl0 VICVectCntl15: Mi thanh ghi trong 16 thanh ghi ny iu khin 1 vectored IRQ slot. Slot 0 c mc u tin cao nht v slot 15 c mc u tin thp nht. Ch rng vic disable 1 IRQ slot trong cc thanh ghi VICVectCntl khng lm disable ngt, ngt ch b chuyn sang dng non-vectored IRQ. Bit 4:0 5 31:6 K hiu sw_int_assig IRQslot_en ghi mc 1: cho php ngt c trong slot ny Reserved 0 n/a ngha Gi tr sau Reset 0

int_request/ s hiu ca cc ngt

Cc ngun ngt WDT ARMCore0

s hiu 0 2

ARMCore1 TIMER0 TIMER1 UART0 UART1 PWM0 I2C0 SPI0 SPI1/SSP PLL RTC EINT0 EINT1 EINT2 EINT3 ADC0 I2C1 BOD ADC1 USB

3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22

7.1 Pin Connect Block

Vic cu hnh kt ni gia cc chn ca vi iu khin vi cc khi chc nng trn chip cho php 1 chn c kh nng thc hin nhiu chc nng thng qua cu hnh cc thanh ghi iu khin PIN. Khi la chn 1 chc nng cho 1 chn th cc chc nng khc khng th hot ng c trn cng chn (nhng vn c th trn cc chn khc). Cc thanh ghi iu khin bao gm: PINSEL0, PINSEL1, PINSELL2 (Pin funtion Select register). PINSEL0: Bit 1:0 K hiu P0.0 ngha 00 01 10 11 00 GPIO Port 0.0 TXD (UART0) PWM1 Reserved GPIO Port 0.1 Gi tr sau Reset 00

3:2

P0.1

00

5:4

P0.2

7:6

P0.3

9:8

P0.4

11:10

P0.5

13:12

P0.6

15:14

P0.7

17:16

P0.8

19:18

P0.9

21:20

P0.10

23:22

P0.11

25:24

P0.12

27:26

P0.13

29:28

P0.14

01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00

RxD (UART0) PWM3 EINT0 GPIO Port 0.2 SCL0 (I2C0) Capture 0.0 (Timer 0) Reserved GPIO Port 0.3 SDA0 (I2C0) Match 0.0 (Timer 0) EINT1 GPIO Port 0.4 SCK0 (SPI0) Capture 0.1 (Timer 0) AD0.6 GPIO Port 0.5 MISO0 (SPI0) Match 0.1 (Timer 0) AD0.7 GPIO Port 0.6 MOSI0 (SPI0) Capture 0.2 (Timer 0) AD1.0 GPIO Port 0.7 SSEL0 (SPI0) PWM2 EINT2 GPIO Port 0.8 TXD UART1 PWM4 AD1.1 GPIO Port 0.9 RxD (UART1) PWM6 EINT3 GPIO Port 0.10 RTS (UART1) Capture 1.0 (Timer 1) AD1.2 GPIO Port 0.11 CTS (UART1) Capture 1.1 (Timer 1) SCL1 (I2C1) GPIO Port 0.12 DSR (UART1) Match 1.0 (Timer 1) AD1.3 GPIO Port 0.13 DTR (UART1) Match 1.1 (Timer 1) AD1.4 GPIO Port 0.14

00

00

00

00

00

00

00

00

00

00

00

00

00

31:30

P0.15

01 10 11 00 01 10 11

DCD (UART1) EINT1 SDA1 (I2C1) GPIO Port 0.15 RI (UART1) EINT2 AD1.5

00

PINSEL1: Bit 1:0 K hiu P0.16 ngha 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 GPIO Port 0.16 EINT0 Match 0.2 (Timer 0) Capture 0.2 (Timer 0) GPIO Port 0.17 Capture 1.2 (Timer 1) SCK1 (SSP) Match 1.2 (Timer 1) GPIO Port 0.18 Capture 1.3 (Timer 1) MISO1 (SSP) Match 1.3 (Timer 1) GPIO Port 0.19 Match 1.2 (Timer 1) MOSI1 (SSP) Capture 1.2 (Timer 1) GPIO Port 0.20 Match 1.3 (Timer 1) SSEL1 (SSP) EINT3 GPIO Port 0.21 PWM5 AD1.6 Capture 1.3 (Timer 1) GPIO Port 0.22 AD1.7 Capture 0.0 (Timer 0) Match 0.0 (Timer 0) GPIO Port 0.23 VBUS Reserved Reserved Reserved Reserved Reserved Reserved GPIO Port 0.25 AD0.4 Aout(DAC) Gi tr sau Reset 00

3:2

P0.17

00

5:4

P0.18

00

7:6

P0.19

00

9:8

P0.20

00

11:10

P0.21

00

13:12

P0.22

00

15:14

P0.23

00

17:16

P0.24

00

19:18

P0.25

00

21:20

P0.26

23:22

P0.27

25:24

P0.28

27:26

P0.29

29:28

P0.30

31:30

P0.31

11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11

Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved GPIO Port 0.28 AD0.1 Capture 0.2 (Timer 0) Match 0.2 (Timer 0) GPIO Port 0.29 AD0.2 Capture 0.3 (Timer 0) Match 0.3 (Timer 0) GPIO Port 0.30 AD0.3 EINT3 Capture 0.0 (Timer 0) GPO Port only UP_LED CONNECT Reserved

00

00

00

00

00

00

PINSEL2: Bit 1:0 2 3 31:4 K hiu GPIO/ DEBUG GPIO/ TRACE ngha Reserved 0: P1.31-P1.26 used as GPIO 1: P1.31-P1.26 used as a Debug port 0: P1.25-P1.16 used as GPIO 1: P1.25-P1.16 used as a Trace port Reserved n/a Gi tr sau Reset n/a

8.1 General Purpose Input/Output ports (GPIO):

LPC 2148 c 2 port: Port 0: P0.0-P0.23, P0.25, P0.28-P0.30: input/output P0.31: output only Port 1: P1.16-P1.31: intput/output.

Vic truy cp cc port c th chia lm 2 cch: slow GPIO v fast GPIO. Cu hnh vic truy cp cc port theo 2 phng thc ni trn bng thanh ghi SCS (System Control and Status flags register).

SCS (System Control and Status flag register): Bit 0 K hiu GPIO0M ngha bit chn mode port 0 0: slow 1 GPIO1M 1: fast 0 Gi tr sau Reset 0

bit chn mode port 1 0: slow 1: fast

31:2

Reserved

n/a

Cc thanh ghi qun l xut nhp port 0: + Slow GPIO: IO0DIR: Bit 31:0 K hiu P0xDIR ngha bit 0 tng ng vi P0.0 0: chn tng ng l input 1: chn tng ng l output ngha 0: no effect 1: chn tng ng c set bng 1 ngha 0: no effect 1: chn tng ng c set bng 0 Gi tr sau Reset 0x00000000

IO0SET: Bit 31:0 K hiu P0xSET Gi tr sau Reset 0x00000000

IO0CLR: Bit 31:0 K hiu P0xCLR Gi tr sau Reset 0x00000000

IO0PIN:

Trng thi ca port 0 lun lun c c trong thanh ghi ny, d l input/output hay bt k chc nng no. Vic ghi vo thanh ghi IO0SET v IO0CLR ch nh hng ti cc chn c bit tng ng bng 1 cn vic ghi vo thanh ghi IO0PIN s nh hng ti ton b port 0. + Fast GPIO: FIO0DIR*: Tng t IO0DIR. FIO0MASK*: Qun l cc chn theo tp hp cc bit c gi tr 0 trong FIO0MASK. Vic ghi vo cc thanh ghi FIO0SET, FIO0CLR, FIO0PIN ch c tc dng vi tp hp chn nh ngha trong FIO0MASK, vic c t FIO0PIN cng vy. FIO0SET*:

Tng t IO0SET nhng ch c tc dng vi tp hp chn nh ngha trong FIO0MASK. FIO0CLR*: Tng t IO0CLR nhng ch c tc dng vi tp hp chn nh ngha trong FIO0MASK. FIO0PIN*: Tng t IO0PIN nhng ch c tc dng vi tp hp chn nh ngha trong FIO0MASK. * Ngoi ra, i vi Fast GPIO cn c cc thanh ghi truy cp theo n v byte, half-word: v d i vi FIO0DIR cn c: - FIO0DIR0: qun l t P0.0-P0.7 - FIO0DIR1: qun l t P0.8-P0.15 - FIO0DIR2: qun l t P0.16-P0.23 - FIO0DIR3: qun l t P0.24-P0.31 - FIO0DIRL: qun l t P0.0-P0.15 - FIO0DIRU: qun l t P0.16-P0.31

Cc thanh ghi qun l xut nhp port 1: tng t port 0 (IO1DIR, FIO1DIR). V d: Code C 1. Cu hnh chn P0.7 l output v a ra 1 xung trn chn ny: IO0DIR = 0x0000 0080 ;pin P0.7 configured as output IO0CLR = 0x0000 0080 ;P0.7 goes LOW IO0SET = 0x0000 0080 ;P0.7 goes HIGH IO0CLR = 0x0000 0080 ;P0.7 goes LOW 2. Xut d liu ng thi trn cc chn P0.8-P0.15 m khng lm nh hng ti cc chn cn li: Cch 1: IO0PIN = (IO0PIN & 0xFFFF00FF) | 0x0000A500 Cch 2: FIO0MASK = 0xFFFF00FF; FIO0PIN = 0x0000A500; Cch 3: FIO0MASKL = 0x00FF; FIO0PINL = 0xA500; Cch 4: FIO0PIN1 = 0xA5;

15.1 Timer/Counter TIMER0 and TIMER1:

Tnh nng chnh: 32-bit Timer/Counter vi b chia 32-bit lp trnh c (Programmable Prescaler). 4 knh chn bt gi tr ca Timer khi xy ra chuyn trng thi ng vo nh trc, c th gy ra ngt. 4 thanh ghi cha cc gi tr cho trc (Match Register), khi gi tr ca Timer bng gi tr cha trong cc thanh ghi ny s to ra 1 ngt v: - Tip tc chy Timer. - Dng Timer. - Reset Timer. - Thay i 1 ng ra nh trc: - set bng 1 - set bng 0

- o gi tr - khng lm gi c Timer/Counter c thit k m xung PCLK hoc 1 xung cp ngoi. Hot ng ca Timer/Counter v b Prescaler: thanh ghi PC tng ln 1 sau mi chu k PCLK, khi gi tr ca PC +1 bng gi tr ca thanh ghi PR (c t trc) th PC = 0 v thanh ghi TC (Timer Counter) tng ln 1. Cc chn c chc nng lin quan n Timer/Counter: Capture Signal: s chuyn trng thi trn cc chn ny th gi tr trong TC s c load vo 1 trong cc thanh ghi CR0-CR3 (Capture Register), c th gy ra ngt. Bao gm cc chn: CAP0.0: P0.2, P0.22 & P0.30 CAP0.1: P0.4 & P0.27 CAP0.2: P0.6, P0.16 & P0.28 CAP0.3: P0.29 CAP1.0: P0.10 CAP1.1: P0.11 CAP1.2 P0.17 & P0.19 CAP1.3: P0.18 & P0. 21

i vi cc chn c cng chc nng, khi c nhiu hn 1 chn c chn, chn c s thp hn s c s dng. V d: i vi CAP0.1 th chn P0.4 s c uu tin s dng. External Match Output: khi gi tr trong TC bng gi tr ca 1 trong cc thanh ghi MR0-MR3 th ng ra cc chn ny s c set bng 0, 1, o gi tr hoc khng lm g c, c th gy ra ngt. MAT0.0: P0.3 & P0.22 MAT0.1: P0.5 & P0.27 MAT0.2: P0.16 & P0.28 MAT0.3: P0.29 MAT1.0: P0.12 MAT1.1: P0.13 MAT1.2: P0.17 & P0.19 MAT1.3: P0.18 & P0.20

i vi MAT, khi c nhiu chn c cng chc nng c chn, chng s c iu khin song song vi nhau. Cc thanh ghi iu khin Timer/Counter: Interrupt Register (T0IR & T1IR): Khi xy ra ngt do Match hoc Capture th cc bit tng ng trong TCIR c set ln 1. Ghi mc logic 1 vo 1 bit s xa c ngt tng ng vi bit (vic ny thng c lm ngay trong hm phc v ngt update trng thi ngt, nu khng ngt s lin tc xy ra). Bit 0 1 2 3 4 5 6 7 K hiu MR0_Int MR1_Int MR2_Int MR3_Int CR0_Int CR1_Int CR2_Int CR3_Int ngha c ngt cho Match 0 c ngt cho Match 1 c ngt cho Match 2 c ngt cho Match 3 c ngt cho Capture 0 c ngt cho Capture 1 c ngt cho Capture 2 c ngt cho Capture 3 Gi tr sau Reset 0 0 0 0 0 0 0 0

Timer Control Register (T0TCR & T1TCR): Bit 0 1 K hiu Counter Enable Counter Reset ngha 0: disable Timer/Counter 1: enable Timer/Counter khi bit ny bng 1, TC v PC c Reset. tnh trng Reset c gi nguyn ti khi bit Counter Enable = 0. Reserved Gi tr sau Reset 0 0

7:2

n/a

Count Control Register (T0CTCR & T1CTCR): Bit 1:0 K hiu Timer/ Counter Mode Count Input Select ngha Gi tr sau Reset

3:2

7:4

00: Timer mode 00 01: Counter mode tch cc cnh ln 10: Counter mode tch cc cnh xung 11: Counter mode tch cc cnh ln & xung 00: CAP0.0 & CAP1.0 c dng cho Counter mode 00 01: CAP0.1 & CAP1.1 c dng cho Counter mode 10: CAP0.2 & CAP1.2 c dng cho Counter mode 11: CAP0.3 & CAP1.3 c dng cho Counter mode Reserved n/a

Timer Counter (T0TC & T1TC): Prescale Register (T0PR & T1PR): Prescale Counter (T0PC & T1PC):

PC tng ln 1 sau mi chu k ca PCLK, khi PC + 1 = PR th TC tng ln 1 v PC = 0. Match Register (T0MR0-3 & T1MR0-3): Khi TC = MRx, Timer c th b dng li hoc Reset, c th gy ra 1 ngt. Match Control Register (T0MCR & T1MCR): Bit 0 1 2 11:3 15:12 K hiu MR0I MR0R MR0S ngha 1: ngt khi TC = MR0 0: khng cho php ngt 1: TC b Reset khi TC = MR0 1: dng TC, set bit TR[0] v 0 tng t cho MR1, MR2 & MR3 Reserved Gi tr sau Reset 0 0 0 0 n/a

Capture Register (T0CR0-3 & T1CR0-3): Gi tr ca TC s c load vo 1 trong cc thanh ghi CR khi xy ra 1 chuyn trng thi trn cc chn CAP.

Capture Control Register (T0CCR & T1CCR): Bit 0 1 2 11:3 15:12 K hiu CAP0RE CAP0FE CAP0I ngha 1: Capture tch cc cnh ln 1: Capture tch cc cnh xung 1: gy ra ngt khi TC0 c load vo CR0 tng t cho CAP1, CAP2 & CAP3 Reserved Gi tr sau Reset 0 0 0 0 n/a

Khi set c 2 bit CAPxRE v CAPxFE th CAP xy ra khi c c cnh ln v cnh xung. External Match Register (T0EMR & T1EMR): Bit 0 1 2 3 5:4 K hiu EM0 EM1 EM2 EM3 EMC0 ngha Gi tr sau Reset 0 0 0 0 00

11:6 15:12

trng thi ca MAT0.0/MAT1.0 trng thi ca MAT0.1/MAT1.1 trng thi ca MAT0.2/MAT1.2 trng thi ca MAT0.3/MAT1.3 quyt nh trng thi ng ra trn cc chn MAT0.0 v MAT1.0 khi TC = MR0 00: khng lm g c 01: xa chn MAT0.0/MAT1.0 10: set chn MAT0.0/MAT1.0 ln 1 11: o gi tr chn MAT0.0/MAT1.0 tng t cho EMC1, EMC2 & EMC3 Reserved

00 n/a

Minh ha:

16.1 Pulse Width Modulator (PWM):

B to xung PWM c thit k da trn b Timer/Counter, hot ng theo xung PCLK. Nguyn tc hot ng da trn cc Match events ca 7 match register. C 2 loi xung: Single Edge: tt c cc xung u c set ln 1 ngay khi bt u 1 xung PWM, xung c set v 0 khi gi tr ca timer counter bng vi gi tr ca 1 trong cc Match register 1-6. C th c ti a 6 xung Single Edge ng thi, tt c cc xung u c cng tn s c iu khin bi Match register 0 (khi gi tr ca timer counter bng gi tr trong Match register 0 th kt thc 1 xung PWM v bt u 1 xung mi). Double Edge: cc xung c set bng 0 khi bt u 1 xung PWM, c set ln 1 bng 1 Match register v set v 0 bng 1 Match register khc. Cc xung double edge cng c tn s c iu khin bi Match register 0.

PWM2 & PWM4: double edge PWM5: single edge Bng cc knh PWM: Single Edge Knh Set by 1 2 3 4 5 6 Match 0 Match 0 Match 0 Match 0 Match 0 Match 0 Reset by Match 1 Match 2 Match 3 Match 4 Match 5 Match 6 Set by Match 1 Match 2 Match 3 Match 4 Match 5 Reset by Match 2 Match 3 Match 4 Match 5 Match 6 Double Edge

Ta c th thy c ti a 3 xung double edge ng thi (knh 2, 4 & 6) c th c iu khin c lp bng 7 Match register. Cc thanh ghi iu khin PWM: PWM Interrupt Register (PWMIR): Khi xy ra ngt do 1 knh PWM (xy ra match trn cc Match registers) th bit tng ng trong PWMIR s c set ln 1. Sau khi xy ra ngt phi ghi 1 vo bit xa c ngt (tng t T0IR & T1IR). Bit 0 1 2 3 7:4 8 K hiu PWM0_Int PWM1_Int PWM2_Int PWM3_Int PWM4_Int ngha c ngt PWM knh 0 c ngt PWM knh 1 c ngt PWM knh 2 c ngt PWM knh 3 Reserved c ngt PWM knh 4 Gi tr sau Reset 0 0 0 0 n/a 0

9 10 15:11

PWM5_Int PWM6_Int -

c ngt PWM knh 5 c ngt PWM knh 6 Reserved

0 0 n/a

PWM Timer Control Register (PWMTCR): Bit 0 1 K hiu Counter Enable Counter Reset PWM Enable ngha 0: disable Counter 1: enable Counter khi bit ny bng 1, TC v PC c Reset. tnh trng Reset c gi nguyn ti khi bit Counter Enable = 0. Reserved 0: disable PWM 1: enable PWM Reserved Gi tr sau Reset 0 0

2 3 7:4

n/a 0 n/a

PWM Timer Counter (PWMTC): Tng t T0TC & T1TC.

PWM Prescale Register (PWMPR): Tng t T0PR & T1PR.

PWM Prescale Counter (PWMPC): Tng t T0PC & T1PC.

PWM Match Register (PWMMR0-6): Tng t cc Match register ca Timer, khi xy ra match trn cc thanh ghi PWMMR0-6 ta c th cho dng timer, reset hoc yu cu ngt.

PWM Match Control Register (PWMMCR): Bit 0 1 2 20:3 31:21 K hiu ngha Gi tr sau Reset 0 0 0 0 n/a

PWMMR0I 1: ngt khi PWMTC = PWMMR0 (match 0) PWMMR0R 1: reset timer khi match 0 PWMMR0S 1: dng timer khi match 0 tng t cho PWMMR1-6 Reserved

PWM Control Register (PWMPCR): Kch hot v chn loi xung trn cc knh PWM. Bit 1:0 2 K hiu PWMSEL2 ngha Reserved 0: xung PWM2 l xung single edge Gi tr sau Reset n/a 0

6:3 8:7 9 14:10 15

1: xung PWM2 l xung double edge tng t cho cc xung PWM3-6 Reserved PWMENA1 0: disable PWM1 1: enable PWM1 tng t cho PWM6-2 Reserved

0 n/a 0 0 n/a

PWM Latch Enable Register (PWMLER): Khi ghi ln cc thanh ghi PWMMR0-6, d liu c lu gi trong cc shadow register. Khi xy ra match 0 (bt u 1 xung PWM), d liu ch c ghi ln cc thanh ghi PWMMR0-6 khi cc bit tng ng trong PWMLER c set bng 1, xung PWM mi s hot ng da trn cc gi tr mi. Nu xy ra vic chuyn gi tr t cc shadow register sang cc match register th cc bit tng ng trong PWMLER s c xa t ng. Bit 6:0 7 K hiu ngha cc bit tng ng cho PWMMR0-6 Reserved Gi tr sau Reset 0 n/a

17.1 Analog to Digital Converter (ADC):

LPC 2148 c 2 b ADC (ADC0 & ADC1) c th la chn ng vo t 1 trong 14 chn (ADC0: 6, ADC1: 8). o in p t 0 Vref (Vref khng c vt qu VDDA). Thi gian chuyn i 10 ti thiu l 2.44 us. Busrt conversion mode cho php t ng lp li vic chuyn i. B ADC hot ng theo xung VPB, tn s ti a l 4.5 MHz, 1 php chuyn i y cn 11 chu k. C th khi ng chuyn i bng phn cng da trn vic chuyn i trng thi ng vo ca cc chn cho trc. Cc thanh ghi iu khin b ADC: A/D Control Register (AD0CR & AD1CR): Bit 7:0 K hiu SEL ngha Gi tr sau Reset 0x01

15:8

CLKDIV

16

BURST

19:17

CLKS

la chn cc chn AD chuyn i. bit 0 la chn chn AD0.0/AD1.0 bit 7 la chn chn AD0.7/AD1.7 bit no c set ln 1 th cc chn tng ng s c chn. Gi tr mc nh l chn AD0.0/AD1.0 c chn. xung hot ng ca b ADC bng xung PCLK chia cho gi tr CLKDIV + 1. Xung hot ng ti a ca b ADC l 4.5 MHz 1: cho php lp li vic chuyn i t ng theo cc ch trong trng CLKS. 0: vic chuyn i do phn mm kim sot v cn 11 chu k cho 1 chuyn i. chn cc ch cho BURST: 000: 11 clocks/ 10 bits

000

20 21 23:22 26:24

PDN START

27

EDGE

31:28

001: 10 clocks/ 9 bits 010: 9 clocks/ 8 bits 011: 8 clocks/ 7 bits 100: 7 clocks/ 6 bits 101: 6 clocks/ 5 bits 110: 5 clocks/ 4 bits 111: 4 clocks/ 3 bits Reserved 0: ch power-down 1: ch bnh thng Reserved khi BURST = 0, iu khin khi no b ADC bt u chuyn i. khi BURST = 1, START phi bng 000. 000: no start 001: start now 010: bt u chuyn i khi c chuyn trng thi trn chn P0.16 011: P0.22 100: MAT0.1 101: MAT0.3 110: MAT1.0 111: MAT1.1 bit ny ch c tc dng khi START = 010-111 0: bt u khi c cnh ln 1: bt u khi c cnh xung Reserved

n/a 0 n/a 0

n/a

A/D Global Data Register (AD0GDR & AD1GDR): Bit 5:0 15:6 23:16 26:24 K hiu RESULT CHN ngha Reserved khi DONE = 1, in p chn Ain bng Vref nhn vi gi tr ny. Reserved xc nh ngun ca RESULT 000: t knh 0 111: t knh 7 Reserved c set ln 1 khi c 1 hoc nhiu kt qu chuyn i b mt hoc ghi ln trc khi t kt qu vo RESULT. Bit ny c xa khi c thanh ghi ny. bit ny bng 1 khi hon thnh 1 chuyn i, c xa khi thanh ghi ny c c v thanh ghi ADCR c ghi. Gi tr sau Reset n/a n/a n/a n/a

29:27 30

OVERRUN

n/a 0

31

DONE

A/D Global Start Register (ADGSR): Cho php khi to ng thi 2 b ADC0 & ADC1

Bit 15:0 31:16

K hiu -

ngha Reserved tng t bit 31:16 trong ADCR, c tc dng ln c 2 b ADC.

Gi tr sau Reset n/a

A/D Status Register (AD0STAT & AD1STAT): Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 31:17 K hiu DONE0 DONE1 DONE2 DONE3 DONE4 DONE5 DONE6 DONE7 OVERRUN0 OVERRUN1 OVERRUN2 OVERRUN3 OVERRUN4 OVERRUN5 OVERRUN6 OVERRUN7 ADINT ngha c DONE knh 0 c DONE knh 1 c DONE knh 2 c DONE knh 3 c DONE knh 4 c DONE knh 5 c DONE knh 6 c DONE knh 7 c OVERUN knh 0 c OVERUN knh 1 c OVERUN knh 2 c OVERUN knh 3 c OVERUN knh 4 c OVERUN knh 5 c OVERUN knh 6 c OVERUN knh 7 c ngt ca b ADC, c set khi hon thnh chuyn i 1 knh bt k Reserved Gi tr sau Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 n/a

A/D Interrupt Enable Register (AD0INTEN & AD1INTEN): Bit 0 K hiu ADINTEN0 ngha Gi tr sau Reset 0

7:1 8

31:9

0: khng gy ngt khi hon thnh chuyn i trn knh 0. 1: gy ngt khi hon thnh chuyn i trn knh 0 tng t cho knh 1-7 ADGINTEN 0: ch cho php yu cu ngt trn cc knh 1: ch cho php yu cu ngt khi bit DONE trn thanh ghi ADGDR c set. Reserved

0 0

n/a

A/D Data Register (AD0DR0-7 & AD1DR0-7): Bit 5:0 15:6 29:16 30 K hiu RESULT OVERRUN ngha Reserved kt qu chuyn i trn knh 0 Reserved Gi tr sau Reset n/a n/a n/a n/a

31

DONE

n/a

3.5 External Interrupt:

LPC2148 c 4 ngun ngt ngoi c th dng kch hot vi iu khin t ch Power-down. Cc chn ngt ngoi:
EINT0: P0.1 & P0.16 EINT1: P0.3 & P0.14 EINT2: P0.7 & P0.15 EINT3: P0.9, P0.20 & P0.30

Cc thanh ghi iu khin ngt: External Interrupt Flag register (EXTINT): Bit 0 K hiu EINT0 ngha c set ln 1 khi xy ra chuyn trng thi gy ra ngt (c quy nh trong EXTMODE & EXTPOLAR) trn chn EINT0 tng t cho EINT1, EINT2 & EINT3 Reserved Gi tr sau Reset 0

3:1 7:4

0 n/a

Ghi 1 vo cc bit EINT0-3 s xa cc bit tng ng. Trong ch tch cc mc, cc bt ny ch c xa khi cc chn ang trong trng thi khng tch cc. Interrupt Wakeup register (INTWAKE): Cho php cc ngt ngoi v cc ngun khc c kh nng kch hot vi iu khin t ch Power-down. Bit 0 3:1 4 5 13:6 14 15 K hiu ngha Gi tr sau Reset 0 0 n/a 0 n/a 0 0

EXTWAKE0 cho php kch hot vi iu khin bng EINT0 tng t cho EXTWAKE1-3 Reserved USBWAKE cho php kch hot vk bng USB Reserved BODWAKE cho php kch hot vk bng BOD RTCWAKE cho php kch hot vk bng RTC

External Interrupt Mode register (EXTMODE): Bit 0 K hiu ngha Gi tr sau Reset 0

EXTMODE0 0: EINT0 l tch cc mc 1: EINT0 l tch cc cnh

3:1 7:4

tng t cho EXTMODE1-3 Reserved

0 n/a

External Interrupt Polarity register (EXTPOLAR): Bit 0 K hiu ngha Gi tr sau Reset 0

3:1 7:4

EXTPOLAR0 0: EINT0 l tch cc mc thp hoc tch cc cnh xung (ty vo EXTMODE0) 1: EINT0 l tch cc mc cao hoc tch cc cnh ln tng t cho EXTPOLAR1-3 Reserved

0 n/a

Khi la chn cc chn input cho ngt ngoi, ta c th la chn nhiu hn 1 chn cho 1 ngun ngt, khi cc tn hiu s c x l ty vo cc ch : - ch tch cc mc thp, cc tn hiu trn cng 1 ngun EINTx s c AND li thnh 1 tn hiu duy nht. - ch tch cc mc cao, cc tn hiu trn cng 1 ngun EINTx s c OR li thnh 1 tn hiu duy nht. - ch tch cc cnh (ln hoc xung), chn c s nh nht s c s dng. V d: t PINSEL0 v PINSEL1 ta chn ngun cho EINT3 l P0.9, P0.20 v P0.30, ngt c t ch tch cc mc thp, khi tn hiu t 3 chn ny s c AND li thnh ngun cho EINT3.