V Balasubrahmanyam D. M.

Tech VLSI Design

email id: varma.sunshine@live.com mobile: +91 9945260664, 9989330002

CAREER OBJECTIVE:
Seeking a responsible job to start my career by contributing my share to the growth of organization and developing my skills with evolving technology.

EDUCATION DETAILS:
Degree & Discipline Institute Year of Passing 2012 Aggregate (%) 77.54

M.Tech V L S I Design B.Tech Electrical & Electronics Engineering Intermediate 10th standard

Vellore Institute of Technology (VIT University)

Sri Vasavi Engineering College

2010

72.25

Aditha VidyaSagar Jr. college Sri Rama Vidyaniketan

2006 2004

89.50 84.00

TECHNICAL KNOWLEDGE:
RTL Coding in Verilog HDL PERL & TCL scripting Working experience of Cadence Functional verification tools: Model-Sim Design architect (Mentor Graphics) Other tools: Xilinx Programming in C language working knowledge of Linux and windows operating systems ASIC Design Verilog RTL Hardware description language PERL

AREA OF INTEREST:
Digital Logic and Digital IC Design Physical Design STA

PROJECTS:
Main Project:

M.Tech VLSI Design

Hybrid Final Adder design for High Performance Multiplier with TDM Interconnections
The project aims at designing a hybrid final adder for optimal performance of parallel multiplier by analysing different circuits in accordance to their signal arrival profile from the partial product reduction stage to the final adder along with area and power considerations. Tool used: cadence

Mini projects: done during M.Tech Design Of Flash ADC Based On A CMOS Inverter
This project is to prove that CMOS inverters usage in mixed signal IC designs can be substantially beneficial. Tools used: cadence-virtuoso

Fully Depleted Tri-Gate Transistors- A Review.

This project is a review of Tri-Gate transistors which is a geometric modification of existing one and a study of its merits and demerits.

Low Power Linear Feedback Shift Register

This project is meant to study a way to reduce power consumption of linear Feedback shift register by applying clock gating technique. Tools used: Xilinx

BEC modified 128 bit Carry Select Adder

This project is continuation of BEC modification work for Carry select adder for higher bit sizes. Tools used: modelsim, cadence(NC-sim)

PUBLICATIONS:
My project work on Optimization of Hybrid Final Adder design for High Performance Multiplier (HPM) got selected for publication in IEEE Xplore. My work on Low Power Linear Feedback Shift Register is presented in Second International Conference on Science Engineering and Technology. My work on BEC modified 128 bit Carry Select Adder is presented in Third International Conference on Science Engineering and Technology.

PERSONAL INFORMATION:
Name Father name Gender Date of Birth Languages Known Address : Venkata Balasubrahmanyam Dandu : Dandu Rama Raju : male : 30th Aug -1989 : English, Hindi and Telugu : 1-10-3/1, near durga temple, namala vari Street, gollagudem center, Tadepalligudem-534101, West Godavari District, Andhra Pradesh : Indian

Nationality

REFERENCES:
Dr. Harish M. Kittur, Professor, School of Electronics Engineering VIT University, Vellore. mobile number: 9566814544 Mr. S. Sriram Karthik, Component Design Engineer, Intel India pvt Ltd, Bangalore. Mobile Number: 8861057369

DECLARATION:
I hereby declare that the above-mentioned information is correct up to my knowledge and I bear the responsibility for the correctness of the above-mentioned particulars.

(V Balasubrahmanyam Dandu)