Pipelined Parallel FFT Architectures via Folding Transformation

Abstract In this work a novel approach to develop parallel pipelined architectures for the fast Fourier transform (FFT) is developed. A formal procedure for designing FFT architectures using folding transformation and register minimization techniques is developed. Novel parallelpipelined architectures for the computation of complex and real valued fast Fourier transform are derived. For complex valued Fourier transform (CFFT), the proposed architecture takes advantage of underutilized hardware in the serial architecture to derive -parallel architectures without increasing the hardware complexity by a factor of L. The operating frequency of the developed architecture can be decreased which in turn reduces the power consumption. Further, this work presents new parallel-pipelined architectures for the computation of realvalued fast Fourier transform (RFFT). The proposed architectures exploit redundancy in the computation of FFT samples to reduce the hardware complexity. The output samples are obtained in a scrambled order in the proposed architectures. Circuits to reorder these scrambled output sequences to a desired order are presented. The work is implemented on Spartan-3 XC3S400PQ208 field-programmable gate array from Xilinx, Inc.