The Design of Hybrid Symmetric-FIR (Analog Pulse-Shaping) Filters

Abstract
This work presents a method for designing linear phase square-root (SR) FIR digital filters that alleviate the effect of receiver timing jitter. We take a newly conceived parameter, the roughness of the analog/FIR-SR filter impulse response, into account. We show that the error-performance of a system employing a matched SR filter pair, in the presence of receiver timing jitter, is more strongly related to how well the roughness parameter is minimized, than it is to the maximizing of the eye width caused by the Nyquist pulse.

Aim
To design Hybrid Symmetric-FIR (Analog Pulse-Shaping) Filters using FPGA

Objective
The objectives of this works are, 1. Design of Hybrid Symmetric-FIR (Analog Pulse-Shaping) Filters using VHDL 2. Functional verification of Hybrid Symmetric-FIR (Analog Pulse-Shaping) Filters 3. Result analysis in terms of a. Area b. Power c. Speed

Tools to be used:
For functional simulation For synthesis and implementation Mentor Graphics ModelSim 6.5 or later Xilinx Incs Xilinx ISE 13.1or later version

For FPGA based implementation, the FPGA Details are,

Manufacturer Family FPGA Series Xilinx Spartan 3/Spartan 3E XC3S400PQ208/XC3S250EPQ208

For CPLD based implementation, the CPLD Details are,

Manufacturer Family CPLD Series Xilinx XC9500 XC9572-XL

HDL to be used:
VHDL/Verilog HDL

Project Report Details:

Soft copy of documents referred by our guide to do the project will be given to prepare the report.