SSN COLLEGE OF ENGINEERING, KALAVAKKAM Department of Computer Science and Engineering

B.E. (CSE) III semester UNIT TEST III 141302 - Digital Principles and System Design Date: 14.10.2011 Staff: Mr. K. R. Sarath Chandran / Ms. M. A. Padma Priya Time: 08.00 09:30 A.M Max. Marks: 50 PART-A: [5*2=10]

1. Draw the circuit diagram of a JK flip flop using D Flip Flop. 2. Differentiate between synchronous and asynchronous counters. 3. What are the applications of shift registers. 4. List down the Characteristic equations for JK, SR, T and D Flip-Flop. 5. Explain preset and clear inputs of flip flops. PART B: 6. Analyze the following Sequential Circuit. [8+ 16+16 =40] [8]

ANSWER ANY TWO 7. a) Design a BCD ripple counter b) Design and explain universal shift register [8] [8]

[PTO]

8. a)Design a mod-7 synchronous counter using JK flip flop b) Obtain the Reduced state diagram from the following diagram

[8] [8]

9.a) Explain the internal operation of the Master-slave JK Flip Flop. b) Design a synchronous sequential circuit for the following state diagram by using JK Flip Flop

[6] [10]

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