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PIC16F84
D VDD R1 16k S1 SW-PB C5 VSS C 4n7 PIC TXD 5V DSR 5V DTR PIC RXD 16 4 17 18 1 2 3 6 VSS IC_PIC1 OSC1/CLKIN OSC2/CLKOUT MCLR RB1 RA0 RB2 RA1 RB3 RA2 RB4 RA3 RB5 RA4/T0CKI RB6 RB0/INT RB7 VSS PIC16F84-04/P(18) 5 15 7 8 9 10 11 12 13 VDD C1 10p (Direction seen from controller) XT1 4.000 MHz VDD 14 VSS RS232 TXD RS232 DTR PIC TXD 5V DSR 13 RS232 8 11 5V 10 1 3 C6 10u C2 10p

MAX232
D VDD VSS C3 10u C4 10u 2 6 16 U1 R1 IN R2 IN T1 IN T2 IN C1+ C1 R1 OUT R2 OUT T1 OUT T2 OUT C2+ C2 12 9 14 7 4 5 V+ VVCC 5V RS232 PIC RXD 5V DTR RS232 RXD RS232 DSR

MAX232CPE(16) 15

GND

C7 10u

VSS

VDD VDD B VSS VSS RS232 DTR RS232 TXD RS232 RXD RS232 DSR 1 6 2 7 3 8 4 9 5
Title

VSS C8 100n VDD

RS232
(Direction seen from host) VSS

DSR and DTR signals are not used in my RS232 routines, but are drawn for completion. These signals are necessary for hardware handshaking, whilst my routines perform no handshaking. The MAX232 has two output and two input channels, specified to transmit up to 120 kbps depending on the type used.

B C9 100n VSS

PIC-RS232 Interface using MAX232

A SUB1 DB9 1 2 3
Written by Date Revision

A
20-Aug-2003 1.01
Page

Peter Luethi Dietikon, Switzerland

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