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General Description
The Ultra37000 family of CMOS CPLDs provides a range of high-density programmable logic solutions with unparalleled system performance. The Ultra37000 family is designed to bring the flexibility, ease of use, and performance of the 22V10 to high-density CPLDs. The architecture is based on a number of logic blocks that are connected by a Programmable Interconnect Matrix (PIM). Each logic block features its own product term array, product term allocator, and 16 macrocells. The PIM distributes signals from the logic block outputs and all input pins to the logic block inputs. All of the Ultra37000 devices are electrically erasable and In-System Reprogrammable (ISR), which simplifies both design and manufacturing flows, thereby reducing costs. The ISR feature provides the ability to reconfigure the devices without having design changes cause pinout or timing changes. The Cypress ISR function is implemented through a JTAG-compliant serial interface. Data is shifted in and out through the TDI and TDO pins, respectively. Because of the superior routability and simple timing model of the Ultra37000 devices, ISR allows users to change existing logic designs while simultaneously fixing pinout assignments and maintaining system performance. The entire family features JTAG for ISR and boundary scan, and is compatible with the PCI Local Bus specification, meeting the electrical and timing requirements. The Ultra37000 family features user programmable bus-hold capabilities on all I/Os. Ultra37000 5.0V Devices The Ultra37000 devices operate with a 5V supply and can support 5V or 3.3V I/O levels. VCCO connections provide the capability of interfacing to either a 5V or 3.3V bus. By connecting the VCCO pins to 5V the user insures 5V TTL levels on the outputs. If VCCO is connected to 3.3V the output levels meet 3.3V JEDEC standard CMOS levels and are 5V tolerant. These devices require 5V ISR programming. Ultra37000V 3.3V Devices Devices operating with a 3.3V supply require 3.3V on all VCCO pins, reducing the devices power consumption. These devices support 3.3V JEDEC standard CMOS output levels, and are 5V-tolerant. These devices allow 3.3V ISR programming.
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200
167
154
143 X X
125
100 X X
83
66
X X X
X X X X X X X
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3 016
PRODUCT TERMS
2 I/O CELL 0
MACROCELL 0 MACROCELL 1
016
PRODUCT TERMS
to cells 2, 4, 6 8, 10, 12
FROM PIM
36
80
MACROCELL 14 MACROCELL 15
I/O CELL 14
016 TO PIM 16 8
PRODUCT TERMS
Figure 1. Logic Block with 50% Buried Macrocells Low-Power Option Each logic block can operate in high-speed mode for critical path performance, or in low-power mode for power conservation. The logic block mode is set by the user on a logic block by logic block basis. Product Term Allocator Through the product term allocator, software automatically distributes product terms among the 16 macrocells in the logic block as needed. A total of 80 product terms are available from the local product term array. The product term allocator provides two important capabilities without affecting performance: product term steering and product term sharing. Product Term Steering Product term steering is the process of assigning product terms to macrocells as needed. For example, if one macrocell requires ten product terms while another needs just three, the product term allocator will steer ten product terms to one macrocell and three to the other. On Ultra37000 devices, product terms are steered on an individual basis. Any number between 0 and 16 product terms can be steered to any macrocell. Note that 0 product terms is useful in cases where a particular macrocell is unused or used as an input register. Product Term Sharing Product term sharing is the process of using the same product term among multiple macrocells. For example, if more than one output has one or more product terms in its equation that are common to other outputs, those product terms are only programmed once. The Ultra37000 product term allocator allows sharing across groups of four output macrocells in a variable fashion. The software automatically takes advantage of this capabilitythe user does not have to intervene. Note that neither product term sharing nor product term steering have any effect on the speed of the product. All worst-case steering and sharing configurations have been incorporated in the timing specifications for the Ultra37000 devices. Ultra37000 Macrocell Within each logic block there are 16 macrocells. Macrocells can either be I/O Macrocells, which include an I/O Cell which is associated with an I/O pin, or buried Macrocells, which do not connect to an I/O. The combination of I/O Macrocells and buried Macrocells varies from device to device. Buried Macrocell Figure 2 displays the architecture of buried macrocells. The buried macrocell features a register that can be configured as combinatorial, a D flip-flop, a T flip-flop, or a level-triggered latch. The register can be asynchronously set or asynchronously reset at the logic block level with the separate set and reset product terms. Each of these product terms features programmable polarity. This allows the registers to be set or reset based on an AND expression or an OR expression. Clocking of the register is very flexible. Four global synchronous clocks and a product term clock are available to clock the register. Furthermore, each clock features programmable polarity so that registers can be triggered on falling as well as rising edges (see the Clocking section). Clock polarity is chosen at the logic block level.
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I/O MACROCELL
FROM PTM
016 PRODUCT TERMS
0 1
C25 P D/T/L 0 1 2 3 O R DECODE Q
C26
I/O CELL
C0 C1 C24
1 0
C6 C5 C2 C3
BURIED MACROCELL
0 1
0 0 1 2 3 1 Q C7
0 O P D/T/L R DECODE Q 1
C0 C1 C24
1 0
C2 C3
FEEDBACK TO PIM FEEDBACK TO PIM FEEDBACK TO PIM ASYNCHRONOUS BLOCK RESET 4 SYNCHRONOUS CLOCKS (CLK0,CLK1,CLK2,CLK3) ASYNCHRONOUS 1 ASYNCHRONOUS CLOCK(PTCLK) BLOCK PRESET
OE0 OE1
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TO PIM
0 1 2 3 C10 C11
D O
D LE
0 1 2 3
D O
D LE
Figure 4. Input/Clock Macrocell Clocking Each I/O and buried macrocell has access to four synchronous clocks (CLK0, CLK1, CLK2 and CLK3) as well as an asynchronous product term clock PTCLK. Each input macrocell has access to all four synchronous clocks. Dedicated Inputs/Clocks Five pins on each member of the Ultra37000 family are designated as input-only. There are two types of dedicated inputs on Ultra37000 devices: input pins and input/clock pins. Figure 3 illustrates the architecture for input pins. Four input options are available for the user: combinatorial, registered, double-registered, or latched. If a registered or latched option is selected, any one of the input clocks can be selected for control. Figure 4 illustrates the architecture for the input/clock pins. Like the input pins, input/clock pins can be combinatorial, registered, double-registered, or latched. In addition, these pins feed the clocking structures throughout the device. The clock path at the input has user-configurable polarity. Product Term Clocking In addition to the four synchronous clocks, the Ultra37000 family also has a product term clock for asynchronous clocking. Each logic block has an independent product term clock which is available to all 16 macrocells. Each product term clock also supports user configurable polarity selection. Timing Model One of the most important features of the Ultra37000 family is the simplicity of its timing. All delays are worst case and system performance is unaffected by the features used. Figure 5 illustrates the true timing model for the 167-MHz devices in high speed mode. For combinatorial paths, any input to any output incurs a 6.5-ns worst-case delay regardless of the amount of logic used. For synchronous systems, the input set-up time to the output macrocells for any input is 3.5 ns and the clock to output time is also 4.0 ns. These measurements are for any output and synchronous clock, regardless of the logic used. The Ultra37000 features: No fanout delays No expander delays No dedicated vs. I/O pin delays No additional delay through PIM No penalty for using 016 product terms No added delay for steering product terms No added delay for sharing product terms No routing delays No output bypass delays The simple timing model of the Ultra37000 family eliminates unexpected performance penalties.
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resources for pinout flexibility, and a simple timing model for consistent system performance.
OUTPUT
tCO = 4.5 ns
OUTPUT
INPUT
CLOCK
TMS TCK
Data Registers
Figure 6. JTAG Interface In-System Reprogramming (ISR) In-System Reprogramming is the combination of the capability to program or reprogram a device on-board, and the ability to support design changes without changing the system timing or device pinout. This combination means design changes during debug or field upgrades do not cause board respins. The Ultra37000 family implements ISR by providing a JTAG compliant interface for on-board programming, robust routing
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TDO
PIM
16
LOGIC BLOCK B 16
CY37064/CY37064V
Input
Clock/ Input
16 I/Os I/O48-I/O63
PIM
36 16 I/Os I/O32-I/O47 16
16 I/Os I/O16-I/O31
32
TDI TCK TMS JTAG Tap Controller
32
TDO
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CLOCK INPUTS INPUTS 1 INPUT MACROCELL 4 16 I/Os LOGIC BLOCK 4 INPUT/CLOCK MACROCELLS 4 36 PIM 16 36 16 36 16 36 16
Clock/ Input 4
TCK TMS
TDO
JTAGEN
I/O0I/O15
36 16 36 16 36 16 36 16
LOGIC BLOCK
16 I/Os
I/O112I/O127
I/O16I/O31
16 I/Os
LOGIC BLOCK
LOGIC BLOCK
16 I/Os
I/O96I/O111
I/O32I/O47
16 I/Os
LOGIC BLOCK
LOGIC BLOCK
I/O28I/O63
16 I/Os
LOGIC BLOCK
LOGIC BLOCK
64
64
Input 1
CY37192/CY37192V
4 10 I/Os I/O0I/O9 10 I/Os I/O10I/O19 10 I/Os I/O20I/O29 10 I/Os I/O30I/O39 10 I/Os I/O40I/O49 10 I/Os I/O50I/O59 LOGIC BLOCK A LOGIC BLOCK B LOGIC BLOCK C LOGIC BLOCK D LOGIC BLOCK E LOGIC BLOCK F 60 36 16 36 16 36 16 36 16 36 16 36 16 36 16 36 16 36 16
4 LOGIC BLOCK L LOGIC BLOCK K LOGIC BLOCK J LOGIC BLOCK I LOGIC BLOCK H LOGIC BLOCK G 60 10 I/Os I/O110I/O119 10 I/Os I/O100I/O109 10 I/Os I/O90I/O99 10 I/Os I/O80I/O89 10 I/Os I/O70I/O79 10 I/Os I/O60I/O69
PIM
36 16 36 16 36 16
TDO
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4 12 I/Os I/O0I/O11 12 I/Os I/O12I/O23 12 I/Os I/O24I/O35 I/O36I/O47 12 I/Os LOGIC BLOCK A LOGIC BLOCK B LOGIC BLOCK C LOGIC BLOCK D LOGIC BLOCK E LOGIC BLOCK F LOGIC BLOCK G LOGIC BLOCK H 96 36 16 36 16 36 16 36 16 36 16 36 16 36 16 36 16 36 16 36 16 36 16 36 16
4 LOGIC BLOCK P LOGIC BLOCK O LOGIC BLOCK N LOGIC BLOCK M LOGIC BLOCK L LOGIC BLOCK K LOGIC BLOCK J LOGIC BLOCK I 96 12 I/Os I/O180I/O191 12 I/Os I/O168I/O179 12 I/Os I/O156I/O167 12 I/Os I/O144I/O155 12 I/Os I/O132I/O143 12 I/Os I/O120I/O131 12 I/Os I/O108I/O119 12 I/Os I/O96I/O107
12 I/Os I/O48I/O59 12 I/Os I/O60I/O71 12 I/Os I/O72I/O83 12 I/Os I/O84I/O95 TDI TCK TMS
PIM
36 16 36 16 36 16 36 16
TDO
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4 12 I/Os I/O0I/O11 12 I/Os I/O12I/O23 I/O24I/O35 12 I/Os LOGIC BLOCK AA LOGIC BLOCK AB LOGIC BLOCK AC LOGIC BLOCK AD 12 I/Os I/O36I/O47 LOGIC BLOCK AE LOGIC BLOCK AF 12 I/Os I/O48I/O59 12 I/Os I/O60I/O71 12 I/Os I/O72I/O83 LOGIC BLOCK AG LOGIC BLOCK AH LOGIC BLOCK AI LOGIC BLOCK AJ 12 I/Os I/O84I/O95 LOGIC BLOCK AK LOGIC BLOCK AL TDI TCK TMS 36 16 36 16 36 16 36 16 36 16 36 16 36 16 36 16 36 16 36 16 36 16 36 16 36 16 36 16 36 16 36 16
4 LOGIC BLOCK BL LOGIC BLOCK BK LOGIC BLOCK BJ LOGIC BLOCK BI LOGIC BLOCK BH LOGIC BLOCK BG LOGIC BLOCK BF LOGIC BLOCK BE LOGIC BLOCK BD LOGIC BLOCK BC LOGIC BLOCK BB LOGIC BLOCK BA 12 I/Os I/O96I/O107 12 I/Os I/O120I/O143 12 I/Os I/O108I/O131 12 I/Os I/O96I/O119 12 I/Os I/O132I/O155 12 I/Os I/O168I/O191 12 I/Os I/O156I/O179 12 I/Os I/O144I/O167
PIM
36 16 36 16 36 16 36 16 36
16
36 16 36 16 36 16
TDO
96
96
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4 12 I/Os I/O0I/O11 12 I/Os I/O12I/O23 12 I/Os I/O24I/O35 LOGIC BLOCK AA LOGIC BLOCK AB LOGIC BLOCK AC LOGIC BLOCK AD 12 I/Os I/O36I/O47 LOGIC BLOCK AE LOGIC BLOCK AF 12 I/Os I/O48I/O59 LOGIC BLOCK AG LOGIC BLOCK AH 12 I/Os I/O60I/O71 LOGIC BLOCK AI LOGIC BLOCK AJ 12 I/Os I/O72I/O83 12 I/Os I/O84I/O95 12 I/Os I/O96I/O107 12 I/Os I/O108I/O119 12 I/Os I/O120I/O131 LOGIC BLOCK AK LOGIC BLOCK AL LOGIC BLOCK AM LOGIC BLOCK AN LOGIC BLOCK AO LOGIC BLOCK AP 132 TDI TCK TMS JTAG Tap Controller TDO 36 16 36 16 36 16 36 16 36 16 36 16 36 16 36 16 36 16 36 16 36 16 36 16 36 16 36 16 36 16 36 16 36 16 36 16 36 16 36 16 36 16 36 16 36 16 36 16
4 LOGIC BLOCK BP LOGIC BLOCK BO LOGIC BLOCK BN LOGIC BLOCK BM LOGIC BLOCK BL LOGIC BLOCK BK LOGIC BLOCK BJ LOGIC BLOCK BI LOGIC BLOCK BH LOGIC BLOCK BG LOGIC BLOCK BF LOGIC BLOCK BE LOGIC BLOCK BD LOGIC BLOCK BC LOGIC BLOCK BB LOGIC BLOCK BA 132 12 I/Os I/O180I/O191 12 I/Os I/O168I/O179 12 I/Os I/O156I/O167 12 I/Os I/O144I/O155 12 I/Os I/O132I/O143 12 I/Os I/O192I/O203 12 I/Os I/O204I/O215 12 I/Os I/O216I/O227 12 I/Os I/O252I/O263 12 I/Os I/O240I/O251 12 I/Os I/O228I/O239
PIM
36 16 36 16 36 16 36 16 36 16 36 16 36 16 36 16
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Operating Range[2]
Range Commercial Industrial Military[3] Ambient Temperature[2] 0C to +70C 40C to +85C 55C to +125C Junction Temperature 0C to +90C 40C to +105C 55C to +130C Output Condition 5V 3.3V 5V 3.3V 5V 3.3V VCC 5V 0.25V 5V 0.25V 5V 0.5V 5V 0.5V 5V 0.5V 5V 0.5V VCCO 5V 0.25V 3.3V 0.3V 5V 0.5V 3.3V 0.3V 5V 0.5V 3.3V 0.3V
Guaranteed Input Logical HIGH Voltage for all Inputs[7] Guaranteed Input Logical LOW Voltage for all VI = GND OR VCC, Bus-Hold Disabled VO = GND or VCC, Output Disabled, Bus-Hold Disabled VCC = Min., VIL = 0.8V VCC = Min., VIH = 2.0V VCC = Max. VCC = Max.
Notes: 2. Normal Programming Conditions apply across Ambient Temperature Range for specified programming methods. For more information on programming the Ultra37000 Family devices, please refer to the Application Note titled An Introduction to In System Reprogramming with the Ultra37000. 3. TA is the Instant On case temperature. 4. IOH = 2 mA, IOL = 2 mA for TDO. 5. Tested initially and after any design or process changes that may affect these parameters. 6. When the I/O is output disabled, the bus-hold circuit can weakly pull the I/O to above 3.6V if no leakage current is allowed. Note that all I/Os are output disabled during ISR programming. Refer to the application note Understanding Bus-Hold for additional information. 7. These are absolute values with respect to device ground. All overshoots due to system or tester noise are included. 8. Not more than one output should be tested at a time. Duration of the short circuit should not exceed 1 second. VOUT = 0.5V has been chosen to avoid test problems caused by tester ground degradation.
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Capacitance[5]
Parameter CI/O CCLK CDP Description Input/Output Capacitance Clock Signal Capacitance Dual-Function Pins
[9]
Test Conditions VIN = 5.0V at f = 1 MHz at TA = 25C VIN = 5.0V at f = 1 MHz at TA = 25C VIN = 5.0V at f = 1 MHz at TA = 25C Test Conditions Normal Programming Conditions[2]
Max. 10 12 16
Unit pF pF pF
Endurance
Parameter N
Characteristics[5]
Description Minimum Reprogramming Cycles Min. 1,000 Typ. 10,000 Unit Cycles
DC Voltage Applied to Outputs in High-Z State................................................0.5V to +7.0V DC Input Voltage ............................................0.5V to +7.0V DC Program Voltage............................................. 3.0 to 3.6V Current into Outputs ...................................................... 8 mA Static Discharge Voltage........................................... > 2001V (per MIL-STD-883, Method 3015) Latch-up Current..................................................... > 200 mA
Operating Range[2]
Range Commercial Industrial Military[3] Ambient Temperature[2] 0C to +70C 40C to +85C 55C to +125C Junction Temperature 0C to +90C 40C to +105C 55C to +130C VCC[10] 3.3V 0.3V 3.3V 0.3V 3.3V 0.3V
Min. 2.4
Max.
Unit V
V V V A A mA A A
Guaranteed Input Logical HIGH Voltage for all Inputs[7] Guaranteed Input Logical LOW Voltage for all Inputs[7] VI = GND OR VCC, Bus-Hold Disabled VO = GND or VCC, Output Disabled, Bus-Hold Disabled VCC = Max., VOUT = 0.5V
Input Bus-Hold LOW Sustaining Current VCC = Min., VIL = 0.8V Input Bus-Hold HIGH Sustaining Current VCC = Min., VIH = 2.0V Input Bus-Hold LOW Overdrive Current VCC = Max.
+500
A A
Input Bus-Hold HIGH Overdrive Current VCC = Max. 500 Notes: 9. Dual pins are I/O with JTAG pins. 10. For CY37064VP100-143AC, CY37064VP100-143BBC, CY37064VP44-143AC, CY37064VP48-143BAC; Operating Range: VCC is 3.3V 0.16V. Document #: 38-03007 Rev. *E
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Capacitance[5]
Parameter CI/O CCLK CDP Description Input/Output Capacitance Clock Signal Capacitance Dual Functional Pins
[9]
Test Conditions VIN = 3.3V at f = 1 MHz at TA = 25C VIN = 3.3V at f = 1 MHz at TA = 25C VIN = 3.3V at f = 1 MHz at TA = 25C
Max. 8 12 16
Unit pF pF pF
Endurance Characteristics[5]
Parameter N Description Minimum Reprogramming Cycles Test Conditions Normal Programming Conditions
[2]
Min. 1,000
Typ. 10,000
Unit Cycles
AC Characteristics
5.0V AC Test Loads and Waveforms
5V OUTPUT 35 pF INCLUDING JIG AND SCOPE Equivalent to: 238 (COM'L) 319 (MIL) 238 (COM'L) 319 (MIL) 5V OUTPUT 5 pF INCLUDING JIG AND SCOPE (b) 3.0V 170 (COM'L) GND 236 (MIL) <2 ns ALL INPUT PULSES 90% 10% 90% 10% <2 ns
(a)
(c)
THVENIN EQUIVALENT 99 (COM'L) 136 (MIL) 2.08V (COM'L) OUTPUT 2.13V (MIL) 5 OR 35 pF
(c)
THVENIN EQUIVALENT 158 (COML) 270 (MIL) 1.77V (COM'L) 1.77V (MIL) 5 OR 35 pF
OUTPUT
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VOH
tER(+) 2.6V
0.5V
VX VX
VOL
tEA(+) 1.5V
0.5V
VX
tEA() Vthe
0.5V
VOH
VX
0.5V
VOL
Description Input to Combinatorial Output Input to Output Through Transparent Input or Output Latch Input to Output Through Transparent Input and Output Latches Input to Output Enable Input to Output Disable Clock or Latch Enable Input LOW Time[8] Clock or Latch Enable Input HIGH Time[8] Input Register or Latch Set-up Time Input Register or Latch Hold Time Input Register Clock or Latch Enable to Combinatorial Output Input Register Clock or Latch Enable to Output Through Transparent Output Latch Synchronous Clock (CLK0, CLK1, CLK2, or CLK3) or Latch Enable to Output Set-Up Time from Input to Sync. Clk (CLK0, CLK1, CLK2, or CLK3) or Latch Enable Register or Latch Data Hold Time Output Synchronous Clock (CLK0, CLK1, CLK2, or CLK3) or Latch Enable to Combinatorial Output Delay (Through Logic Array) Output Synchronous Clock (CLK0, CLK1, CLK2, or CLK3) or Latch Enable to Output Synchronous Clock (CLK0, CLK1, CLK2, or CLK3) or Latch Enable (Through Logic Array) Set-Up Time from Input Through Transparent Latch to Output Register Synchronous Clock (CLK0 CLK1, CLK2, or CLK3) or Latch Enable Hold Time for Input Through Transparent Latch from Output Register Synchronous Clock (CLK0, CLK1, CLK2, or CLK3) or Latch Enable
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
tEA[13, 14, 15] tER[11, 13] tWL tWH tIS tIH tICO[13, 14, 15] tICOL[13, 14, 15] tCO[14, 15] tS[13] tH tCO2
[13, 14, 15]
Notes: 11. tER measured with 5-pF AC Test Load and tEA measured with 35-pF AC Test Load. 12. All AC parameters are measured with two outputs switching and 35-pF AC Test Load. 13. Logic Blocks operating in Low-Power Mode, add tLP to this spec. 14. Outputs using Slow Output Slew Rate, add tSLEW to this spec. 15. When VCCO = 3.3V, add t3.3IO to this spec.
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Description Product Term Clock or Latch Enable (PTCLK) to Output Set-Up Time from Input to Product Term Clock or Latch Enable (PTCLK) Register or Latch Data Hold Time Set-Up Time for Buried Register used as an Input Register from Input to Product Term Clock or Latch Enable (PTCLK) Buried Register Used as an Input Register or Latch Data Hold Time Product Term Clock or Latch Enable (PTCLK) to Output Delay (Through Logic Array) Input Register Synchronous Clock (CLK0, CLK1, CLK2, or CLK3) to Output Register Synchronous Clock (CLK0, CLK1, CLK2, or CLK3) Maximum Frequency with Internal Feedback (Lesser of 1/tSCS, 1/(tS + tH), or 1/tCO)[5] Maximum Frequency Data Path in Output Registered/Latched Mode (Lesser of 1/(tWL + tWH), 1/(tS + tH), or 1/tCO)[5] Maximum Frequency with External Feedback (Lesser of 1/(tCO + tS) or 1/(tWL + tWH)[5] Maximum Frequency in Pipelined Mode (Lesser of 1/(tCO + tIS), 1/tICS, 1/(tWL + tWH), 1/(tIS + tIH), or 1/tSCS)[5] Asynchronous Reset Width[5] Asynchronous Reset Recovery Time[5] Asynchronous Reset to Output Asynchronous Preset Width[5] Asynchronous Preset Recovery Asynchronous Preset to Output Low Power Adder Slow Output Slew Rate Adder 3.3V I/O Mode Timing Adder[5] Set-up Time from TDI and TMS to TCK[5] Hold Time on TDI and TMS[5]
[5]
Unit ns ns ns ns ns ns ns
Operating Frequency Parameters fMAX1 fMAX2 fMAX3 fMAX4 MHz MHz MHz MHz
ns ns ns ns Time[5] ns ns ns ns ns ns ns ns ns
tPO[13, 14, 15] tLP tSLEW t3.3IO tS JTAG tH JTAG tCO JTAG fJTAG
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Combinatorial Mode Parameters 6 11 12 8 8 2.5 2.5 2 2 11 12 4 4 0 9.5 5 7.5 0 7 2.5 2.5 0 6 12 2.5 2.5 0 6.5 14 6 7.5 0 10 2.5 2.5 0 6.5 15 4 0 10 6.5 8.5 0 10 3 3 0 7.5 19 2.5 2.5 2 2 11 12 4 5 0 11 7 9 0 13 5 5 0 9 19 6.5 12.5 13.5 8.5 8.5 2.5 2.5 2 2 11 12 4.5 5 0 12 8[16] 10 0 13 5.5 5.5 0 11 21 7.5 14.5 15.5 11 11 2.5 2.5 2 2 12.5 14 6 5.5[16] 0 14 10 12 0 13 6 6 0 14 24 8.5 16 17 13 13 3 3 2 2 12.5 16 6.5[16] 6[17] 0 16 12 15 0 15 10 16.5 17.5 14 14 3 3 2.5 2.5 16 18 6.5[17] 8[18] 0 19 12 17 18 16 16 4 4 3 3 19 21 8[18] 15 19 20 19 19
Pipelined Mode Parameters tICS[13] fMAX1 fMAX2 fMAX3 fMAX4 tRW 5 200 200 125 167 8 6 167 200 125 167 8 6 154 200 105 154 8 7 143 167 91 125 8 8[16] 125[16] 154 83 118 10 10 100 153[17] 80[17] 100 12 12 83 125[18] 62.5 83 15 15 66 100 50 66 20 ns MHz MHz MHz MHz ns Operating Frequency Parameters
Reset/Preset Parameters tRR[13] 10 10 10 10 12 14 17 22 ns Notes: 16. The following values correspond to the CY37512 and CY37384 devices: tCO = 5 ns, tS = 6.5 ns, tSCS = 8.5 ns, tICS = 8.5 ns, fMAX1 = 118 MHz. 17. The following values correspond to the CY37192V and CY37256V devices: tCO = 6 ns, tS = 7 ns, fMAX2 = 143 MHz, fMAX3 = 77 MHz, and fMAX4 = 100 MHz; and for the CY37512 devices: tS = 7 ns. 18. The following values correspond to the CY37512V and CY37384V devices: tCO = 6.5 ns, tS = 9.5 ns, and fMAX2 = 105 MHz.
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12 8 10
13 8 10 13 2.5 3 0.3 0 20
13 8 10 13 2.5 3 0.3 0 20 20 20
14 10 12 14 2.5 3 0.3 0 20 20 20
15 12 14 15 2.5 3 0.3 0 20 20 20
18 15 17 18 2.5 3 0.3
21
Switching Waveforms
Combinatorial Output
INPUT tPD COMBINATORIAL OUTPUT
tWL
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Registered Output with Product Term Clocking Input Coming From Adjacent Buried Register
INPUT tISPT PRODUCT TERM CLOCK tCO2PT REGISTERED OUTPUT tIHPT
Latched Output
INPUT tSL LATCH ENABLE tPDL LATCHED OUTPUT tCO tHL
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tWH CLOCK
tWL
Clock to Clock
INPUT REGISTER CLOCK tICS OUTPUT REGISTER CLOCK tSCS
Latched Input
LATCHED INPUT tIS LATCH ENABLE tPDL COMBINATORIAL OUTPUT tICO tIH
tWL
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tHL
Asynchronous Reset
tRW INPUT tRO REGISTERED OUTPUT tRR CLOCK
Asynchronous Preset
tPW INPUT tPO REGISTERED OUTPUT tPR CLOCK
Output Enable/Disable
INPUT tER OUTPUTS tEA
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H ig h S p e e d
50
40
20
10
F re q u e n c y (M H z )
CY37064
90
The typical pattern is a 16-bit up counter, per logic block, with outputs disabled. VCC = 5.0V, TA = Room Temperature
80
H ig h S p e e d
70
60
Icc (mA)
50
Low Power
40
30
20
10
F re q u e n c y (M H z )
The typical pattern is a 16-bit up counter, per logic block, with outputs disabled. VCC = 5.0V, TA = Room Temperature
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140
H ig h S p e e d
120
100
Icc (mA)
Low Power
80
60
40
20
F re q u e n c y (M H z )
The typical pattern is a 16-bit up counter, per logic block, with outputs disabled. VCC = 5.0V, TA = Room Temperature
CY37192
300
250
H ig h S p e e d
200
Icc (mA)
150
Low Power
100
50
F re q u e n c y (M H z )
The typical pattern is a 16-bit up counter, per logic block, with outputs disabled. VCC = 5.0V, TA = Room Temperature
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H ig h S p e e d
250
200
100
50
F re q u e n c y (M H z )
The typical pattern is a 16-bit up counter, per logic block, with outputs disabled. VCC = 5.0V, TA = Room Temperature
CY37384
500
450
H ig h S p e e d
400
350
300
Icc (mA)
250
Low Power
200
150
100
50
F re q u e n c y (M H z )
The typical pattern is a 16-bit up counter, per logic block, with outputs disabled. VCC = 5.0V, TA = Room Temperature
Page 26 of 64
[+] Feedback
H ig h S p e e d
500
400
Icc (mA)
300
Low Power
200
100
F re q u e n c y (M H z )
The typical pattern is a 16-bit up counter, per logic block, with outputs disabled. VCC = 5.0V, TA = Room Temperature
H igh S p ee d
25
L ow P o w er
20
Icc (mA)
15
10
F re qu e n cy (M H z)
The typical pattern is a 16-bit up counter, per logic block, with outputs disabled. VCC = 3.3V, TA = Room Temperature
Page 27 of 64
[+] Feedback
H ig h S p e e d
40
35
30
Low Power
Icc (mA)
25
20
15
10
F re q u e n c y (M H z )
The typical pattern is a 16-bit up counter, per logic block, with outputs disabled. VCC = 3.3V, TA = Room Temperature
CY37128V
80
H ig h S p e e d
70
60
50
Low Power
Icc (mA)
40
30
20
10
F r e q u e n c y (M H z )
The typical pattern is a 16-bit up counter, per logic block, with outputs disabled. VCC = 3.3V, TA = Room Temperature
Page 28 of 64
[+] Feedback
H ig h S p e e d
100
80
60
40
20
0 0 20 40 60 80 100 120
F re q u e n c y (M H z )
The typical pattern is a 16-bit up counter, per logic block, with outputs disabled. VCC = 3.3V, TA = Room Temperature
CY37256V
140
120
H ig h S p e e d
100
60
40
20
0 0 20 40 60 80 100 120
F re q u e n c y (M H z )
The typical pattern is a 16-bit up counter, per logic block, with outputs disabled. VCC = 3.3V, TA = Room Temperature
Page 29 of 64
[+] Feedback
H ig h S p e e d
160
140
120
Low Power
Icc (mA)
100
80
60
40
20
0 0 10 20 30 40 50 60 70 80 90
F r e q u e n c y (M H z )
The typical pattern is a 16-bit up counter, per logic block, with outputs disabled. VCC = 3.3V, TA = Room Temperature
CY37512V
250
200
H ig h S p e e d
150
Low Power
Icc (mA)
100 50 0 0 10 20 30 40 50 60 70 80 90
F re q u e n c y (M H z )
The typical pattern is a 16-bit up counter, per logic block, with outputs disabled. VCC = 3.3V, TA = Room Temperature
Page 30 of 64
[+] Feedback
I/O5/TCK I/O6 I/O 7 CLK2/I0 JTAGEN GND CLK0/I 1 I/O8 I/O9 I/O10 I/O11
I/O27 /TDI I/O26 I/O25 I/O24 CLK1/I 4 GND I3 CLK3/I2 I/O23 I/O22 I/O21
I/O 5/TCK I/O6 I/O7 CLK2/I0 JTAGEN GND CLK0/I 1 I/O8 I/O9 I/O10 I/O 11
7 8 9 10 11 12 13 14 15 16 17
39 38 37 36 35 34 33 32 31 30 29 18 19 20 21 22 23 24 25 26 27 28 I/O12 I/O /TMS 13 I/O14 I/O15 I/O19 /TDO I/O20 VCC GND I/O16 I/O17 I/O18
I/O 4 I/O 3
6 5 4 3 2 1 44 43 42 41 40
I/O 2
Page 31 of 64
[+] Feedback
VCC
I/O3
I/O1
I/O31
I/O30
VCC
I/O4
I/O2
I/O0
I/O29
I/O28
I/O26
CLK2/ I0
I/O7
I/O6
GND
GND
I/O25
I/O24
I3
JTAGEN
I/O8
I/O9
GND
GND
I/O22
I/O23
CLK3/ I2
CLK0/ I1
I/O12
I/O11
I/O10
I/O16
I/O20
I/O21
VCC
I/O13 TMS
VCC
I/O14
I/O15
I/O17
I/O18
VCC
I/O19 TDO
11 10 I/O 8 I/O 9 I/O /TCK 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 CLK0/I 0 VCCO GND CLK1/I 1 I/O16 I/O 17 I/O 18 I/O 19 I/O 20 I/O 21 I/O 22 I/O 23 GND 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
1 84 83 82 81 80 79 78 77 76
[21]
/TDO I/O 38
32
33
34
35
36
37
I/O 24
I/O 25
VCCO
Note: 21. This pin is a N/C, but Cypress recommends that you connect it to VCC to ensure future compatibility.
I/O
VCC
I/O 39
GND
I/O
I/O
I/O
I/O
I/O
I/O
Page 32 of 64
[+] Feedback
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 TCK GND I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 CLK0 /I 0 VCCO N/C GND CLK 1 /I 1 I/O16 I/O17 I/O18 I/O19 I/O20 I/O21 I/O22 I/O23 VCCO NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 TDI VCCO I/O 55 I/O 54 I/O 53 I/O 52 I/O 51 I/O 50 I/O 49 I/O 48 CLK 3 /I 4 GND NC VCCO CLK 2 /I 3 I/ O47 I/O 46 I/O 45 I/O 44 I/O 43 I/O 42 I/O 41 I/O 40 GND NC
TMS
I/O 24 I/O 25
I/O 26 I/O 27
I/O 28 I/O 29
I/O 30 I/O 31
I/O 33 I/O 34
I/O 38 I/O 39
GND
I2 VCCO
GND
VCCO
TDO
NC
Page 33 of 64
[+] Feedback
3 I/O8 I/O7 VCC I/O15 I/O18 I/O21 I/O26 VCC I/O35 I/O34
4 I/O6 I/O5 I/O4 I/O16 I/O19 I/O20 I/O24 I/O25 VCC I/O36
5 I/O3 I/O2 I/O1 I/O0 GND GND I/O23 I/O39 I/O38 I/O37
6 I/O76 I/O77 I/O78 I/O79 GND GND I/O56 I/O40 I/O41 I/O42
7 I/O74 VCC I/O75 I/O63 I/O60 I/O59 I/O55 I/O52 I/O43 I/O44
8 I/O72 I/O73 VCC I/O64 I/O61 I/O58 I/O54 VCC I/O45 I/O46
9 I/O71 I/O68 I/O67 TDI CLK3/ I4 CLK2/ I3 I2 NC I/O47 TDO I/O48 I/O49
Page 34 of 64
[+] Feedback
120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
VCCO I/O111 I/O110 I/O109 I/O108 /TDI I/O107 I/O106 I/O105 I/O104 GND I/O103 I/O102 I/O101 I/O100 I/O99 I/O98 I/O97 I/O96 CLK3/I4 GND VCCO CLK2/I3 I/O95 I/O94 I/O93 I/O92 I/O91 I/O90 I/O89 I/O88 GND I/O87 I/O86 I/O85 I/O84 I/O83 I/O82 I/O81 I/O80 GND
GND I/O48 I/O49 I/O50 I/O51 I/O52/TMS I/O53 I/O54 I/O55 GND I/O56 I/O57 I/O58 I/O59 I/O60 I/O61 I/O62 I/O63 I2 VCCO GND VCC I/O64 I/O65 I/O66 I/O67 I/O68 I/O69 I/O70 I/O71 GND I/O72 I/O73 I/O74 I/O75 I/O76/TDO I/O77 I/O78 I/O79 VCCO
Page 35 of 64
[+] Feedback
GND NC I/O16 I/O17 I/O18 TCK I/O19 I/O20 I/O21 GND I/O22 I/O23 I/O24 I/O25 I/O26 I/O27 I/O28 I/O29 CLK0/I0 VCCO GND CLK1/I1 I/O30 I/O31 I/O32 I/O33 I/O34 I/O35 I/O36 I/O37 GND I/O38 I/O39 I/O40 I/O41 I/O42 I/O43 I/O44 I/O45 VCCO
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80
160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121
VCCO I/O15 I/O14 I/O13 I/O12 I/O11 I/O10 I/O9 I/O8 GND I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 VCCO GND VCC NC I/O119 I/O118 I/O117 I/O116 I/O115 I/O114 I/O113 I/O112 GND I/O111 I/O110 I/O109 I/O108 I/O107 I/O106 I/O105 NC GND
120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
VCCO I/O104 I/O103 I/O102 TDI I/O101 I/O100 I/O99 I/O98 GND I/O97 I/O96 I/O95 I/O94 I/O93 I/O92 I/O91 I/O90 CLK3/I4 GND VCCO CLK2/I3 I/O89 I/O88 I/O87 I/O86 I/O85 I/O84 I/O83 I/O82 GND I/O81 I/O80 I/O79 I/O78 I/O77 I/O76 I/O75 NC GND
TMS I/O49 I/O50 I/O51 GND I/O52 I/O53 I/O54 I/O55 I/O56 I/O57 I/O58 I/O59 I2 VCCO GND VCC I/O60 I/O61 I/O62 I/O63 I/O64 I/O65 I/O66 I/O67 GND I/O68 I/O69 I/O70 I/O71
Page 36 of 64
[+] Feedback
208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157
VCC VCC0 I/O19 I/O18 I/O17 I/O16 I/O15 NC I/O14 I/O13 I/O12 I/O11 I/O10 GND I/O9 I/O8 I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 VCC0 GND VCC NC I/O159 I/O158 I/O157 I/O156 I/O155 NC I/O154 I/O153 I/O152 I/O151 I/O150 GND I/O149 I/O148 I/O147 I/O146 I/O145 I/O144 I/O143 I/O142 I/O141 I/O140 NC GND 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105
GND I/O60 I/O61 I/O62 I/O63 I/O64 TMS I/O65 I/O66 I/O67 I/O68 I/O69 GND I/O70 I/O71 I/O72 I/O73 I/O74 NC I/O75 I/O76 I/O77 I/O78 I/O79 I2 VCC0 GND VCC I/O80 I/O81 I/O82 I/O83 I/O84 I/O85 I/O86 I/O87 I/O88 I/O89 GND I/O90 I/O91 I/O92 I/O93 I/O94 GND TDO I/O95 I/O96 I/O97 I/O98 I/O99 VCC0
GND I/O20 I/O21 I/O22 I/O23 I/O24 TCK I/O25 I/O26 I/O27 I/O28 I/O29 GND I/O30 I/O31 I/O32 I/O33 I/O34 NC I/O35 I/O36 I/O37 I/O38 I/O39 CLK0/I0 VCCO GND NC CLK1/I1 I/O40 I/O41 I/O42 I/O43 I/O44 I/O45 I/O46 I/O47 I/O48 I/O49 GND I/O50 I/O51 I/O52 I/O53 I/O54 NC I/O55 I/O56 I/O57 I/O58 I/O59 VCC0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52
VCCO I/O139 I/O138 I/O137 I/O136 I/O135 TDI I/O134 I/O133 I/O132 I/O131 I/O130 GND I/O129 I/O128 I/O127 I/O126 I/O125 I/O124 I/O123 I/O122 I/O121 I/O120 CLK3/I4 VCC GND VCCO GND CLK2/I3 I/O119 I/O118 I/O117 I/O116 I/O115 NC I/O114 I/O113 I/O112 I/O111 I/O110 GND I/O109 I/O108 I/O107 I/O106 I/O105 I/O104 I/O103 I/O102 I/O101 I/O100 GND
Page 37 of 64
[+] Feedback
GND
I/O21
NC
I/O16
I/O12
I/O9
I/O7
I/O4
I/O0
I/O190
I/O189
I/O186
I/O182
NC
I/O178
I/O175
NC
NC
I/O169
I/O168
I/O23
I/O20
I/O19
I/O18
I/O15
I/O11
I/O8
I/O5
I/O1
I/O191
I/O187
I/O185
I/O181
NC
NC
I/O174
I/O171
I/O170
NC
I/O166
NC
NC
I/O22
NC
I/O17
I/O14
I/O10
I/O6
I/O2
NC
I/O188
I/O184
I/O180
I/O179
I/O176
I/O173
I/O172
I/O167
I/O165
I/O162
I/O24
NC
NC
GND
NC
VCCO
I/O13
GND
I/O3
NC
VCC
I/O183
GND
I/O177
VCCO
NC
GND
I/O164
TDI
I/O160
I/O27
I/O26
I/O25
NC
I/O163
I/O161
I/O159
I/O156
I/O30
TCK
I/O28
VCCO
VCCO
I/O158
NC
I/O154
I/O33
I/O32
I/O31
I/O29
I/O157
I/O155
I/O153
I/O152
I/O35
NC
I/O34
GND
GND
GND
GND
GND
GND
GND
GND
I/O151
I/O150
I/O149
I/O39
I/O38
I/O37
I/O36
GND
GND
GND
GND
GND
GND
I/O148
I/O147
I/O146
I/O145
I/O42
I/O40
I/O41
VCC
GND
GND
GND
GND
GND
GND
I/O144 CLK3/I4
NC
NC
I/O43
I/O44
I/O45
I/O46
GND
GND
GND
GND
GND
GND
VCC
CLK2/I3 I/O143
NC
I/O47
CLK0/I0 CLK1/I1
I/O48
GND
GND
GND
GND
GND
GND
I/O139
I/O140
I/O141
I/O142
I/O49
I/O50
I/O51
GND
GND
GND
GND
GND
GND
GND
GND
I/O136
I/O137
I/O138
I/O52
I/O53
I/O55
I/O58
I/O131
I/O133
I/O134
I/O135
I/O54
I/O56
I/O59
VCCO
VCCO
I/O130
NC
I/O132
I/O57
I/O60
I/O62
I/O65
I/O124
I/O127
I/O128
I/O129
I/O61
I/O63
I/O66
GND
I/O76
VCCO
I/O82
GND
I/O91
VCC
I/O98
I/O102
GND
I/O112
VCCO
NC
GND
I/O123
I/O122
I/O126
I/O64
I/O67
I/O69
I/O75
I/O78
I/O81
I/O85
I/O88
I/O92
I2
I/O97
I/O101
I/O105
I/O109
I/O113
TDO
I/O114
I/O117
I/O121
I/O125
I/O68
I/O70
I/O72
I/O74
I/O79
I/O83
I/O86
I/O89
I/O93
I/O95
I/O96
I/O100
I/O104
I/O107
I/O110
NC
NC
I/O115
I/O118
I/O120
I/O71
I/O73
I/O77
TMS
I/O80
I/O84
I/O87
I/O90
I/O94
NC
NC
I/O99
I/O103
I/O106
I/O108
I/O111
NC
NC
I/O116
I/O119
10
11
12
13
14
15
16
17
18
19
20
Page 38 of 64
[+] Feedback
GND
I/O27
I/O25
I/O23
I/O19
I/O15
I/O10
GND
GND
I/O185
I/O181
I/O176
I/O171
I/O166
I/O165
GND
I/O29
I/O28
NC
I/O22
I/O18
I/O14
I/O9
I/O4
I/O191
I/O184
I/O180
I/O175
I/O170
NC
I/O163
I/O164
I/O32
I/O31
I/O30
NC
I/O17
I/O13
I/O8
I/O3
I/O190
I/O183
I/O179
I/O174
I/O169
I/O160
I/O161
I/O162
I/O35
I/O34
I/O33
I/O21
I/O16
I/O12
I/O7
I/O2
I/O189
VCC
I/O178
I/O173
I/O168
I/O157
I/O158
I/O159
VCC
I/O38
I/O37
I/O36
TCK
VCC
I/O6
I/O1
I/O188
I/O182
VCC
TDI
I/O154
I/O155
I/O156
VCC
I/O43
I/O42
I/O41
I/O40
VCC
I/O39
I/O5
I/O0
I/O187
I/O148
I/O149
I/O150
I/O151
I/O152
I/O153
GND
GND
I/O47
I/O46
CLK0 /I0 NC
I/O45
I/O44
GND
GND
I/O144
I/O145
I/O146
I/O147
GND
GND
GND
GND
I/O51
I/O50
I/O49
I/O48
GND
GND
I/O140
I/O141
I/O142
I/O143
GND
GND
I/O57
I/O56
I/O55
I/O54
I/O53
I/O52
I/O91
I/O96
I/O101
I/O135
VCC
I/O136
I/O137
I/O138
I/O139
VCC
I/O60
I/O59
I/O58
VCC
I/O86
I/O92
I/O97
I/O102
VCC
TDO
I/O132
I/O133
I/O134
VCC
I/O63
I/O62
I/O61
I/O72
I/O77
I/O82
VCC
I/O93
I/O98
I/O103
I/O108
I/O112
I/O117
I/O129
I/O130
I/O131
I/O66
I/O65
I/O64
I/O73
I/O78
I/O83
I/O87
I/O94
I/O99
I/O104
I/O109
I/O113
NC
I/O126
I/O127
I/O128
I/O68
I/O67
NC
I/O74
I/O79
I/O84
I/O88
I/O95
I/O100
I/O105
I/O110
I/O114
I/O118
NC
I/O124
I/O125
GND
I/O69
I/O70
I/O75
I/O80
I/O85
I/O89
GND
GND
I/O106
I/O111
I/O115
I/O119
I/O121
I/O123
GND
GND
GND
I/O71
I/O76
I/O81
VCC
I/O90
GND
GND
I/O107
VCC
I/O116
I/O120
I/O122
GND
GND
Page 39 of 64
[+] Feedback
GND GND I/O19 I/O15 I/O13 I/O34 I/O31 I/O28 I/O25 I/O10 GND NC I/O18 I/O17 I/O14 I/O35 I/O32 I/O29 I/O26 I/O11 I/O9 NC
I/O1 I/O263 I/O260 I/O257 I/O254 I/O239 I/O237 I/O232 I/O229 I/O250 I/O248 I/O244 GND GND I/O2 VCC I/O261 I/O258 I/O255 I/O252 I/O234 I/O231 I/O228 I/O249 I/O246 I/O245 I/O240 GND
I/O23 I/O38 I/O37 I/O16 I/O12 I/O33 I/O30 I/O27 I/O24 I/O39 I/O40 I/O36 I/O42 TCK I/O41 NC NC NC I/O21 I/O20 VCCO VCCO
I/O0 I/O262 I/O259 I/O256 I/O253 I/O238 I/O235 I/O233 I/O230 I/O251 I/O247 I/O225 I/O224 I/O227 NC VCCO VCCO I/O236 I/O243 NC NC NC I/O226 I/O222 I/O223 TDI I/O221 I/O220
I/O45 I/O44 I/O43 I/O22 I/O48 I/O47 I/O46 I/O63 I/O49 I/O50 I/O51 VCCO I/O52 I/O53 I/O54 VCCO I/O55 I/O56 I/O57 I0 NC GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND
I/O242 I/O219 I/O218 I/O217 I/O241 I/O216 I/O215 I/O214 VCCO I/O211 I/O212 I/O213 VCCO I/O208 I/O209 I/O210 NC I/O205 I/O206 I/O207 I4 I/O197
I/O203 I/O202
I/O62 VCCO
VCCO I/O201 I/O200 I/O199 VCCO I/O196 VCC I/O198 GND I/O193 I/O194 I/O195 GND I/O178 I/O179 I/O192 NC I/O177 I/O176 I/O175
I/O65 I/O66 I/O67 VCCO I/O68 I/O69 I/O70 GND I/O71 I/O84 I/O85 GND I/O88 I/O87 I/O86 NC
I/O91 I/O90 I/O89 VCCO I/O94 I/O93 I/O92 VCCO I/O95 I/O72 I/O73 I/O110 I/O74 I/O75 I/O76 I/O111 I/O77 I/O78 I/O79 N/C NC I/O112 I/O113 VCCO VCCO NC GND GND VCCO VCCO GND GND I2 NC VCCO VCCO I/O150 I/O151 NC
VCCO I/O174 I/O173 I/O172 VCCO I/O171 I/O170 I/O169 I/O153 I/O190 I/O191 I/O168 I/O152 I/O187 I/O188 I/O189 NC NC I/O184 I/O185 I/O186 I/O155 I/O183 I/O182
AD I/O109 I/O82 I/O83 I/O117 I/O97 I/O100 I/O102 I/O105 I/O120 I/O123 I/O126 I/O129 AE AF GND NC
I/O133 I/O136 I/O139 I/O142 I/O157 I/O159 I/O161 I/O163 I/O166 I/O146 I/O180 I/O181 I/O154 NC GND
I/O115 I/O116 I/O119 I/O98 I/O101 I/O103 I/O106 I/O121 I/O124 I/O127 VCC I/O130 I/O134 I/O137 I/O140 I/O143 I/O160 I/O162 I/O165 I/O144 I/O147 I/O148
GND GND I/O114 I/O118 I/O96 I/O99 TMS I/O104 I/O107 I/O122 I/O125 I/O128 I/O131 I/O132 I/O135 I/O138 I/O141 I/O156 I/O158 TDO I/O164 I/O167 I/O145 I/O149 GND GND
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GND
GND
GND
GND
GND
GND
GND
GND
NC
GND
GND
GND
GND
GND
GND
GND
GND
NC
NC
GND
GND
GND
I/O254 I/O235
I/O243
GND
NC
I/O263 I/O253 I/O234 I/O262 I/O252 I/O249 I/O261 VCC I/O246 VCC
I/O241 I/O242 I/O225 I/O240 I/O222 I/O223 I/O212 I/O213 I/O214 I/O211 VCC VCC
I/O40 I/O39 I/O48 I/O55 I/O65 I/O69 I/O85 I/O90 I/O75 I/O77 NC
I/O247 I/O220 I/O221 I/O217 I/O218 I/O219 TDI I/O216 I/O210 I/O204 I/O205 I/O200 I/O201 I/O196 I/O197 I/O174 I/O175 I/O180 I/O168
I/O38 I/O36 I/O54 I/O64 I/O68 I/O84 I/O72 I/O74 I/O76 I/O116 I/O119 I/O96 I/O99
I/O259 I/O260
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
I/O126
I/O134 I/O137 I/O163 I/O135 I/O138 I/O164 I/O136 I/O139 I/O156 GND I/O140 I/O157 I/O141 I/O142 I/O143 VCC VCC VCC
I/O170 I/O171 I/O172 I/O185 I/O186 I/O189 I/O154 I/O155 I/O187 I/O153 GND GND NC
I/O120 I/O130
I/O102 I/O121 I/O131 I/O103 I/O122 VCC VCC VCC I/O123 I/O124 I/O125 GND
I/O166 I/O167
GND
GND
GND
GND
GND
GND
GND
GND
GND
NC
GND
GND
NC
GND
GND
GND
GND
GND
NC
I/O98
I/O100 I/O101
GND
GND
I/O149
NC
GND
GND
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51-85064-*B
51-85003-*A
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51-80014-**
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51-85109-*C
51-85006-*A
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51-80095-*A
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51-85048-*B
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51-85107-*B
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51-85049-*B
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0-7 28.00 0.10 (1.102 .004) SQ. 31.20 0.25 (1.228 .010) SQ.
DETAIL A
SEATING PLANE
0.050(.002) 0.500(.020)
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51-85069-*B
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PIN 1
0.20(.008) TYP.
R 0.13(.005) MIN.
0-7 28.00 0.10 (1.102 .008) SQ. 31.22 0.25 (1.229 .010) SQ.
0 MIN.
DETAIL A
SEE DETAIL A 3.43(.135) 3.94(.155) SEATING PLANE 0.15 0.02 (.006 .001)
0.050(.002) 0.500(.020)
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TOP VIEW
0.05 M C 0.25 M C A B
BOTTOM VIEW
PIN 1 CORNER
9 8 7 6 5 4 3 2 1 A B C
+0.10 -0.05
1.00
D E F G
D E F G
17.000.10
15.00
H J K L
H J K L
N P R T
7.50
M N P R T
0.25 C
17.000.10
0.20(4X)
A1 0.36
0.56
0.35
51-85108-*F
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51-85097-*B
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51-85103-*C
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51-85111-*A
ViewDraw and SpeedWave are trademarks of ViewLogic. Windows is a registered trademark of Microsoft Corporation. Warp is a registered trademark, and In-System Reprogrammable, ISR, Warp Professional, Warp Enterprise, and Ultra37000 are trademarks, of Cypress Semiconductor Corporation. All product and company names mentioned in this document are the trademarks of their respective holders.
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Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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*D
282709
See ECN
YDT
*E
321635
See ECN
PCX
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