L

Alternate Class AB Amplifier Design

..

This Class AB amplifier (Figure 1) has an integral common emitter bipolar amplifier (see Q4). The CE amplifier replaces the bipolar main amplifier in the previous design, Le. Vs in this circuit is the output of the preamp. This produces a more compact and less expensive design since there are fewer components. For designs with high open circuit gain, the overall voltage gain of the Class AB stage is determined by the feedback resistors R7 (RA) and RS (RB)' So AV = - RB/RAThis audio amplifier has three aspects which need to be explained: (a) the VBE amplifier, (b) bootstrapping for increased gain, (c) feedback for output stability.

page 1 of 14

,/

Va:::

R3 + l:x:Dtstrap oIu::acitor

R5 +
(Rb)

X1

Figure 1. Alternate Class AB Amplifier Schematic page 2 of 14

,.. --

---

Amplifier Features The VBE Multiplier A VBE multiplier, sometimes called an amplified diode, (Figure 2) is used to provide a tunable voltage between the bases of the Darlingtons X1 and X2. The purpose of this voltage is to bias the bases of the two Darlingtons, keeping them in a "slightly" ON state - a quiescent current of about 20 mA is desirable. Tuning is obtained through the use of potentiometer XRV1. The quiescent current minimizes the zero crossing distortion associated with the power stage emitter followers. Since VBE is a function of temperature, 03 should be mounted on the same heat sink as X1 and X2 to minimize voltage drift.
2

3 TQ4

Figure 2. Vbe Multiplier The value of the bias should be about 4 x VBE = 2.8V, enough to forward bias each of the four base-emitter junctions in the pair of Darlingtons. Operation Assume a current I flows down out of node 2. Assume the gain of 03 is high, so

page 3 of 14

Ib3 can be ignored. A current I' = I-lE flows through R1 and R2.
VR1 = 11 R1 VR2 = 11 R2 = R2 VSE3 R1

V(2,3) = VR1+ VR2 = (1 +

:~)VBE3

Thus the voltage drop is a multiple of VBE3' and is not restricted to being an integral multiple. By placing a potentiometer at the base of Q3 we can adjust the bias to accommodate tolerance variations between Darlingtons. A capacitor can be used between nodes 2 and 3 to bypass ac signals so that the VBE multiplier provides a simple dc bias.
Example 1

Design a VBE multiplier to provide a 3.0 V bias. Assume 1=2.5 mA, B = 100, and VBE= 0.7 V.

v = (1+ :~)VBE3
R2 _ V -1 = 3.0V -1 = 3.29 R1 - VSE3 O.7V
Let the resistors have standard values R2 = 3.3 kil, R1 = 1.0 kil. Or we could let R2 be a 2.7 kil fixed resistor and a 1 kil potentiometer in series. This would allow bias adjustment from 2.59 V to 3.29 V. *** 07/15/97 00:36:17 *** Evaluation PSpice (July 1993) ***
DC Simulation of VBE Multiplier

page 4 of 14

****
*Spice

CIRCUIT DESCRIPTION
extraction from McLogic

R2 R1 Q3 14

2 1 2 0

1 3.3k 0 1.0k 1 0 Q2N2222 2 2.5mA

.lib eval.lib

*** 07/15/97 00:36:17 *** Evaluation PSpice (July 1993) ***

DC Simulation of VBE Multiplier

***

BJT MODEL PARAMETERS Q2N2222 NPN 14.340000E-15 255.9 1 74.03 .2847 14.340000E-15 1.307 6.092 1 10 10 1 22.010000E-12 .377 7.306000E-12 .3416 411.100000E-12 3 1.7 .6 46.910000E-09 1.5

IS BF NF VAF IKF ISE NE BR NR RE REM RC CJE MJE CJC MJC TF XTF VTF ITF TR XTB

*** 07/15/97 00:36:17 *** Evaluation PSpice (July 1993) ***

DC Simulation **** SMALL of VBE Multiplier BIAS SOLUTION TEMPERATURE

SIGNAL

= 27.000 DEG C

NODE ( 1)

VOLTAGE 0.6609

NODE ( 2)

VOLTAGE 2.8794

Note that since the 2N2222 transistor does not have the ideal VBE of 0.7 V, the voltage drop across the VBE multiplier is not exactly 3.0V.

page 5 of 14

Note that in Example 1 the calculation produced the ratio of R2 to R1. How do you choose unique values? To get a better feel for the range of appropriate values, look at the ac resistance of the VBE multiplier:

r =-

R2

~ (

+ 1+ -

R2
R1 )

re' where re =

0.025V
le

This can be derived from the ac equivalent circuit of the VBE multiplier.To produce a nearly pure dc voltage drop of a given value you would want R2 small, B large and Ic large. Example 2 Calculate the ac resistance of the VBE multiplier in the previous example. lE =

1-1'= 2.5mA _ tOkQ = t8mA O.7V t8mA

r = O.025V = 13.9Q
e

r = 3.3kQ + 1+ 3.3 13.9 = 33.0Q + 59.8Q = 92.8Q 100 ( to )

Ifthis value of r is too high you could lower R2 (and R1), raise I, or add a capacitor between nodes 2 and 3 with an impedance much less than r at the frequencies of interest.

Bootstrapping [Reference: Transistor Circuit Techniques

- Discrete and integrated, 3rd ed., G.J.

Ritchie, Chapman and Hall, London, 1993] Bootstrapping is a method of increasing the open loop [no feedback] gain of an

page 6 of 14

amplifier. In this amplifier, capacitor C4 is the bootstrap capacitor. The higher the open loop gain, the more accurately the equation AV = - RS/RA will predict the closed loop [with feedback] gain. Consider the circuit below, where 01 is used in a common emitter amplifier and 02 is an emitter follower (common collector amplifier).
Ucc R3 +

Q2

Av

GND

Figure 3. Sootstrapping Example If the ac voltage at the collector of 01 is v, then voltage Avis present at the emitter of 02 and also at the common terminals of R3 and R4, assuming that the impedance of C4 is very small at the frequencies of interest. The gain A of the common emitter amplifier is

A- -

r e2 + R

' where R = RE R3 and R

11

- O.025V
e2

'

Ic2

The voltage across resistor R4 is v- Av= (1 - A) v. So for ac signals, the resistance of R4 appears to be R4' = R4/ (1 - A), which is much

page 7 of 14

higher than R4 since A is typically just slightly less than 1 for the emitter follower. Since R4' is the collector resistance for the common emitter stage, the gain of the CE stage will become

Av = -

R4' Ilrin(fOllower)

r e1

, where rin(follower) r 1t+ (1+ -

A p

)R -

AR
p

Without the bootstrapping, the gain would be

(R3+ R4)
AV = -

11

rin(follower)

ret

a value much less than that seen if C4 is used. Example 3. Bootstrapping Design a CE/CC amplifier pair. Compare the voltage gains with and without bootstrapping. Assumptions and Design Parameters Vcc= 12 V le for each transistor is 2.5 mA B for each transistor is 100 RL = 1 kQ Use 2N2222 for simulations See appendix for detailed component calculations and PSpice files

page 8 of 14

Vc:c:

12V ,

A.+
, 32k<

r
R1 +

r
RC +1. 6k IQ2

VI a::: Vin

91uF Vin

f--16k

Ib1

R2 L+

sin(OV

10mV 1kHz)

Figure 4. Common emitter, common collector amplifiers without bootstrapping. Without bootstrapping (Figure 4), the voltage gain is

(~x RE2) x Av = - RC 11
re1
11

RE2 + re2

RE2

, where rei = Vt = 25mV

Ici Ici

A A

v v

= _ 1.6kQ = -159

10Q

290kQ x

2.9kQ + 10Q

2.9kQ

x 2900 2910

= -158.6

Av(PSpice)

= -129

B x RE2 represents the input resistance of the common collector amplifier, and is the load for the common emitter amp. With bootstrapping (Figure 5), the collector resistor of the common emitter is split into two pieces and the bootstrap capacitor C4 is page 9 of 14

added. The impedance of C4 should be small in the audio frequency band.

Ucc

12U

R1 + 32k <..

<800

IQ2

I+ C4

1000uF N u
+1

b1 R2 + :>
16k

Q2N2222
.e I
I

=t

.
RE2 + <2.9k

Uout

1\

33uF

1t

?in(OU

1mU 1kHz)

Figure 5. Common emitter, common collector amplifiers with bootstrapping. RC was split in half and capacitor C4 added. The amplitude of the sine wave input was reduced in anticipation of higher gain. The voltage gain of the amplifier pair is AV' and the voltage gain of the common collector stage is A.

A v- - _ RC21 rin (follower)

11

r e1

xA

Vt 25mV R where rei = - = , A =, Ici Ici R + r e2 R = RE211 RC1, and rin (follower) = ~R

page 10 of 14

Plug in the component values and solve for the bootstrap gain:

R = RE2

11RC1

= 2. 9kQ 11800Q = 627Q

r e2 =
A =

25mV
2.5mA R

= 10Q

= 627 Q = 0.984

R + r e2

637Q

RC21= RC2 = 800Q = 50kQ 1- A 1- 0.984 A

v

= - 50kQ 1162.7kQ x 0.984

10Q

Av = -2782 x 0.984 = -2737 Av (PSpice) = -1300

While we can show a large increase in gain (factor of nearly 20) from the no bootstrap case, the calculation and simulation do not match. The reason for this is not yet known.

Daoe 11 of 14

Appendix Amplifier Calculations Ic = 2.5 mA, B = 100, RL = 1k.Q,Vcc = 12 V. Let the voltage at the base of 01, VS, be about Vcc/3 or 4 V for good output swing Then at the emitter of 01, VE = 4 - VSE= 3.3 V. Let lE = IC to simplify calculations.

RE1=- VE _ 3.3V = 1.32kQ , E - 2 . 5mA Let the current through the divider consisting of R1 and R2 be about ten times the 01 base current, or about 0.11Ewhen B = 100.

R1+R2 = R2 V

12V = 48kQ O.25mA = 4V

cc

R1+R2

R2 = 4V (R1+R2) = 4V 48kQ = 16kQ 12V V cc R1 = 32kQ

Let the drop across 01's collector resistor be about Vcc/3.

RC=

V cc - Vc _
Ic

- 2.5mA

4V

= 1.6kQ

The dc bias at the base of 02 should be 8 V. The emitter voltage should be 7.3 V.

page 12 of 14

RE2 = 2.5mA

7.3V

= 2.9kQ

PSpice Input Files

CE/CC Amplifier - no 1::xJotstrapping * naninal gain = -160 * Spice extraction fran McLogic Cl 1 b1 91uF C2 e2 Vout 33uF RC Vcc cl 1.6k RE1 e1 0 1.32k RE2 e2 0 2 . 9k vin vin 0 sin(OV lOrnV 1kHz) Vcc Vcc 0 12V Q1 cl b1 e1 Q2N2222 CE e1 0 1000uF R1 Vcc b1 32k R2 b1 0 16k RL Vout 0 1k Q2 Vcc cl e2 Q2N2222 Rs vin 1 100 * Pull the transistor rnoclels fran the eval .lib eval.lib

library

.prote
* Run simulation

.tran

for 2 cycles

200 points

mirllinum

O.02ms 2ms 0 1000

* Show the output voltage

in the dialog J:::oxas sim runs

.watch

.en::1

tran

V( [Vout] )

***************************************************************************************

Eootstrapped CC/CE arrplifier * Naninal gain = -2700 * Spice extraction fran McLogic Cl 1 b1 91uF page 13 of 14

C2 e2 Vout 33uF RC1 Vcc 2 800 RC2 2 cl 800 RE1 e1 0 1.32k vin vin 0 sin (OV lmV 1kHz) Vcc Vcc 0 12V Q1 cl b1 e1 Q2N2222 CE e1 0 1000uF R1 Vcc b1 32k R2 b1 0 16k RL Vout 0 lk Q2 Vcc cl e2 Q2N2222 RE2 e2 0 2 . 9k Rs vin 1 100 C4 2 e2 4000uF * Pull the transistor rncx:1els fran .lib eval.lib

the eval

library

.prote
* Run simulation for 2 cycles, 200 points rninirrn.1m .tran O.02ms 2ms 0 10us * Show the output voltage in the dialog l:Dx as sim nms

.watch
.arl

tran

V ( [Vout] )

oaae 14 of 14