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¾ When the input voltage is zero, both transistors are cut off and the output
voltage is zero.
¾ When the input voltage goes positive and is sufficiently large
(approximately 0.7 V for silicon transistors), Q1 turns on and conducts
current from the +VCC supply to ground through the load resistance. Q1
acts as an emitter-follower and vout=vin-VBE1. During the positive half
cycle of vin, Q2 remains cutoff.
¾ Similarly, when the input voltage goes negative and is less than
approximately –0.7 V, Q2 turns on and conducts current from ground to
the –VCC supply through the load resistance. During the negative half of
the input cycle, Q2 acts as an emitter follower and vout follows vin
(vout=vin+VBE2) and Q1 is cut off.
If the Thevenin equivalent voltage (VBB) resulting from the voltage divider in
the circuit above is equal to VBE, the quiescent collector current is equal to
zero and the amplifier is operating as Class B. However, if VBB > VBE, ICQ > 0
and the amplifier is operating as Class AB. The analysis of either EF stage
(half of the total power amplifier circuit) mirrors the presentation of the EF
(a.k.a. CC) configuration of Section D4, where RE is now zero and the dc
source is VCC/2.
R2
RB = R2 || R2 = .
2
As we mentioned above for the first circuit, analysis or design of the Class
AB half-circuit proceeds as for an EF amplifier.
∆V V2 − V1
Rf = = ,
∆I I 2 − I1
It is also extremely important that the diode bias current be large enough
to keep the diodes forward biased for all possible input voltages. The
maximum negative peak current through the diode under ac operation must
be less than the direct current bias. In other words, when the ac (id) and dc
(ID) portions of current through the diode are added together, the resultant
current (iD) should never go negative, or
where idp is the peak value (positive or negative) of the ac component of the
diode current. If this sum is negative, or ID < |idp|, the diode would be
reverse biased and significant distortion would result.
where the simplification was made by assuming Rf << R2. Note that this is
generally a valid assumption and illustrates why the instantaneous value of
Rf is not absolutely critical in the design process.
v inp v outp
i dp = i bp + i R2 p = i bP + ≅ i bp + , (Equation 8.23)
R2 + Rf R2
where the last equality is derived by assuming Rf<<R2 and that the voltage
gain for the EF amplifier is unity (AV=1, or vout=vin). By equating the dc
diode current (ID) to the peak value of the ac diode current (idp), we may
find the limiting condition for operation in the forward biased diode region
(Equation 8.21) as
From the small signal circuit above, the output voltage may be found by
Similarly, if R2 is defined, the required value for the peak base current may
be calculated by manipulating Equations 8.24 and 8.27:
β ib β (Rf + R2 )R2
Ai = = . (Equation 8.30)
i in (2Rf + R2 + R2 || β RL )(R2 + β RL )
Unlike the Class A amplifier that dissipates maximum power under quiescent
conditions (VCEQICQ), the quiescent power dissipation of transistors in the
Class B stage is zero since ICQ=0. However, the power delivered by the
source is still split between the transistor (average power over a half cycle)
and the resistors of the bias circuitry, with the ac signal source providing an
additional (but usually insignificant) amount of power. The various power
relationships in the circuit are specified as follows:
2
VCC
PVCC = . (Equation 8.33)
2π RL
¾ The total dc power supplied to the Class B stage is the sum of the power
to the transistors and the power to the bias and compensation circuitry:
2 2
VCC VCC
PVCC (total ) = + . (Equation 8.36)
2π RL 2(Rf + R2 )
Note: the above expression was derived for the diode compensated
circuit, but still holds for the circuit of Figure 8.11a if Rf is replaced with
R1. Also, if RC and/or RE is included in the dc bias circuitry, appropriate
modifications must be made to Equation 8.32.
1 ⎛⎜ (VCC / 2)
2
1 ⎛ VCC / 2 ⎞
2
⎞
Pout (ac max) = ⎜⎜ ⎟ RL = ⎟
2 ⎝ RL ⎟⎠ 2 ⎜⎝ RL ⎟
⎠. (Equation 8.35)
2
1 ⎛ V / 2 ⎞ VCC
= VCC ⎜⎜ CC ⎟⎟ =
2 ⎝ RL ⎠ 8RL
To ensure a viable design, it is critical that the power rating of the transistor
is sufficient. Maximizing Equation 8.37 with respect to collector current, we
come up with the criteria for the maximum power of the transistor:
2
VCC
Pmax = . (Equation 8.40)
4π 2 RL