Homework 5. Asynchronous Pulse Mode Analysis (Problem 1 and 2): Problem 1. A. Determine state table B.

Construct a timing diagram that shows the overall response of the circuit. Include x1,x2,x3,y1,y2,Y1,Y2, and z in the timing diagram.

Problem 2. A. Determine state table B. Determine the output response to the input sequence x1-x2-x1-x1-x1-x1-x2-x2 if starting from state 00 C. What form (level or pulse) will an output of z = 1 have? Why?

Problem 3. Design a two input (x1, x2) and a output where an output transition 0 to 1 occurs on the occurrence of the last x2 pulse in the sequence of x1-x2-x1-x2. The output goes back to 0 only after the first x1 pulse following a 0 to 1 transition. No overlapping sequences. Design using SR Latch.

Asynchronous Fundamental Mode Problem 1. Analysis A. Determine the excitation table and output B. Construct flow table C. Use the flow table to determine the output response to the input sequence x1x2: 00-01-11-1000-01-00-10. Assume initially x1=x2=y1=y2=Y1=Y2=0

Problem 2. Primitive flow table design A fundamental mode circuit must be designed to satisfy the following requirements. Two inputs (x1, x2) and one output (z) are required. The output z=0 will always be produced when x1=x2. When x1=0 and x2 changes from 0 to 1, an output z=1 must occurs. When x1=1 and x2 changes from 1 to 0, an output z=1 must occurs. Otherwise, no input change will cause an output change. Determine the primitive flow table. Problem 3. Flow table reduction Reduce the following flow table.
State\x1x2 1 2 3 4 5 6 00 1/0 4/1/4/-/1/01 2/2/1 -/2/2/-/11 -/5/5/-/5/5/10 3/-/3/0 6/6/6/1

Problem 4. Complete Asynchronous Circuit Design A Fundamental mode circuit is to be designed to function as an electronic lock. The lock has two switch inputs (x1 and x2). Design the circuit such that an open signal (z=1) is produced only after the following conditions have been satisfied. A. Begin with x1=x2=0

B. While x2=0, x1 turned on, then off twice. C. While x1 remains off, x2 is turned on to open the lock