IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 25, NO.

8, AUGUST 2010 2045

A High-Power-Factor Single-Stage Single-Switch
Electronic Ballast for Compact Fluorescent Lamps
John C. W. Lam, Member, IEEE, and Praveen K Jain, Fellow, IEEE
AbstractA very high power factor electronic ballast that uses
a single switch in the power circuit is proposed in this paper for
compact uorescent lamps (CFLs). The proposed power circuit is
designed by integrating a SEPIC power factor corrector with a
novel single-switch current-fed resonant inverter. The advantage
of this single-switch electronic ballast is that it greatly simplies
the gate-drive circuit design due to the elimination of isolation de-
vices that are otherwise required in the conventional half-bridge
totem pole conguration. This topology features a reduction of at
least two switches in the power stage compared to conventional
two-stage approach for high-power-factor electronic ballasts. In
addition, the proposed circuit is also able to achieve close-to-unity
power factor by operating the integrated SEPIC power factor cor-
rector in discontinuous conduction mode. The conduction loss of
the switch in the proposed circuit is also signicantly reduced com-
pared to the conventional class-E single-switch resonant inverter.
Experimental results are provided to justify all the theoretical anal-
ysis and highlight the features of the proposed circuit on a 13-W
CFL.
Index TermsCompact uorescent lamps (CFLs), electronic
ballast, power factor correction (PFC).
I. INTRODUCTION
C
OMPACT uorescent lamps (CFLs) were rst introduced
in the early 1990s, and are now gradually replacing con-
ventional incandescent lamps in household and commercial
lighting. The reason for the CFLs increasing popularity is that it
conserves energy, and subsequently, reduces energy cost when
compared to traditional incandescent lamps. Fig. 1 shows the
power consumption comparison between CFLs and different
types of incandescent lamps. From Fig. 1, it is clear that in
order to produce the same amount of light output, CFLs only
consumes one-third of the power an incandescent lamp requires
and that the CFLs lifetime is thousand times that of an incan-
descent lamp [1].
The major difference between uorescent lamps and incan-
descent lamps is that uorescent lamps have negative resistance
characteristics, which means that as the uorescent lamp power
increases, the lamp current increases with a decrease in the lamp
Manuscript received November 4, 2009; revised January 17, 2010. Date of
current version June 25, 2010. This paper is presented in part at the IEEE Power
Electronics Specialists Conference (PESC), Rodes, Greece, June 1519, 2008.
U.S. Patent led on June 13, 2008, Reference no. US61/236036. Recommended
for publication by Associate Editor M. Alonso.
The authors are with the Queens Centre for Energy and Power Electron-
ics Research (ePOWER), Queens University, Kingston, K7 L 3N6, Canada
(e-mail: john.lam@ece.queensu.ca; praveen.jain@ece.queensu.ca).
Color versions of one or more of the gures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identier 10.1109/TPEL.2010.2046426
Fig. 1. Energy consumption curves for different kinds of lamp [1].
voltage. As a result, uorescent lamps cannot be connected di-
rectly to the line, as in the case of incandescent lamps. A lamp
current stabilization element called ballast is required in order to
provide sufcient voltage for proper lamp ignition and to stabi-
lize the lamp current once the lamp arc is established. To provide
a compact and lightweight solution for CFLs, high-frequency
electronic ballasts operating at higher frequency than 25 kHz are
more suitable than magnetic ballasts. By operating at a higher
frequency, the light efcacy can be increased by at least 20%
and advanced dimming control can also be implemented with
great exibility.
To minimize cost and to ensure that a compact electronic bal-
last circuit can be installed at the base of a CFL, commercial
CFLs normally do not include a power factor correction (PFC)
circuit in their electronic ballasts. Fig. 2 is a block diagram of
typical electronic ballast used in a commercial CFL. It consists
of a diode rectier and a self-driven half-bridge parallel resonant
inverter [2][5] with a dc-link capacitor connected in between
to provide the required energy to the lamp. The major drawback
of this type of circuit conguration is the highly distorted line
current drawn at the input. The poor quality of the line current,
when reected back to the utility side, produces a large amount
of unwanted harmonics and results in very poor power factor.
Although, it has been reported in [6] that the high total harmonic
distortion (THD) issue in the line current causes only little con-
cern for the power quality when the CFLs are less than 25% of
0885-8993/$26.00 2010 IEEE
2046 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 25, NO. 8, AUGUST 2010
Fig. 2. Block diagram of electronic ballast in commercial CFL.
a buildings total load, this will become a more severe problem
when a large amount of unnecessary reactive power is produced
from the utility side, if the incandescent lamps are going to be
replaced by CFLs in the near future. This defeats the original
energy-saving purpose offered by CFL.
The use of single-stage inverters in uorescent lightings to re-
duce the size and cost of the power circuit while simultaneously
achieving high power factor at the input have been discussed in
literature [7][11]. A thorough analysis has been given in [7] to
compare the performance of different power factor preregula-
tors that can be integrated with the half-bridge parallel resonant
inverter. A buckboost converter integrated with a current-fed
resonant inverter was proposed in [11] to eliminate the isolation
devices in the MOSFET driver circuit that would have been oth-
erwise needed in the half-bridge inverter case. Compared to the
conventional two-stage congurations, the single-stage inverter
approach allows the reduction of one controller and MOSFET
in the power circuit. However, with the existing single-stage in-
verter approach, two MOSFETs are still required in the power
circuit.
To further reduce the number of MOSFETs required in the
ballast power circuit, single-switch electronic ballasts were re-
ported in [12][17] by using the class-E resonant inverter. These
electronic ballasts use only one switch to simultaneously achieve
PFCwhile providing the lamp current stabilization at the inverter
stage. The advantage of using the class-Eresonant inverter is that
the design complexity of the MOSFET driver circuit is greatly
reduced and the switch has lossless switching characteristic.
But the switch needs to suffer a high voltage stress of about 35
times of the input dc voltage [17]. A modied class-E inverter
was proposed in [18] to improve the high voltage stress issue in
the MOSFET for CFL applications. But the current stress in the
switch was increased to achieve the aforementioned advantage.
The efciency of the circuit is also lower than the conventional
two-stage electronic ballast with boost PFC.
This paper proposes new high-power-factor single-switch
electronic ballast for CFL applications. The proposed circuit
has both lower peak current and voltage stress across the switch
than that of the class-E resonant inverter. Detailed operating
principles and characteristics of the proposed circuit are pro-
vided in this paper. The merits and performance of the circuit
are justied through experimental results. This paper is orga-
nized as follows. Section II provides a detailed description of
the operating principles of the proposed single-switch ballast
circuit. The mathematical analysis of the proposed ballast cir-
cuit, including current and voltage stress analysis on all the
semiconductor devices is discussed. Section III gives a design
example and provides experimental waveforms to highlight the
performance of the circuit. Section IV summarizes the merits of
the proposed work.
II. DESCRIPTIONS AND CHARACTERISTICS
OF PROPOSED CIRCUIT
A. Derivation of Proposed Single-Stage Ballast Circuit
To design a low-cost and small-size high-power-factor elec-
tronic ballast circuit for CFLs, the design objective is to reduce
the number of active components (i.e., diode and MOSFET)
in the power circuit. Since it is not possible to further reduce
the switch count from the active PFC stage perspective, switch
count reduction is performed on the inverter stage. A single-
switch current-fed resonant inverter is proposed by connect-
ing the switch (M
1
) in series with a diode (D
1
), as shown in
Fig. 3(b). The other circuit elements that make up the single-
switch inverter include: an input inductor (L
in
) and a resonant
circuit consists of L
r
and C
r
, and a starting inductor (L
p
). An
advantage of the proposed inverter circuit compared to the class
E resonant inverter is that when the switch is ON, only the input
current (i
in
) will ow through the switch, as illustrated in Fig. 3.
This means that the conduction loss of the MOSFET is signi-
cantly reduced in the proposed design compared to the class-E
resonant inverter. Another advantage of the proposed single-
switch resonant inverter is that the MOSFET voltage stress
is much lower than that of the class-E resonant inverter. The
MOSFET peak voltage of a class-E resonant inverter is approx-
imately 35 times the peak of the input voltage. However, in the
proposed circuit, the voltage across the MOSFET is a function
of both L
in
and C
r
. Hence, by properly designing L
in
and C
r
,
the voltage across the MOSFET can be minimized.
In active PFC, a front-end converter is required to provide
very high power factor at the line input. DCDC converters
such as the boost, buckboost, yback, Cuk, and SEPIC are
all possible options for active PFC. In the proposed design,
the SEPIC converter is chosen for PFC for the following rea-
sons: 1) it does not require a large-size high-voltage dc-link
capacitor, as in the boost PFC case; 2) unlike the discontinuous-
conduction-mode (DCM) operating boost converter, the dc-link
capacitor of the SEPIC converter does not suffer from high
voltage stress in order to achieve high power factor [19]; and
3) the output dc-link voltage polarity is not inverted, as in the
LAM AND JAIN: HIGH-POWER-FACTOR SINGLE-STAGE SINGLE-SWITCH ELECTRONIC BALLAST FOR COMPACT FLUORESCENT LAMPS 2047
Fig. 3. Comparisons between class-E inverter and proposed circuit. (a) Class-E resonant inverter. (b) Proposed single-switch resonant inverter.
Fig. 4. Proposed single-stage single-switch electronic ballast.
buckboost converter case, which allows simpler circuit con-
guration and input electromagnetic interference (EMI) lter
designs [20]. When the SEPIC converter operates in DCM with
a xed switching frequency, the peak of the DCM inductor
current will follow the rectied sinusoidal envelope and a close-
to-unity power factor is achieved at the input. This feature can
be analyzed by rst examining the input line voltage. The in-
put line voltage is given by: v
s
(t) = V
p
sin(2f
L
t), where V
p
is the peak line voltage and f
L
is the line frequency. Second,
the average current (i
s,avg
(t)) drawn from the line is given in
(1), where L
eq
= (L
1
L
2
)/(L
1
+ L
2
), T
s
is the switching pe-
riod, and d is the duty ratio. From (1), it can be observed that
i
s,avg
(t) is purely sinusoidal and is in phase with v
s
(t). There-
fore, a very high power factor is achieved at the input. The input
average power equation is derived from (1) and is expressed as
(2). Another advantage of the SEPIC converter is that the input
line current ripple can be reduced by properly designing the two
inductors (L
1
and L
2
) and capacitor C
1
[20]. By doing so, an
input LC lter can be saved in the SEPIC PFC conguration.
As a result, it can be concluded that SEPIC converter is capable
of achieving all the advantages of the other dcdc converters
for PFC application. Fig. 4 illustrates the nalized single-stage
single-switch electronic ballast circuit that is essentially an in-
tegration of a SEPIC converter and a single-switch inverter to
form a high-power-factor electronic ballast
i
s,avg
(t) =
V
p
d
2
T
s
2L
eq
sin(2f
L
t) (1)
p
avg
=
1
2
_
2
0
V
p
sin(2f
L
t)i
s,avg
(t)d(2f
L
t)
=
d
2
V
2
p
T
s
4L
eq
. (2)
B. Proposed Circuit Operation
The operating stages and key waveforms of the proposed cir-
cuit are presented in this section. The circuit operating principles
2048 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 25, NO. 8, AUGUST 2010
Fig. 5. Operating principles of proposed circuit.
Fig. 6. Key waveforms of proposed circuit.
can be explained by examining the proposed circuit in four dif-
ferent intervals within a switching period, as shown in Fig. 5.
The key waveforms of proposed circuit within a switching pe-
riod are illustrated in Fig. 6.
Interval 1: When M
1
is ON, i
L
rises linearly, i
in
increases
slowly due to the presence of L
in
, so that close to zero-current
switching is provided at the turn ON of the MOSFET. The total
current owing through the switch is i
ds
, which is the sum of
i
in
and i
D
i n
.
Interval 2: When M
1
is OFF, i
L
decreases linearly through
diode D
b
. It continues to decrease linearly until it is equal to
i
L
2
, this stage ends when diode D
b
stops conducting.
Interval 3: All three diodes are OFF with the resonant circuit
continuing to deliver the required energy to the output. Now,
i
L
ows through both L
1
and L
2
. After this stage, the next
switching cycle starts again.
C. Current and Voltage Stress Analysis
One common drawback in many single-stage or single-switch
converters is that the active components, such as the MOSFET
and diodes, may suffer from higher voltage or current stress
compared to the conventional two stages converters for the
same power level. High current or voltage stress across any ac-
tive components can result in bulkier power circuits and higher
overall circuit cost. Hence, in this section, the current/voltage
stress across the switch and all the diodes in the proposed circuit
is studied.
1) RMS Current of Diode D
in
: Diode D
in
conducts only
when the switch is ON. Therefore, the current ( i
D
i n
) owing
through D
in
is equal to the sum of the rising portion of inductor
current (i
L
) and current (i
c1
). The rms current ( i
D
i n
,rms
) is
obtained by rst taking the average of the square of i
D
i n
over
the switching period, and then, averaging it over the ac line
period [21]. The nal expression of i
D
i n
,rms
is given in (3) as
follows:
i
D
i n
,rms
=

_

0
_
1
T
s
_
T
s
0
i
2
D
i n
d(t)
_
d (
L
t)
=

_
1

_

0
_
I
2
pk
d
3
_
d (
L
t) =
d
3/2
T
s
V
p

6L
eq
. (3)
LAM AND JAIN: HIGH-POWER-FACTOR SINGLE-STAGE SINGLE-SWITCH ELECTRONIC BALLAST FOR COMPACT FLUORESCENT LAMPS 2049
Fig. 7. Equivalent circuit of the inverter when the switch is ON.
2) RMS Current of Diode D
b
: Diode D
b
conducts only when
the inductor discharges its energy to the inverter. Hence, using
the similar technique from (3), the rms current i
D
b
,rms
of D
b
can be derived and expressed as follows:
i
D
b
,rms
=

_

0
_
1
T
s
_
T
s
0
i
2
D
b
d(t)
_
d (
L
t)
=

_
1

_

0
_
I
2
pk
t
o1
3T
s
_
d (
L
t) =
_
1 d
_
dT
s
V
p

6L
2
.
(4)
3) RMS Current of Diode D
1
: The current owing through
diode D
1
can be analyzed by observing that its current is equal to
the current owing through inductor L
in
. The simplied equiv-
alent circuit of the inverter stage when the switch is ON is shown
in Fig. 7, where the output current source represents the resonant
current (i
res
) owing through L
r
. The current i
D
1
and the capac-
itor voltage v
cr
are then obtained simultaneously from (5) and
(6), respectively. The key waveforms are illustrated in Fig. 8 and
the nal expressions representing i
in
(
s
t) and v
cr
(
s
t) within
one switching cycle are expressed by (7) and (8), respectively.

V cr
(
s
), which represents the phase difference between i
in
and v
cr
, is given in (9) as a function of
s
. The equation that
represents the rms current of i
D
1
is given by (10a). The average
current of i
in
within one switching cycle has been derived and is
given by (10b), as shown in (5)(10a) and (10b), at the bottom
of the next page.
4) Current Stress of MOSFET: When the MOSFET con-
ducts, the current owing through the MOSFET comprises of
i
D
i n
and i
D
1
. The rms current of the switch is then obtained as
shown in (11) at the bottom of the next page.
The peak current owing through D
in
, D
b
, and M
1
, as ob-
served from Fig. 6, is the same, which is expressed by the
following equation:
i
D
i n
,pk
= i
D
b
,pk
= i
ds,pk
=
V
p
dT
s
L
eq
. (12)
5) Voltage Stress of MOSFET: The voltage stress across the
MOSFET is obtained by using KVL in the proposed inverter.
Since the voltage across L
in
is approximately zero when the
MOSFET is OFF, the peak value of the MOSFET voltage can be
Fig. 8. Key waveforms at the inverter stage.
approximated by (13), where (
s
t)
pk
is the phase corresponds
to the maximum peak voltage across the MOSFET, as given by
(14) and K
0
= I
res
_
L
in
/C
r
v
ds,rms
((
s
t))
pk
= K
0
sin ((
s
t))
pk
cos ((
s
t))
pk
_
K
0
sin () V
dc
cos ()
_
,
2d
s
t T
s
(13)
(
s
t)
pk
= tan
1
_
K
0
cos ()
K
0
sin () V
dc
_
. (14)
D. Analysis of Resonant Inverter With nth Harmonics Circuit
This section analyzes the proposed resonant circuit in detail.
First of all, the nth harmonics circuit of the resonant inverter
is derived. Then, the Fourier series that represents the inverter
input current (i
in
) and the output current (i
out
) is subsequently
derived. The analysis was performed with the assumption that
both the MOSFET and diode are ideal components with lossless
characteristics.
The resonant inverter stage employs a single input induc-
tor (L
in
) and a current source resonant circuit that consists
of a resonant inductor (L
r
), a parallel capacitor (C
r
), and a
parallel inductor (L
p
). The resonant circuit serves as a lamp-
starting element to provide sufcient high voltage to ignite
the lamp. Fig. 9 shows the nth harmonic equivalent ac cir-
cuit of the resonant inverter with R
lamp
and r
f
to represent
the steady-state lamp resistance and the resistance of the la-
ment, respectively. The nth harmonic impedance of the circuit
elements in the resonant circuit are given by (15)(17) respec-
tively, where n = 1 represents the fundamental impedance. The
Fourier series that represents current i
in
(
s
t) is derived based
on (7), where a
0
, a
1
, and b
1
are given by (20)(22), respectively.
The phase difference between i
in
and v
cr
is represented by ,
and the resonant current at is represented by I
res
. Equation
(23) is the expression that represents K. The detailed deriva-
tions of the Fourier coefcients of i
in
(
s
t) are given in the
2050 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 25, NO. 8, AUGUST 2010
Appendix. Equations (15) to (23) shown at the bottom of the
next page.
The Fourier series that represents the output lamp current
(i
out
) is derived by applying basic current division technique to
the ac equivalent circuit in Fig. 9. The corresponding Fourier
series of i
out
is expressed by (24) with the nth harmonic phase
angle (
n
) given by (25). The fundamental phase difference is
obtained by setting n = 1 in (25)
i
out
(
s
t) =
_
Z
cr
Z
cr
+ Z
L
r
+ Z
par
__
Z
L
p
Z
L
p
+ R
lamp
_
(a
1
cos (
s
t
1
) + b
1
sin (
s
t
1
))
+
_
Z
c
r n
Z
c
r n
+ Z
L
r n
+ Z
parn
__
Z
L
p n
Z
L
p n
+ R
lamp
_

n=2,3,...
a
n
cos (n
s
t
n
) + b
n
sin (n
s
t
n
)
_
(24)

n
(
s
) =
90

tan
1
_
(n
s
L
p
/R
lamp
)(1 (n
s
)
2
L
r
C
r
)
1 (n
s
)
2
L
t
C
r
_
. (25)
Equations (19) and (24) have been plotted in MATLAB with
the following circuit parameters: V
dc
= 200 V, d = 0.4, L
in
=
0.39 mH, L
r
= 1 mH, C
r
= 3.3 nF, and L
p
= 3.9 mH. Fig. 10
shows the current waveforms i
in
and i
out
obtained from the
MATLAB calculations. Fig. 11 shows the simulation results
from PSIM 7.0. It can be observed that both gures are very
similar, and therefore, proves that the derived mathematical
equations are able to accurately describe the current waveforms
in the proposed resonant circuit.
E. Characteristics of Resonant Circuit
The basic characteristics that dene the resonant circuit are
provided in this section. The corner frequency (f
o
) and the
v
L
(
s
t) = L
in
d (i
in
(
s
t))
dt
= V
dc
v
cr
(
s
t) , 0
s
t 2d (5)
i
cr
(
s
t) = C
r
d (v
cr
(
s
t))
dt
= i
in
(
s
t) i
res
(
V cr
(
s
)) , 0
s
t 2d (6)
i
in
(
s
t) = i
res
(
V cr
(
s
))
_
1
cos (
s
t )
cos ()
_
+ V
dc
_
C
r
L
in
sin (
s
t)
cos ()
= i
D
1
(
s
t) , 0
s
t 2d (7)
v
cr
(
s
t) = V
dc
_
1
cos (
s
t)
cos ()
_
i
res
(
V cr
(
s
))
_
L
in
C
r
sin (
s
t )
cos ()
, 0
s
t 2d (8)

V cr
(
s
) = tan
1
_
L
t
R
lamp

s
L
r
L
p
_
tan
1
_
(
s
L
p
/R
lamp
)
_
1
2
s
L
r
C
r
_
1
2
s
L
t
C
r
_
(9)
i
D
1
,rms
=

_

0
_
1
T
s
_
T
s
0
i
2
D
1
d(t)
_
d (
L
t)
=

_
1

_

0
_
_
1
T
s
_
dT
s
0
_
i
res
( (
s
))
_
1
cos (
s
t )
cos ()
_
+ V
dc
_
C
r
L
in
sin (
s
t)
cos ()
_
2
d(
s
t)
_
_
d(
L
t) (10a)
i
D
1
,avg
=
1
2
_
2d
0
i
D
1
(
s
t) d(
s
t)
= i
res
( (
s
)) d
1
2
_
i
res
( (
s
))
cos ()
(sin (2d ) + sin ()) +
_
C
r
L
in
V
dc
cos ()
(1 cos (2d))
_
. (10b)
i
ds,rms
=
_
i
2
D
i n
,rms
+ i
2
D
1
,rms
=

d
3
T
2
s
V
2
p
6L
2
eq
+
1
2 cos (
2
)
__
3I
2
res
2

K
2
2
_
sin(2) +
_
K
2
2

I
2
res
2
_
sin(2( d))
_
. (11)
LAM AND JAIN: HIGH-POWER-FACTOR SINGLE-STAGE SINGLE-SWITCH ELECTRONIC BALLAST FOR COMPACT FLUORESCENT LAMPS 2051
Fig. 9. AC nth harmonics equivalent circuit with lamp and lament resistances included.
Fig. 10. Current waveforms at the resonant inverter stage plotted in MATLAB.
Fig. 11. Current waveforms at the resonant inverter stage plotted in PSIM.
Z
L
r n
(
s
) = jn
s
L
r
(15)
Z
C
r n
(
s
) =
1
jn
s
C
r
(16)
Z
L
p n
(
s
) = jn
s
L
p
(17)
Z
pn
(
s
) =
jn
s
L
p
R
lamp
jn
s
L
p
+ R
lamp
(18)
i
in
(
s
t) =
a
0
2
+ a
1
cos (
s
t) + b
1
sin (
s
t) +

n=2,3,...
a
n
cos (n
s
t) + b
n
sin (n
s
t) (19)
a
0
=
I
res
(sin() + K + I
res
d cos () + I
res
sin ( d) K cos (d))
cos ()
(20)
a
1
=
(1/8) (I
res
sin()K2I
res
sin (+d) I
res
sin ( 2d) +2I
res
d cos () + 2I
res
d sin ( d) + K cos (2d))
cos ()
(21)
b
1
=
(1/8) (3I
res
cos() K sin(2d) + 2Kd 2I
res
cos(d + ) 2I
res
cos( d) 2dI
res
sin() + I cos( 2d))
cos ()
(22)
K = V
dc
_
C
r
L
in
. (23)
2052 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 25, NO. 8, AUGUST 2010
Fig. 12. Voltage gain plot for different Q values.
quality factor (Q) are dened as (26) and (27), respectively
f
o
=
1
2

L
r
C
r
(26)
Q =
2f
o
L
r
R
lamp
. (27)
During the lamp preheat stage, the lamp resistance is innite
and the resonant circuit becomes a parallel LC network. The
preheat frequency during this phase is given by (28), where i
pre
is the preheat current. The preheat voltage is given by (29)
f
pre
=
v
pre
2 (L
r
+ L
p
) i
pre
(28)
v
pre
=
_
2f
pre
L
p
1 (2f
pre
)
2
(L
r
+ L
p
) C
r
_
i
in
. (29)
During lamp ignition, the load can still be treated as an open
circuit at the output of the resonant circuit. The lamp ignition
frequency (f
ign
) is then derived using (29) and the nal ex-
pression is given by (30), where V
ign
is the amplitude of the
lamp ignition voltage and I
in
is the average current of i
in
. The
magnitude of the ignition voltage (V
ign
), which is the voltage
across the parallel inductor (L
p
), is given by (31) in terms of
the fundamental component of i
in
. After the lamp is ignited,
the lamp resistance becomes a nite value. By applying fun-
damental approximation to the resonant circuit and assuming
that the losses in the passive circuit components are negligi-
ble, the output-to-input voltage gain equation can be obtained
and is plotted in Fig. 12 as a function of the relative operat-
ing switching frequency, f
r
= f
s
/f
o
, where f
s
is the switching
frequency. Providing that L
p
is designed to be much larger
than L
r
, it can be observed that high output voltage can be
achieved and guaranteed during the lamp start-up condition (i.e.,
TABLE I
DESIGN SPECIFICATIONS
low Q)
f
ign
=
_
(L
p
I
in
/V
ign
)
2
4 (L
r
+ L
p
) C
r
(L
p
I
in
/V
ign
)
4 (L
r
+ L
p
) C
r
(30)
V
ign
= v
L
p
() = i
in,1

L
p
1
2
L
eq
C
r

. (31)
III. DESIGN EXAMPLE AND PERFORMANCE OF PROPOSED
CIRCUIT
A. Design Example
To verify the feasibility of the proposed circuit, the proposed
circuit is tested on a 13-W CFL. The design specications are
given in Table I.
Design Procedure:
1) Calculations of L
r
, C
r
, and L
p
: R
lamp
is rst calculated,
as shown in (32) using I
out
and P
out
R
lamp
=
P
out
I
2
out
=
13 W
(0.14 A)
2
= 663 . (32)
The values of L
r
, C
r
, and L
p
are then obtained as follows:
L
r
=
QR
lamp
2f
s
=
0.8(663 )
2(80 kHz)
1.1 mH (33)
C
r
=
1
(2f
s
)
2
L
r
=
1
(280 kHz)
2
(1.1 mH)
3.5 nF. (34)
L
p
is selected to be higher than L
r
so that sufcient high
voltage can be guaranteed at the output during lamp ignition. In
this example, L
p
is selected to be 3.3 mH.
2) Calculations of L
1
, L
2
, and C
2
: The SEPICinductors L
1
and L
2
are calculated according to the method outlined in [20].
In the proposed design, in order to minimize the current ripple
in i
s
, L
1
is selected to be 5.6 mH and L
2
is designed to be
1 mH. L
eq
is then calculated to be 0.84 mH. The duty cycle (d)
is calculated according to the SEPIC average power equation in
(2). The d that is required in this design example is given by
(35), where V
p
= 170 V, L
eq
= 0.84 mH, T
s
= 1/74 kHz, and
= 90%
d =

4P
avg
L
eq
V
2
p
T
s
= 0.35. (35)
The SEPIC DCM voltage gain equation is given in (36) [21],
where R
i
represents the mean input resistance of the inverter cir-
cuit and is dened as given by (37). i
in,avg
can be obtained from
(10b) and is calculated to be approximately 80 mA. Assuming
that =90%, R
i
is then calculated to be 1823 . V
dc
is then cal-
culated to be 146 V, according to (36), with V
rect,avg
= 2V
p
/
LAM AND JAIN: HIGH-POWER-FACTOR SINGLE-STAGE SINGLE-SWITCH ELECTRONIC BALLAST FOR COMPACT FLUORESCENT LAMPS 2053
TABLE II
CIRCUIT PARAMETERS
Fig. 13. (a) Measured line current from a commercial 13-W CFL without PFC (v
s
: 50 V/div, i
s
: 0.5 A/div, and time: 5 ms/div). (b) Measured line current from
proposed circuit on a 13-W CFL (v
s
: 50 V/div, i
s
: 0.2 A/div, and time: 5 ms/div).
representing the average rectied voltage. The output capacitor
C
2
is obtained in (38) by allowing 10% ripple in V
dc
. With both
R
i
and V
dc
obtained earlier, C
2
is subsequently calculated to
be at least 4.8 F, according to (38), in order to minimize the
voltage ripple across the dc-link capacitor. In the actual design,
C
2
is selected to be 15 F
V
dc
V
rect,avg
=

d
2
T
s
R
i
2L
eq
(36)
R
i
=
P
avg
(i
in,avg
)
2
(37)
C
2

V
dc
4f
L
V
dc
R
i
4.8 F. (38)
3) Calculation of L
in
: In order to achieve zero-current
switching (ZCS) at the turn ON of the MOSFET and ensure
that i
in
return to zero before the turn OFF of the MOSFET, the
selection of L
in
is critical. The maximum value of L
in
can be
obtained from (A10) or (A11) given in the Appendix. Since d is
2054 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 25, NO. 8, AUGUST 2010
Fig. 14. Lamp voltage and current during ignition phase (v
out
: 200 V/div; i
out
: 0.2 A/div; time: 500 ms/div).
Fig. 15. Output lamp current and dc capacitor voltage (V
dc
) waveforms (V
dc
: 50 V/div; i
out
: 0.2 A/div; time: 5 ms/div).
Fig. 16. Steady-state lamp current (i
out
: 0.1 A/div; time: 10 s/div).
LAM AND JAIN: HIGH-POWER-FACTOR SINGLE-STAGE SINGLE-SWITCH ELECTRONIC BALLAST FOR COMPACT FLUORESCENT LAMPS 2055
Fig. 17. MOSFET current and voltage waveforms (v
ds
: 100 V/div; i
ds
: 0.5 A/div; time: 5 s/div).
Fig. 18. MOSFET current and voltage waveforms within line frequency cycle (v
ds
: 100 V/div; i
ds
: 0.5 A/div; time: 2 ms/div).
obtained to be 0.35 from (35), K
1
is then determined to be 0.51
from (A10). The constant K is then determined to be accord-
ing to the K
1
expression given in the Appendix. Finally, with
C
r
= 3.3 nF and V
dc
= 146, the maximum allowable value of
L
in
is calculated to be 0.58 mH from (23). In the actual design,
a value of 0.39 mH is selected to meet all the requirements.
4) Selection of Diodes D
in,
D
b
, D
1
, and MOSFET: Fast-
recovery diodes are required for D
in
and D
b
to minimize the
turn-OFF recovery losses in the diodes. From (12), the peak
current owing through D
in
and D
b
is calculated as follows:
i
D
i n
,pk
= i
D
b
,pk
=
(146 V) (0.35) (1/74 kHz)
0.84 mH
0.82 A.
(39)
MUR160 fast-recovery diodes are used in the experimental
prototype. The peak current owing through the MOSFET is
same as i
D
i n
,pk
and i
D
b
,pk
, which is also 0.82 A. The MOSFET
voltage stress can be calculated from (13) with V
dc
= 146 V,
C
r
=3.3 nF, and L
in
=0.39 mH. The peak voltage stress during
steady-state operation is calculated to be 345 V, according to
(13).
B. Experimental Results
Table II summarizes the list of circuit parameters and com-
ponents used in this design example. Fig. 13(a) shows the mea-
sured line current and voltage from a commercial 13-W CFL.
The power factor obtained is 0.62. Fig. 13(b) shows the in-
put line current of the proposed circuit and a power factor of
0.992 is achieved. Fig. 14 illustrates the lamp voltage transition
during the lamp ignition process. Fig. 15 shows the dc-link ca-
pacitor voltage and output lamp current. The crest factor of the
lamp current is measured to be 1.59, which is below the limit,
according to the ANSI standards [22]. Fig. 16 shows the steady-
2056 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 25, NO. 8, AUGUST 2010
Fig. 19. (a) Power factor. (b) Measured efciency.
state output lamp current. The current and voltage waveforms
across the MOSFET are illustrated in Fig. 17. Fig. 18 shows the
MOSFET current and voltage waveforms within the two line
frequency cycles. It is observed that the peak voltage across the
MOSFET and the peak current owing through the MOSFET
is approximately 350 V and 0.85 A, respectively. The measured
peak voltage and current values are close to the calculated values
obtained in the previous section. Fig. 19 illustrates the power
factor and efciency performance for the proposed circuit un-
der different line voltages. It is observed that a power factor of
at least 0.98 is maintained under all operating conditions. The
overall efciency is measured to be approximately 82% at the
rated voltage. The majority of the power loss is due to the turn-
OFF switching loss of the MOSFET and the copper losses in the
inductors.
IV. CONCLUSION
In this paper, a high-power-factor single-switch electronic
ballast has been introduced for CFL applications. Due to its
single-switch characteristics, both the semiconductor complex-
ity level and the MOSFET driver design are greatly simplied
compared to the existing solutions. Detailed operating principles
and the features of the proposed circuit have been provided in
this paper. All the theoretical analysis has been justied through
the design example for a 13-W CFL. It has been conrmed
through experimental results that the proposed circuit achieves
a power factor of at least 0.98 at the input and an overall ef-
ciency of 82% at the rated condition in the proposed circuit.
APPENDIX
The general form of any Fourier series that is periodic in the
range [, ] is shown in (A1), where a
0
, a
n
, and b
n
repre-
sented by (A2)(A4), respectively. Hence, the Fourier series that
represents i
in
can also be written in the formof (A1), as given in
(A5), where the corresponding a
0
represents the average com-
ponent of i
in
, a
1
and b
1
represent the fundamental coefcient,
and a
n
and b
n
represent the high order coefcients with n 2,
as given in (A6) and (A7), respectively
f(x) =
a
0
2
+

n=1,2,...
a
n
cos (nx) +

n=1,2,...
b
n
sin (nx)
(A1)
LAM AND JAIN: HIGH-POWER-FACTOR SINGLE-STAGE SINGLE-SWITCH ELECTRONIC BALLAST FOR COMPACT FLUORESCENT LAMPS 2057
a
0
=
1

f (x) dx (A2)
a
n
=
1

f (x) cos (nx) dx (A3)

b
n
=
1

f (x) sin (nx) dx (A4)

i
in
(
s
t) =
a
0
2
+ a
1
cos (
s
t) + b
1
sin (
s
t)
+

n=2,3,...
a
n
cos (n
s
t) + b
n
sin (n
s
t) (A5)
a
n
=
1

_
i
res
(
V cr
(
s
))
_
1
cos (
s
t )
cos ()
_
+ V
dc
_
C
r
L
in
sin (
s
t)
cos ()
_
cos (n
s
t) d (
s
t) (A6)
b
n
=
1

_
i
res
(
V cr
(
s
))
_
1
cos (
s
t )
cos ()
_
+ V
dc
_
C
r
L
in
sin (
s
t)
cos ()
_
sin (n
s
t) d (
s
t) . (A7)
The conduction time of i
in
is given by 2d, as shown in
Fig. 8. d, which is dened to be the duty ratio, can be determined
accordingly by substituting
s
t = 2d into (7) and equating (7)
to zero, as shown in (A8), with K given by (23). If we let K
1
=
(cos ()/(sin () (K/(i
res
(
V cr

s
))))), then, squaring both
sides, and then, adding one on each side of (A8) will result in
(A9). Then, K
1
can be expressed in terms of d, as shown in
(A10). Finally, d is also obtained, as expressed in (A11) by
solving (A9) in terms of K
1
i
res
(
V cr
(
s
))
_
1
cos (
s
t )
cos ()
_
+ V
dc
_
C
r
L
in
sin (
s
t)
cos ()
= 0

cos ()
sin () (K/(i
res
(
V cr
(
s
))))
=
sin (2d)
1 cos (2d)
(A8)
K
2
1
+ 1 =
2 2 cos (2d)
1 2 cos (2d) + cos
2
(2d)
K
2
1
+ 1 =
2
1 cos (2d)
(A9)
K
1
=

2
1 cos (2d)
1 (A10)
d =
1
2
cos
1
_
K
2
1
1
K
2
1
+ 1
_
. (A11)
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2058 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 25, NO. 8, AUGUST 2010
John C. W. Lam (S04M06) received the B.Sc.
(with rst class honors) and M.Sc.E. degrees in
electrical engineering from Queens University,
Kingston, Canada, in 2003 and 2006, respectively.
He is currently working toward the Ph.D. degree at
Queens University.
He is working as a Research Assistant at the
Queens Centre for Energy and Power Electronics
Research (ePOWER). His research interests include
high power factor electronic ballasts designs and dig-
ital control techniques in high frequency resonant
inverters. He has published over 15 technical (journal and conference) papers
and has 1 patent pending.
Mr. Lam is the recipient of the Ontario Graduate Scholarship in 20032004
and 20082009. He is a member of the IEEE Power Electronics Society and the
IEEE Industry Applications Society.
Praveen K. Jain (S86M88SM91F02) re-
ceived the B.E. degree (with honors) fromthe Univer-
sity of Allahabad, India, and the M.A.Sc. and Ph.D.
degrees fromthe University of Toronto, Toronto, ON,
Canada, in 1980, 1984, and 1987, respectively, all in
electrical engineering.
Currently, he is a Professor and Canada Research
Chair at the Department of Electrical and Computer
Engineering, Queens University, Kingston, Canada,
and the Director of the Queens Centre for Energy
and Power Electronics Research (ePOWER). He has
secured over $20M cash and $20M in-kind in external research funding to
conduct research in the eld of power electronics. He has supervised more
than 75 graduate students, postdoctoral fellows and research engineers. He has
published over 350 technical papers (including more than 90 IEEE Transac-
tions papers). He holds more than 50 patents (granted and pending). He is also
a Founder of CHiL Semiconductor in Tewksbury, MA; and SPARQ System
in Kingston, Ontario, Canada. Prior to joining Queens, he has worked as a:
Professor at Concordia University (19942000); Technical Advisor at Nortel
(19901994); Senior Space Power Electronics Engineer at Canadian Astronau-
tics Ltd (19871990); Design Engineer at ABB (1981); Production Engineer
at Crompton Greaves (1980). In addition, he has consulted with Astec, Ballard
Power, Freescale, General Electric, Intel and Nortel.
Dr. Jain is an Associate Editor of the IEEE TRANSACTIONS ON POWER
ELECTRONICS and an Editor of International Journal of Power Electronics. He
is also a Distinguished Lecturer of IEEE Industry Applications Society. He is a
Fellowof the Engineering Institute of Canada (EIC) and the Canadian Academy
of Engineering (CAE). He is also a recipient of the 2004 Engineering Medal
(R&D) from the Professional Engineers of Ontario.