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AIM:

To implement the following using CMOS.


Y=(A.(B+C)+(D+E))
Output
C e ll 0

v(O ut)

5. 0

4. 5

4. 0

3. 5

3. 0

Voltage (V)

2. 5

2. 0

1. 5

1. 0

0. 5

0. 0
0

10

20

30

40

50

60

70

80

90

1 00

T im e ( n s )
C e ll 0

v ( E)

5. 0

4. 5

4. 0

3. 5

3. 0

Voltage (V)

2. 5

2. 0

1. 5

1. 0

0. 5

0. 0
0

10

20

30

40

50

60

70

80

90

1 00

T im e ( n s )
C e ll 0

v ( D)

5. 0

4. 5

4. 0

3. 5

3. 0

Voltage (V)

2. 5

2. 0

1. 5

1. 0

0. 5

0. 0
0

10

20

30

40

50

60

70

80

90

1 00

T im e ( n s )
C e ll 0

v ( C)

5. 0

4. 5

4. 0

3. 5

3. 0

Voltage (V)

2. 5

2. 0

1. 5

1. 0

0. 5

0. 0
0

10

20

30

40

50

60

70

80

90

1 00

T im e ( n s )
C e ll 0

v ( B)

5. 0

4. 5

4. 0

3. 5

3. 0

Voltage (V)

2. 5

2. 0

1. 5

1. 0

0. 5

0. 0
0

10

20

30

40

50

60

70

80

90

1 00

T im e ( n s )
C e ll 0

v ( A)

5. 0

4. 5

4. 0

3. 5

3. 0

Voltage (V)

2. 5

2. 0

1. 5

1. 0

0. 5

0. 0
0

10

20

30

40

50

T im e ( n s )

60

70

80

90

1 00

GraphVout
E
D
C
B
A
T-Spice Code.model NMOS NMOS level=1
.model PMOS PMOS level=1
.tran 1n 100n
Vdd Vdd Gnd 5
VA A Gnd PULSE (0 5 0 1n 1n 10n 20n)
VB B Gnd PULSE (0 5 0 1n 1n 20n 40n)
VC C Gnd PULSE (0 5 0 1n 1n 20n 40n)
VD D Gnd PULSE (0 5 0 1n 1n 20n 30n)
VE E Gnd PULSE (0 5 0 1n 1n 20n 50n)
.print tran v(A) v(B) v(C) v(D) v(E) v(Out)
.end
Circuit Diagram:

AIM
To implement the following using CMOS.
Y=AB+BC+CA
Output:
C e ll1
v (O u t )

5.0

4.5

4.0

3.5

3.0

Voltage (V)

2.5

2.0

1.5

1.0

0.5

0.0
0

10

20

30

40

50

60

70

80

90

1 00

T im e ( n s )
C e ll1
v (C )

5.0

4.5

4.0

3.5

3.0

Voltage (V)

2.5

2.0

1.5

1.0

0.5

0.0
0

10

20

30

40

50

60

70

80

90

1 00

T im e ( n s )
C e ll1
v (B )

5.0

4.5

4.0

3.5

3.0

Voltage (V)

2.5

2.0

1.5

1.0

0.5

0.0
0

10

20

30

40

50

60

70

80

90

1 00

T im e ( n s )
C e ll1
v (A )

5.0

4.5

4.0

3.5

3.0

Voltage (V)

2.5

2.0

1.5

1.0

0.5

0.0
0

10

20

30

40

50

T im e ( n s )

60

70

80

90

1 00

graphOut
C
B
A
T-Spice Code.model NMOS NMOS level=1
.model PMOS PMOS level=1
.tran 1n 100n
Vdd Vdd Gnd 5
VA A Gnd PULSE (0 5 0 1n 1n 10n 20n)
VB B Gnd PULSE (0 5 0 1n 1n 20n 30n)
VC C Gnd PULSE (0 5 0 1n 1n 30n 40n)
.print tran v(A) v(B) v(C) v(Out)
.end
Circuit Diagram:

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