KIN TRC MY TNH

ET4270
TS. Nguyn c Minh

[Adapted from Computer Organization and Design, 4th Edition, Patterson & Hennessy, 2008, MK] [Adapted from Computer Architecture lecture slides, Mary Jane Irwin, 2008, PennState University]

T chc lp
S tn ch 3 (3-1-1-6)

Ging vin
Vn phng Email Website

TS. Nguyn c Minh

C9-401 minhnd1@gmail,com https://sites.google.com/site/fethutca/home
Username: ca.fet.hut@gmail.com Pass: dungkhoiminh

Sch

Computer Org and Design, 3rd Ed., Patterson &Hennessy, 2007 Digital Design and Computer Architecture, David Money Harris

Th nghim Bi tp

3 bi Theo chng, bi xem trn trang web

Gii thiu

HUST-FET, 13/03/2011

im s iu kin thi Bi thi gia k

Bi tp
Tin trnh
Ti a: 100 im,
Bt u: 50 im Tch ly, tr qua tr li cu hi trn lp v ng gp t chc lp

Lab 30%
20% (Ti a 100 im)
10%

Bi thi cui k

70%

Gii thiu

HUST-FET, 13/03/2011

Lch hc
Thi gian:
T 14h00 n 17h20 L thuyt: 11 bui x 135 pht / 1 bui Bi tp: 4 bui x 135 pht / 1 bui Thay i lch (ngh, hc b) s c thng bo trn website trc 2 ngy

Gii thiu

HUST-FET, 13/03/2011

Kt lun chng 2
D liu v ch th cho my tnh c biu din bng cc chui bit. Gi tr ca d liu, ngha ca ch th my c quy nh trong phng php m ha. Thit k kin trc tp lnh:
Kch thc v kiu d liu Php ton: loi no c h tr nh dng v m ha ch th: Ch th c gii m th no? V tr ton hng v kt qu
S lng ton hng? Gi tr ton hng c lu u? Kt qu c lu v tr no? Cc ton hng b nh c nh v th no?

Kin trc tp lnh MIPS(RISC) c thit k da trn 4 nguyn tc c bn. B cng tr nhn chia c trin khai bng cc phn t logic hay bng thut ton.

Chng 3. B x l - Processor

HUST-FET, 13/03/2011

Nguyn tc thit k MIPS (RISC)

Tnh n gin quan trng hn tnh quy tc(Simplicity favors regularity)
Ch th kch thc c nh (32 bit) t nh dng ch th (3 loi nh dng) M lnh v tr c nh (6 bit u)

Nh hn th nhanh hn
S ch th gii hn S thanh ghi gii hn S ch a ch gii hn

Tng tc cc trng hp thng dng

Cc ton hng s hc ly t thanh ghi (my tnh da trn c ch loadstore) Cc ch th c th cha ton hng trc tip

Thit k tt i hi s tha hip

3 loi nh dng ch th

Chng 3. B x l - Processor

HUST-FET, 13/03/2011

Ni dung

ng d liu b x l MIPS
n xung nhp a xung nhp Hiu nng

K thut ng ng
Nguyn tc hot ng Hiu nng Xung t trong ng ng

HUST-FET, 13/03/2011

B x l: ng d liu v iu khin

Trin khai cc lnh

Lnh truy cp b nh: lw, sw Lnh s hc v logic: add, sub, and, or, slt Lnh iu khin dng chng trnh: beq, j

Instruction Fetch Instruction Decode Operand

Trin khai cc pha hot ng

Dng thanh ghi PC lu a ch lnh

c lnh t b nh, v cp nht gi tr PC Gii m lnh v c cc thanh ghi Thc hin lnh Fetch Lu kt qu
PC = PC+4

Fetch Execute
Result Store Next

Exec, Store

Decode

Instruction

HUST-FET, 13/03/2011

Thit k ng b theo ng h

Mch ng b theo ng h: thi im d liu trong 1 phn t trng thi l hp l v n nh c quy nh bi xung ng h

Phn t trng thi - phn t nh - VD. thanh ghi, FF Kch hot theo sn cc trng thi thay i khi c xn xung c ni dung ca phn t trng thi -> tnh gi tr bng logic t hp -> ghi kt qu vo phn t trng thi
State element 1 Combinational logic State element 2

Hot ng thng thng:

clock

Cc phn t trng thi c ghi tt c cc chu k ng h. Nu khng: cn tn hiu iu khin vic ghi

one clock cycle

HUST-FET, 13/03/2011

Np lnh

c lnh ti a ch (lu trong) PC t b nh lnh (eng. Instruction Memory)

Cp nht gi tr PC ti a ch ca lnh k tip

clock
Add 4

Fetch PC = PC+4

Instruction Memory

Exec, Store

Decode

PC

Read Address

Instruction

PC c cp nht mi chu k khng cn tn hiu iu khin ghi PC. c t b nh lnh c thc hin bng logic t hp
10 HUST-FET, 13/03/2011

Gii m lnh

Chuyn cc bit thuc trng m lnh v trng m chc nng ti khi iu khin

Fetch PC = PC+4

Control Unit

Exec, Store

Decode
Instruction

Read Addr 1 Register Read Read Addr 2 Data 1 File Write Addr Read Write Data Data 2

c 2 gi tr ton hng ngun t tp thanh ghi

- Ch s cc thanh ghi nm trong lnh
11 HUST-FET, 13/03/2011

Thc hin lnh loi R

Lnh nh dng R (add, sub, slt, and, or)

31 R-type: op

25 rs

20 rt

15 rd

10

shamt funct

Thc hin php ton (m ha bi op v funct) trn gi tr ton hng trong rs v rt Ghi kt qu vo tp thanh ghi (ti v tr rd)
RegWrite ALU control

Fetch PC = PC+4 Exec Decode

Instruction

Read Addr 1 Register Read Read Addr 2 Data 1 File Write Addr Read Write Data Data 2

ALU

overflow zero

Tp thanh ghi khng c ghi mi chu k cn tn hiu iu khin ghi ring bit.
12 HUST-FET, 13/03/2011

Thc hin lnh c ghi b nh

Tnh a ch b nh bng cch cng thanh ghi c s (c t tp thanh ghi khi gii m lnh) vi gi tr offset ghi (sw) gi tr (c c t tp thanh ghi khi gii m lnh) vo b nh d liu c (lw) gi tr t b nh d liu vo tp thanh ghi
RegWrite ALU control overflow zero
Address ALU Data Memory Read Data Write Data

MemWrite

Instruction

Read Addr 1 Register Read Read Addr 2 Data 1 File Write Addr Read Write Data Data 2

Sign Extend

MemRead

13

HUST-FET, 13/03/2011

Thc hin lnh r nhnh c iu kin

so snh ton hng c t tp thanh ghi khi gii m tnh a ch ch bng cch cng gi tr PC (sau khi cp nht) vi trng offset 16 bit c m rng du.
Add 4 Shift left 2 Add

Branch target address

ALU control
PC Read Addr 1 Register Read Read Addr 2 Data 1 File Write Addr Read Write Data Data 2

zero (to branch control logic)

ALU

Instruction

16

Sign Extend

32

14

HUST-FET, 13/03/2011

Thc hin lnh nhy khng iu kin

Thay 28 bit thp ca PC bng 26 bt thp ca lnh c np v 2 bt 0

Add 4 4

Instruction Memory
PC Read Address Instruction 26

Shift left 2

Jump address
28

15

HUST-FET, 13/03/2011

ng d liu

Ghp cc phn ca ng d liu thm cc ng tn hiu iu khin v b ghp (multiplexors) Thit k n xung nhp cc pha thc hin: np, gii m and thc hin, ghi ca mi lnh trong mt chu k ng h

Cc ti nguyn phn cng ca ng d liu khng th ti s dng cho cng 1 lnh, mt s ti nguyn phi nhn i (VD., b nh lnh v d liu ring bit, mt vi b cng) b ghp c dng u vo ca cc ti nguyn dng chung v c iu khin bng tn hiu iu khin

Chu k ng h: xc nh bng di ng d liu di nht

16

HUST-FET, 13/03/2011

ng d liu: Phn np, thc hin lnh R, lw,sw

Add 4

RegWrite

ALUSrc ALU control ovf zero

MemWrite

MemtoReg

Instruction Memory PC Read Address Instruction

Read Addr 1 Register Read Read Addr 2 Data 1 File Write Addr Read Write Data

Address ALU Data Memory Read Data

Data 2

Write Data

Sign 16 Extend

MemRead
32

Cc tn hiu iu khin b ghp: la chn u vo cho cc khi chc nng c tnh bng khi iu khin t trng m lnh (opcode) v trng chc nng lnh (funct)
17 HUST-FET, 13/03/2011

B x l n xung nhp (1) Lnh R

0
Add 4 ALUOp Instr[31-26] Control Unit ALUSrc RegWrite RegDst Instr[25-21] Read Addr 1 Register Read Instr[20-16] Read Addr 2 Data 1 File 0 Write Addr Read Branch Shift left 2 Add

1
PCSrc MemRead MemtoReg MemWrite

ovf zero
ALU Address Data Memory Read Data Write Data

Instruction Memory PC Read Address Instr[31-0]

1 0

0 1
ALU control

Instr[15 -11] Instr[15-0]

Write Data

Data 2

Sign 16 Extend

32

Instr[5-0]

18

HUST-FET, 13/03/2011

BXL n xung nhp (3) Lnh lw, sw

0
Add 4 ALUOp Instr[31-26] Control Unit ALUSrc RegWrite RegDst Instr[25-21] Read Addr 1 Register Read Instr[20-16] Read Addr 2 Data 1 File 0 Write Addr Read Branch Shift left 2 Add

1
PCSrc MemRead MemtoReg MemWrite

ovf zero
ALU Address Data Memory Read Data Write Data

Instruction Memory PC Read Address Instr[31-0]

1 0

0 1
ALU control

Instr[15 -11] Instr[15-0]

Write Data

Data 2

Sign 16 Extend

32

Instr[5-0]

19

HUST-FET, 13/03/2011

BXL n xung nhp (4) Lnh r nhnh

0
Add 4 ALUOp Instr[31-26] Control Unit ALUSrc RegWrite RegDst Instr[25-21] Read Addr 1 Register Read Instr[20-16] Read Addr 2 Data 1 File 0 Write Addr Read Branch Shift left 2 Add

1
PCSrc MemRead MemtoReg MemWrite

ovf zero
ALU Address Data Memory Read Data Write Data

Instruction Memory PC Read Address Instr[31-0]

1 0

0 1
ALU control

Instr[15 -11] Instr[15-0]

Write Data

Data 2

Sign 16 Extend

32

Instr[5-0]

20

HUST-FET, 13/03/2011

BXL n xung nhp Thm lnh nhy

Instr[25-0] 26 Add Shift left 2

1
28 32 PC+4[31-28] Shift left 2 Add

0 0 1
PCSrc

4
ALUOp Instr[31-26] Control Unit ALUSrc RegWrite RegDst Instr[25-21] Read Addr 1 Register Read Instr[20-16] Read Addr 2 Data 1 File 0 Write Addr Read Jump Branch

MemRead MemtoReg MemWrite

ovf zero
ALU Address

Instruction Memory PC Read Address Instr[31-0]

Data Memory Read Data

Write Data

0 1
ALU control

Instr[15 -11] Instr[15-0]

Write Data

Data 2

Sign 16 Extend

32

Instr[5-0]
21 HUST-FET, 13/03/2011

Tnh chu ky ng h Tc ng di nht

Tnh chu k ng h trong trng hp b qua tr b ghp, khi iu khin, khi m rng du, khi c PC, khi dch 2, dy dn, thi gian thit lp v gi. Cho bit tr:

Truy cp b nh lnh v b nh d liu (200 ps)

Khi s hc logic v b cng (200 ps) Truy cp tp thanh ghi (c hoc ghi) (100 ps)

Instr. Rtype load store beq jump

I Mem

Reg Rd ALU Op D Mem Reg Wr

Total

22

HUST-FET, 13/03/2011

V d 3.1 Hiu nng thit k n xung nhp

tr logic khi Truy cp lnh c thanh ghi Hot ng ALU Truy cp b nh DL Ghi thanh ghi Tng Tc ng h = Cc loi lnh: R-type 44% Load 24% Store 12% Branch 18% Jump 2% Trung bnh 2 ns 1 ns 2 ns 2 ns 1 ns 8 ns
ALU-type
P C

Not used

Load

P C

Store

P C

Not used

6 ns 8 ns 7 ns 5 ns 3 ns

Branch
(and jr)

P C

Not used

Not used

Not used

Jump
(except jr & jal)

P C

Not used

Not used

Not used

Not used

23

HUST-FET, 13/03/2011

Thit k n xung nhp u nhc im

S dng chu k ng h khng hiu qu chu k ng h c t theo lnh chm nht

Vn c bit ca cc lnh phc tp nh lnh nhn du phy ng

Cycle 1 Cycle 2

Clk
lw sw Waste

Tn din tch thit k v cn nhn i mt s khi chc nng (VD. b cng) v chng khng th c chia s trong cng 1 chu k ng h Nhng n gin v d hiu

24 HUST-FET, 13/03/2011

So snh nh gi thit k n xung nhp

ng h tc 125 MHz l bnh thng
Instruction access 2 ns Register read 1 ns ALU operation 2 ns Data cache access 2 ns Register write 1 ns Total 8 ns Single-cycle clock = 125 MHz

So snh vi cc b x l trn th trng:

Khng ti nu so snh tr thc hin 1 lnh Mt b x l 2.5 GHz vi 20 giai on pipeline c tr khong: 0.4 ns/cycle 20 cycles = 8 ns Lu lng ca b x l c pipeline tt hn rt nhiu: Tt hn ti 20 ln vi cc b x l pht hnh n lnh Tt hn ti 100 ln vi cc b x l pht hnh a lnh
25 HUST-FET, 13/03/2011

Thit k a xung nhp

Chia lnh thnh cc pha thc hin: IF, ID, EX, MEM, WB. Mi pha thc hin trong 1 chu k xung nhp Cc u im
o
o

Thi gian thc hin (= s pha) ca mi lnh c iu chnh ty thuc phc tp ca lnh Cc khi chc nng c chia s gia cc pha khc nhau ca lnh do mt khi chc nng c th khng cn trong ton b cc pha thc hin ca lnh

Clock
Time needed Time allotted

Instr 1

Instr 2

Instr 3

Instr 4

Clock
Time needed Time saved

3 cycles
Time allotted

5 cycles

3 cycles

4 cycles

Instr 1

Instr 2

Instr 3

Instr 4

26

HUST-FET, 13/03/2011

V d 3.2 Hiu nng thit k a xung nhp

Cc loi lnh s dng s chu k khc nhau R-type 44% 4 cycles Load 24% 5 cycles Store 12% 4 cycles Branch 18% 3 cycles Jump 2% 3 cycles ng gp vo s chu k trung bnh cn cho mt lnh: R-type Load Store Branch Jump
Not used

ALU-type

P C

Load

P C

Store

P C

Not used

Branch
(and jr)

P C

Not used

Not used

Not used

Jump
(except jr & jal)

P C

Not used

Not used

Not used

Not used

CPI trung bnh

_____________________________

27

HUST-FET, 13/03/2011

So snh nh gi thit k a xung nhp

ng h tc 500MHz tt hn 125MHz ca b x l mt xung nhp, nhng vn l bnh thng. So snh vi cc b x l trn th trng:
Cycle time = 2 ns Clock rate = 500 MHz

Khng ti nu so snh tr thc hin 1 lnh Mt b x l 2.5 GHz vi 20 giai on pipeline c tr khong: 0.4 ns/cycle 20 cycles = 8 ns Lu lng ca b x l c pipeline tt hn rt nhiu: Tt hn ti 20 ln vi cc b x l pht hnh n lnh Tt hn ti 100 ln vi cc b x l pht hnh a lnh
28

R-type Load Store Branch Jump

44% 24% 12% 18% 2%

4 cycles 5 cycles 4 cycles 3 cycles 3 cycles

Contribution to CPI R-type 0.444 = 1.76 Load Store Branch Jump 0.245 0.124 0.183 0.023 = = = = 1.20 0.48 0.54 0.06

Average CPI 4.04

_____________________________

HUST-FET, 13/03/2011

Thit k n xung nhp

Clock rate = 125 MHz CPI = 1 (125 MIPS)
jta (PC) PC rs rt (rs) Ovfl ALUOvfl

Incr PC Next PC

Next addr

Instr cache

inst rd 31 imm op fn

0 1 2

Reg file
(rt) / 16 0 32 SE / 1

ALU
Func

ALU out

Data addr Data in

Data cache

Data out

0 1 2

Register input

Br&Jump

RegDst RegWrite

ALUSrc ALUFunc

DataRead RegInSrc DataWrite

29

HUST-FET, 13/03/2011

Thit k a xung nhp

Clock rate = 500 MHz CPI 4 ( 125 MIPS)
26 / 4 MSBs Inst Reg Address PC 0 1 x Reg rs rt 0 rd 1 31 2 0 1 2 Data Reg imm 16 / fn (rs) 30 / SysCallAddr 0 1

30

jta

ALUZero x Mux ALUOvfl 0 Zero z Reg 1 Ovfl y Mux 4 0 1 2 4 3

4 0 1 2 3

Cache
Data

Reg file
(rt) 32 y Reg SE /

ALU
Func ALU out

InstData PCWrite

MemWrite

op IRWrite

RegInSrc RegWrite

ALUSrcX ALUSrcY

ALUFunc JumpAddr

PCSrc

MemRead

RegDst

30

HUST-FET, 13/03/2011

ng ng (Eng. pipeline): Kt hp u im

Pipelined:

Clock rate = 500 MHz CPI 1

Single-cycle: Multicycle:

Clock rate = 125 MHz CPI = 1

Clock rate = 500 MHz CPI 4

31

HUST-FET, 13/03/2011

Dy chuyn sn xut trong nh my

32

HUST-FET, 13/03/2011

Tng hiu nng (tc ) bng cch no?

Bt u np v thc hin lnh tip theo trc khi lnh hin ti kt thc:

K thut ng ng c p dng trong hu ht cc b x l hin i Trong iu kin l tng vi s lng lnh ln, ng ng gip tng tc bng s giai on ng ng. ng ng 5 giai on s nhanh hn gn 5 ln v Tc tng gp 5.

Tcpu I CPI Tc

Np (v thc hin) nhiu lnh cng mt lc

X l superscalar

33

HUST-FET, 13/03/2011

5 giai on ng ng ca lnh lw
Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5

lw

IFetch Dec

Exec

Mem

WB

IFetch: Np lnh v cp nhp gi tr PC IDec: c thanh ghi v gii m lnh

EXec: Thc hin lnh R; tnh a ch b nh

MEM: c/ghi b nh d liu

WB: Ghi kt qu vo tp thanh ghi

34

HUST-FET, 13/03/2011

ng ng trong MIPS

Bt u lnh tip theo trc khi lnh hin ti kt thc

ci thin thng lng tng s cng vic hon thnh trong 1 khong thi gian tr lnh (thi gian thc hin, thi gian p ng thi gian t lc bt u n lc kt thc lnh) khng c gim
Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Cycle 8

lw sw R-type

IFetch

Dec
IFetch

Exec
Dec IFetch

Mem
Exec Dec

WB
Mem Exec WB Mem WB

chu k ng h (thi gian 1 giai on ng ng) quyt nh bi giai on chm nht mt s giai on khng dng ton b chu k ng h (VD., WB) mt s lnh, c cc giai on l chu k lng ph (ngha l, khng thc hin g trong chu k vi lnh )
35 HUST-FET, 13/03/2011

V d 3.3 Pipeline vs. n xung nhp

Trin khai n xung nhp (Tc = 800 ps):
Cycle 1 Clk lw sw
Waste

Cycle 2

Trin khai pipeline (Tc = 200 ps):

lw IFetch sw Dec IFetch Exec Dec Mem Exec Dec WB Mem Exec WB Mem WB

400 ps

R-type IFetch

hon thnh 1 lnh trong trng hp pipeline cn 1000 ps (So vi 800 ps trong trng hp n xung nhp). Ti sao? thc hin 1.000.000 lnh adds cn thi gian bao lu?
36 HUST-FET, 13/03/2011

K thut ng ng cho MIPS(RISC) ISA

D trin khai:

Cc lnh c cng di (32 bits)

C th np lnh trong giai on 1st v gii m lnh trong giai on 2nd

t nh dng lnh (ba). Cc nh dng lnh c tnh i xng

- C th c thanh ghi giai on 2nd

Ch truy cp b nh bng lnh lw v sw

- C th tnh a ch b nh giai on EX (thc hin lnh)

Mi lnh ch ghi ln nht 1 kt qu (lm thay i trng thi my) 2 giai on cui (MEM or WB) Ton hng c sp xp trong b nh sao cho 1 lnh dch chuyn d liu ch cn 1 ln truy cp b nh.

37

HUST-FET, 13/03/2011

ng d liu MIPS pipeline

Thanh ghi trng thi gia cc giai on thc hin lnh phn cch
IF:IFetch ID:Dec EX:Execute MEM: MemAccess WB: WriteBack

IF/ID Add 4

ID/EX

EX/MEM

Shift left 2

Add

MEM/WB

Instruction Memory
Read Address PC

Read Addr 1

Register Read
Data 1 Read Addr 2

Data Memory
ALU

File
Write Addr Write Data Read Data 2

Address
Write Data

Read Data

16

Sign Extend

32

System Clock
38 HUST-FET, 13/03/2011

iu khin MIPS pipeline

Cc tn hiu iu khin c xc nh trong giai on gii m v c lu trong cc thanh ghi trng thi gia cc giai on pipeline
PCSrc ID/EX EX/MEM Control IF/ID Add Branch MEM/WB

RegWrite

Shift left 2

Add

Instruction Memory
Read Address PC

Read Addr 1

Register Read
Data 1 Read Addr 2

Data Memory
ALUSrc ALU Address Write Data ALU cntrl Read Data

MemtoReg

File
Write Addr Write Data

Read Data 2

16

Sign Extend

MemRead

32

ALUOp

RegDst 39 HUST-FET, 13/03/2011

M t hot ng pipeline

ALU

IM

Reg

DM

Reg

o hiu nng: Cn bao nhiu chu k thc hin on m? Phn tch hot ng: ALU lm g chu k 4? Ci tin: C xy ra hazard khng? Ti sao? Dng cch no khc phc?

40

HUST-FET, 13/03/2011

Hiu nng pipeline

Time (clock cycles)

I n s t r. O r d e r

Inst 0
Inst 1

IM

Reg

DM

Reg

IM

Reg

DM

Reg

Khi pipeline y, 1 lnh c hon thnh trong 1 chu k CPI = 1

Reg

ALU

ALU

ALU

Inst 2
Inst 3 Inst 4

IM

Reg

DM

ALU

IM

Reg

DM

Reg

ALU

IM

Reg

DM

Reg

Thi gian in y pipeline

41

HUST-FET, 13/03/2011

Xung t Pipeline
Xung Xung

t cu trc: yu cu s dng cng mt ti nguyn cho 2 lnh khc nhau ti cng 1 thi im t d liu: yu cu s dng d liu trc khi n sn sng Cc ton hng ngun ca 1 lnh c to ra bi lnh pha trc vn ang nm trong pipeline

Xung

t iu khin: yu cu quyt nh iu khin dng chng trnh trc khi iu kin r nhnh v gi tr PC mi c tnh ton Cc lnh r nhnh, nhy v ngt

Gii

quyt xung t bng cch ch i

Khi iu khin pipeline cn pht hin xung t V hnh ng gii quyt xung t
42 HUST-FET, 13/03/2011

B nh n: Xung t cu trc
Time (clock cycles)

I n s t r.
O r d e r

lw Inst 1 Inst 2 Inst 3 Inst 4

Mem

Reg

Mem

Reg

c d liu t b nh
Reg

ALU Reg Mem

ALU

Mem

Mem

ALU Reg Mem

Reg

Mem

Reg

ALU

Mem

Mem

Reg

ALU

c lnh t b nh

Reg

Mem

Reg

Sa: B nh d liu v lnh ring r(I$ and D$)

43 HUST-FET, 13/03/2011

Xung t cu trc khi truy cp tp thanh ghi

add $1, Inst 1 Inst 2 add $2,$1,
IM Reg DM Reg

I n s t r. O r d e r

IM

Reg

DM

Reg

Sa xung t truy cp tp thanh ghhi bng cch c trong na u chu k v ghi trong na sau chu k
Reg

IM

ALU

Reg

IM

ALU

Reg

ALU

DM

Sn ng h iu khin ghi

Sn ng h iu khin c

ALU

DM

Reg

44

HUST-FET, 13/03/2011

S dng thanh ghi: Xung t d liu

Ph thuc d liu ngc theo thi gian gy ra xung t

I n s t r. O r d e r

add $1,
sub $4,$1,$5

ALU

IM

Reg

DM

Reg

ALU

IM

Reg

DM

Reg

ALU

and $6,$1,$7
or $8,$1,$9

IM

Reg

DM

Reg

ALU

IM

Reg

DM

Reg

ALU

xor $4,$1,$5

IM

Reg

DM

Reg

Xung t c trc khi ghi (Read before write)

45 HUST-FET, 13/03/2011

S dng thanh ghi: Xung t d liu

Ph thuc d liu ngc theo thi gian gy ra xung t

I n s t r. O r d e r

add $1,
sub $4,$1,$5

ALU

IM

Reg

DM

Reg

ALU

IM

Reg

DM

Reg

ALU

and $6,$1,$7
or $8,$1,$9

IM

Reg

DM

Reg

ALU

IM

Reg

DM

Reg

ALU

xor $4,$1,$5

IM

Reg

DM

Reg

Xung t c trc khi ghi (Read before write)

46 HUST-FET, 13/03/2011

c t b nh: Gy xung t d liu

Dependencies backward in time cause hazards

ALU

I n s t r. O r d e r

lw

$1,4($2)

IM

Reg

DM

Reg

ALU

sub $4,$1,$5

IM

Reg

DM

Reg

ALU

and $6,$1,$7
or $8,$1,$9

IM

Reg

DM

Reg

ALU

IM

Reg

DM

Reg

ALU

xor $4,$1,$5

IM

Reg

DM

Reg

Load-use data hazard

47 HUST-FET, 13/03/2011

Xung t iu khin

Dependencies backward in time cause hazards

I n s t r. O r d e r

beq
lw

ALU

IM

Reg

DM

Reg

ALU

IM

Reg

DM

Reg

ALU

Inst 3 Inst 4

IM

Reg

DM

Reg

ALU

IM

Reg

DM

Reg

48

HUST-FET, 13/03/2011

Cc cu trc pipeline khc

Php ton nhn (chm) gp 2 ln?

Lm ng h chm i 2 ln hoc thc hin trong 2 chu k ng h (v khng cn s dng giai on DM)
MUL ALU IM Reg DM Reg

Truy cp b nh d liu chm hn b nh lnh 2 ln?

Lm ng h chm i 2 ln hoc thc hin vic c trong 2 chu k (v gi nguyn chu k ng h)

ALU
IM Reg DM1 DM2 Reg

49

HUST-FET, 13/03/2011

Tm tt 1

Cc b x l hin i u dng k thut pipeline Pipelining khng lm gim tr ca 1 nhim v n l, n gip tng thng lng ca ton b Tng tc tim nng: CPI = 1 v ng h nhanh, Tc nh

Tc ng h b hn ch bi giai on pipeline chm nht

Cc giai on pipeline khng cn bng lm gim hiu sut

Thi gian lm y pipeline v thi gian lm trng pipeline nh hng n tng tc khi pipeline su (nhiu giai on) v on m ngn
Dng nh hng xu ti CPI (lm CPI ln hn gi tr l tng 1)

Cn pht hin v gii quyt xung t

50

HUST-FET, 13/03/2011

Xung t d liu

Xung t d liu c trc ghi

10 10 10
ALU

Value of $1

10 10/-20 -20 -20

-20

-20

add $1,
sub $4,$1,$5

IM

Reg

DM

Reg

ALU

IM

Reg

DM

Reg

ALU

and $6,$1,$7
or $8,$1,$9

IM

Reg

DM

Reg

ALU

IM

Reg

DM

Reg

ALU

xor $4,$1,$5
51

IM

Reg

DM

Reg

HUST-FET, 13/03/2011

Gii quyt xung t: Tm dng

C th gii quyt xung t d liu bng dng ch stall nh hng ti CPI

I n s t r.
O r d e r

add $1, stall stall

ALU

IM

Reg

DM

Reg

sub $4,$1,$5 and $6,$1,$7

ALU

IM

Reg

DM

Reg

ALU

IM

Reg

DM

Reg

52

HUST-FET, 13/03/2011

Gii quyt xung t: Chuyn tip d liu

Gii quyt xung t d liu bng chuyn tip kt qu ngay khi chng sn sng ti ni cn
Reg

I n s t r. O r d e r

add $1,

ALU

IM

Reg

DM

Reg

ALU

sub $4,$1,$5 and $6,$1,$7 or $8,$1,$9

IM

Reg

DM

Reg

ALU

IM

Reg

DM

ALU

IM

Reg

DM

Reg

ALU

xor $4,$1,$5

IM

Reg

DM

Reg

53

HUST-FET, 13/03/2011

Chuyn tip d liu

Ly kt qu thi im n xut hin sm nht trong bt k thanh ghi pipeline no, v chuyn tip n n khi chc nng (VD. ALU) m cn kt qu ti chu k ng h Vi khi chc nng ALU: u vo c th t bt k thanh ghi pipeline no ch khng cn t ID/EX bng cch

thm b chn vo trc u vo ca ALU ni d liu ghi Rd EX/MEM hoc MEM/WB ti mt trong 2 hoc c 2 thanh ghi pipeline Rs v Rt thuc giai on EX. thm phn iu khin phn cng iu khin b chn

Cc khi chc nng khc cng cn c thm tng t (VD. DM) Vi chuyn tip c th t c CPI = 1 ngay khi c s ph thuc d liu
54 HUST-FET, 13/03/2011

Minh ha trin khai chuyn tip

I n s t r. O r d e r

add $1,

ALU

IM

Reg

DM

Reg

ALU

sub $4,$1,$5 and $6,$7,$1

IM

Reg

DM

Reg

ALU

IM

Reg

DM

Reg

EX forwarding

MEM forwarding

55

HUST-FET, 13/03/2011

Xung t d liu khi chuyn tip

Mt loi xung t d liu xut hin khi chuyn tip: Xung t gia kt qu ca lnh ang giai on WB v lnh ang giai on MEM kt qu no cn c chuyn tip?

I n s t r. O r d e r

add $1,$1,$2 add $1,$1,$3 add $1,$1,$4

ALU

IM

Reg

DM

Reg

ALU

IM

Reg

DM

Reg

ALU

IM

Reg

DM

Reg

56

HUST-FET, 13/03/2011

Xung t d liu khi c lnh lw

ALU

I n s t r. O r d e r

lw

IM $1,4($2)

Reg

DM

Reg

ALU

sub $4,$1,$5 and $6,$1,$7 or $8,$1,$9

IM

Reg

DM ALU

Reg

IM

Reg

DM

Reg

ALU

IM

Reg

DM

Reg

ALU

xor $4,$1,$5

IM

Reg

DM

Reg

ALU

IM

Reg

DM

57

HUST-FET, 13/03/2011

Xung t iu khin

Khi a ch cc lnh khng tun t (i.e., PC = PC + 4); xut hin khi c cc lnh thay i dng chng trnh

Lnh r nhnh khng iu kin (j, jal, jr) Lnh r nhnh c iu kin (beq, bne) Ngt, Exceptions

Gii php

Tm dng (nh hng CPI) Tn ton iu kin r nhnh cng sm cng tt trong giai on pipeline gim s chu k phi dng R nhnh chm (Delayed branches - Cn h tr ca trnh dch) D on v hy vng iu tt nht!

Xung t iu khin t xy ra, nhng khng c gii php gii quyt hiu qu nh chuyn tip i vi xung t d liu
58 HUST-FET, 13/03/2011

Lnh nhy: Cn mt chu k dng

Lnh

nhy khng c gii m cho n giai on ID, cn mt lnh xa (flush)

xa, t trng m lnh ca thanh ghi pipeline IF/ID bng 0 (lm n tr thnh 1 lnh noop)
IM

I n s t r.

j flush j target

Reg

DM

Reg

IM

Reg

DM ALU

Reg

Gii quyt xung t lnh nhy bng cch ch flush

Reg

ALU

ALU

O r d e r

IM

Reg

DM

Lnh nhy rt t xut hin ch chim 3% s lnh trong SPECint

59 HUST-FET, 13/03/2011

Xung t iu khin lnh r nhnh

I n s t r. O r d e r

beq
lw

ALU

IM

Reg

DM

Reg

ALU

IM

Reg

DM

Reg

ALU

Inst 3 Inst 4

IM

Reg

DM

Reg

ALU

IM

Reg

DM

Reg

60

HUST-FET, 13/03/2011

Gii quyt xung t iu khin lnh r nhnh

I n s t r. O r d e r

beq

IM

Reg

DM

Reg

flush
flush flush beq target

IM

Reg

DM ALU

Reg

Gii quyt xung t bng ch flush nhng nh hng CPI

Reg

IM

ALU

Reg

IM

ALU

DM
ALU Reg

Reg

DM

Reg

ALU

IM

DM

Reg

ALU

Inst 3

IM

Reg

DM

61

HUST-FET, 13/03/2011

Gii quyt xung t iu khin lnh r nhnh

Tnh ton iu kin r nhnh cng sm cng tt, tc l trong giai on gii m ch cn 1 chu k ch
ALU IM Reg DM Reg

I n s t r. O r d e r

beq
flush

IM

Reg

DM

Reg

Fix branch hazard by waiting flush

ALU

ALU

beq target
Inst 3

IM

Reg

DM

Reg

ALU

IM

Reg

DM

62

HUST-FET, 13/03/2011

R nhnh chm

Nu phn cng cho r nhnh nm giai on ID, ta c th loi b cc chu k ch r nhnh bng cch s dng r nhnh chm (delayed branches) lun thc hin lnh theo sau lnh lnh r nhnh r nhnh c tc dng sau lnh k tip n

Trnh dch MIPS compiler chuyn 1 lnh an ton (khng b nh hng bi lnh r nhnh) ti sau lnh r nhnh (vo khe tr). V vy s du c s r nhnh chm

Vi pipeline su (nhiu giai on), tr r nhnh tng cn nhiu lnh c chn vo sau lnh r nhnh

R nhnh chm ang c thay th bi cc phng php khc tn km hn nhng mm do (ng) hn nh d on r nhnh S pht trin ca IC cho php c b d on r nhnh t tn km hn
63 HUST-FET, 13/03/2011

Sp xp lnh trong r nhnh chm

A. T trc lnh r nhnh B. T ch lnh r nhnh
add $1,$2,$3 if $2=0 then delay slot sub $4,$5,$6 add $1,$2,$3 if $1=0 then delay slot becomes

C. T nhnh sai add $1,$2,$3 if $1=0 then

delay slot

sub $4,$5,$6
becomes add $1,$2,$3 if $1=0 then sub $4,$5,$6

becomes if $2=0 then add $1,$2,$3

add $1,$2,$3 if $1=0 then sub $4,$5,$6

TH A l la chn tt nht, in c khe tr v gim I TH B v C, lnh sub cn sao li, tng I TH B v C, phi m bo thc hin lnh sub khng nh hng khi khng r nhnh
64 HUST-FET, 13/03/2011

D on r nhnh tnh

Gii quyt xung t r nhnh bng cch gi s 1 hng r nhnh v tip tc khng cn ch tnh ton kt qu r nhnh thc s. on khng r nhnh lun gi s lnh khng r nhnh, tip tc np cc lnh k tip, ch khi c r nhnh th cn dng pipeline

1.

Nu r nhnh, xa cc lnh sau r nhnh (sm trong pipeline)

trong giai on IF, ID, v EX nu b tnh r nhnh MEM ba dng trong giai on IF v ID nu b tnh r nhnh EX hai dng trong giai on IF nu b tnh r nhnh ID mt dng

m bo rng cc lnh b xa khng nh hng ti trng thi my. Khi to li pipeline ch lnh r nhnh

65

HUST-FET, 13/03/2011

Xa khi d on sai
ALU

I n s t r. O r d e r

4 beq $1,$2,2

IM

Reg

DM

Reg

ALU

8 sub $4,$1,$5

IM

Reg

DM

Reg

66

HUST-FET, 13/03/2011

Xa khi d on sai (on khng r nhnh)

ALU IM Reg DM Reg

I n s t r. O r d e r

4 beq $1,$2,2 8 flush$4,$1,$5 sub 16 and $6,$1,$7

ALU

IM

Reg

DM

Reg

ALU

IM

Reg

DM

Reg

ALU

20 or r8,$1,$9

IM

Reg

DM

Reg

xa, t trng m lnh ca thanh ghi pipeline IF/ID bng 0 (lm n tr thnh 1 lnh noop)

67

HUST-FET, 13/03/2011

D on r nhnh

Gii quyt xung t bng cch gi thit kt qu r nhnh v tip tc on c r nhnh d on lun lun c r nhnh

2.

on c r nhnh lun cn 1 chu k dng (nu phn cng tnh r nhnh giai on ID) Cn phng php c trc (vo b m) lnh a ch ch??

V thit hi do r nhnh ang tng ln (vi cc pipeline su), m hnh d on r nhnh tnh s nh hng ti hiu nng. Vi nhiu phn cng hn, c th th d on hot ng r nhnh ng lc chng trnh c thc hin D on r nhnh ng on r nhnh lc chy da trn cc thng tin chy (run-time information)
68 HUST-FET, 13/03/2011

3.

D on r nhnh ng bng 1 bit

B d on 1 bt s sai 2 ln nu on khng r nhnh:

Gi s predict_bit = 0 lc bt u (ch ra khng r nhnh) lnh r nhnh iu khin Loop: 1st loop instr cui vng lp Ln thc hin vng lp 1, b d on sai cho lnh r nhnh v n dn quay li u vng lp; cn o bt r nhnh (predict_bit = 1) Khi no vn cn r nhnh (vn lp), d on ng Khi thot khi vng lp, b d on s sai 1 ln na v ln ny s khng r nhnh m ra ngoi vng lp; o bit r nhnh (predict_bit = 0)

1.

2.

2nd loop instr . . . last loop instr bne $1,$2,Loop fall out instr

3.

Nu lp 10 ln ta s c t l r nhnh ng l 80%. Nu dng lnh r nhnh beq th ng 90%

69 HUST-FET, 13/03/2011

D on r nhnh ng bng 2 bit

C ch dng 2 bit cho chnh xc 90% v ch khi d on sai 2 ln th bit d on mi thay i

Loop: 1st loop instr 2nd loop instr . . . last loop instr bne $1,$2,Loop fall out instr

Taken
Predict Taken Not taken Taken Not taken Predict Not Taken Predict Taken

Taken

Not taken
Predict Not Taken Not taken

Taken

70

HUST-FET, 13/03/2011

Exceptions

Exceptions (ngt - interrupts) c th coi l 1 dng xung t d liu. Exception xut hin t:

Trn khi thc hin lnh s hc Lnh khng c nh ngha Yu cu t thit b vo ra Yu cu dch v h iu hnh (VD. li trang, li TLB) Li chc nng phn cng dng thc hin lnh li, tt c cc lnh trc hon thnh, xa cc lnh sau , t thanh ghi ch ra nguyn nhn exception, lu li a ch lnh li, nhy n a ch nh trc (a ch ca hm x l exception)

Pipeline cn phi:

Phn mm (OS) s x l tip exception.

71 HUST-FET, 13/03/2011

Hai loi exceptions

Ngt khng ng b vi s thc hin chng trnh

gy ra bi s kin bn ngoi c th c x l gia cc lnh, nn cc lnh ang c trong pipeline hon thnh trc khi chuyn iu khin cho hm x l ngt ca OS. n gin l dng v tip tc chng trnh ngi dng

By (Exception) ng b vi s thc hin chng trnh

gy ra bi s kin bn trong hm x l by cn sa cha iu kin cho ng lnh b by, nn phi dng lnh li trong trong pipeline v chuyn iu khin cho hm x l by ca OS lnh li c th tip tc chng trnh c th b kt thc hoc c tip tc
72 HUST-FET, 13/03/2011

Exception c th xut hin u trong pipeline

ALU IM Reg DM Reg

Stage(s)?

Synchronous?

Trn s hc
Lnh khng nh ngha Li TLB hoc trang Yu cu dch v I/O Li phn cng

73

HUST-FET, 13/03/2011

Exception c th xut hin u trong pipeline

ALU IM Reg DM Reg

Stage(s)?

Trn s hc Lnh khng nh ngha Li TLB hoc trang Yu cu dch v I/O Li phn cng

EX
ID IF, MEM any any

Synchronous? yes yes yes no no

Ch rng nhiu exception c th xut hin ng thi trong mt chu k ng h

74 HUST-FET, 13/03/2011

Nhiu exception ng thi

ALU

I n s t r. O r d e r

Inst 0 Inst 1 Inst 2 Inst 3 Inst 4

IM

Reg

DM

Reg

ALU

IM

Reg

DM

Reg

ALU

IM

Reg

DM

Reg

ALU

IM

Reg

DM

Reg

ALU

IM

Reg

DM

Reg

Lnh sm nht s b ngt u tin

75 HUST-FET, 13/03/2011

Nhiu exception ng thi

ALU

I n s t r.
O r d e r

Inst 0 Inst 1 Inst 2 Inst 3 Inst 4

IM

Reg

DM

Reg

D$ page fault
ALU IM Reg DM Reg

arithmetic overflow
ALU IM Reg DM Reg

undefined instruction
DM Reg

ALU

IM

Reg

ALU

IM

Reg

DM

Reg

I$ page fault

Lnh sm nht s b ngt u tin

76 HUST-FET, 13/03/2011

Tng kt
Tt c cc b x l hin i u dng pipeline tng hiu sut (CPI=1 v ng h nhanh - fc ln) Tc ng h pipeline b gii hn bi giai on pipeline chm nht thit k pipeline cn bng l rt quan trng Cn pht hin v gii quyt xung t trong pipeline

Xung cu trc gii quyt: thit k pipeline ng Xung t d liu

- Dng (nh hng CPI) - Chuyn tip (cn phn cng h tr)

Xung t iu khin t phn cng quyt nh r nhnh ln cc trng thi u trong pipeline
- Dng (nh hng CPI) - R nhnh chm (cn h tr ca trnh dch) - D on r nhnh tnh v ng (cn phn cng h tr)

X l ngt trong pipeline phc tp

77

HUST-FET, 13/03/2011