1.

Illustration of the Technology Scale down

Etienne Sicard
etienne.sicard@insa-tlse.fr http://intrage.insa-tlse.fr/~etienne

Summary
1. Whos who 2. Road map

3. The MOS device

4. The inverter 5. Conclusion

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E. Sicard - Technology scale down

1. Whos who in France

Philips ST rennes
Atmel ST Tours

Philips Ibm
Atmel ST Grenoble

Motorola

ST, Atmel

Texas, VLSI Cadence

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E. Sicard - Technology scale down

2. Roadmap
Bits
10 GIGA

DRAM

1G 256M 64M

4G

1 GIGA
100 MEG 16M 4M 1M 1 MEG 100K 83
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10 MEG
256K

86

89

92

95

98

01

04

Year
4

Anne
E. Sicard - Technology scale down

2. Roadmap
Technology 2.0 (m)
1.0

80286

80386

Production
486 pentium pentium II Pentium IV

0.3 0.2 0.1 0.05 0.03 83 86 89 92 95 98

Research

01

04

Year
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2. Roadmap
Leti 1 MOS 0.02m Dec. 2000

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IBM 106 MOS 0.015m Nov. 2001 6

2. Roadmap
0.5 m Devices
l

0.18 m

0.12m

1995
Interconnects 3 layers

2000
7 layers

2002
8 layers

Frequency

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120MHz

E. Sicard - Technology scale down

500MHz

1500 MHz
7

2. Roadmap
Technology 0.7m 0.5m 0.35m 0.25m 0.18m 0.12m 0.10m
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Year 1988 1992 1994 1996 1999 2001 2003

Metal 2 3 5 6 7 8 8-9

Supply (V) Oxide(A) Vt (V) 5.0 3.3 3.3 2.5 1.9 1.5 1.0 200 120 75 65 50 40 35 0.7 0.6 0.5 0.45 0.40 0.30 0.25

ST technology Hcmos4 Hcmos5 Hcmos6 Hcmos7 Hcmos8 Hcmos9 Hcmos10

8

E. Sicard - Technology scale down

2. Roadmap
Supply (V)
Chip I/Os

5.0 I/O trend

3.3
2.5 1.5

Chip Core

Core trend
0.5
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0.35

0.18

0.10

0.07

Technology (m)
9

E. Sicard - Technology scale down

2. Roadmap
Typical wire load (fF) 100 75 50 Radiation

25
Charges (C.V) 0.5 0.35 0.18 0.10 Technology (m) 0.07

Charge

Soft error due to radiation becomes probable

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3. The MOS device

1
3 2

I 3

demo
1 Little quiz 2
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11

3. The MOS device

0 1

Ron close from 1000

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demo
12

3. The MOS device

1 1 1 Good 0 0 Bad 1 0

1
0 Bad 0 Good 1

Technology scale down keeps those drawbacks

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3. The MOS device

R off
100 M

Static Current (A)

1 0.1 0.01
Low leakage MOS

10 M
1 M

1 MT block

100K

0.001 Technology (m)

14

0.5
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0.35

0.18

0.10

0.07

E. Sicard - Technology scale down

3. The MOS device

High Speed Low power High Voltage

3.3V

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4. The inverter
In

Out Time
In

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0.25m typical delay 50ps demo Depends on conditions (10,90%) Depends on charge (capacitance)
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16

4. The inverter
Idd (mA)

In, Out (V) Time

Current
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peaks 0.2mA
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4. The inverter
Delay (ns)

Interconnection (m)
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4. The inverter
Ring oscillator
0.7m

0.25m

Frequencies x 5 although VDD divided by 2

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Conclusion
Illustration of technology scale down Continuous gain in frequency Power supply reduction The MOS keeps the same, but many versions Increased interconnects improve density In 2002, ST will produce the 0.12m technology

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20