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Set Instruc Atmega16
Set Instruc Atmega16
Rev. 0856IAVR07/10
I/O Registers
RAMPX, RAMPY, RAMPZ
Registers concatenated with the X-, Y-, and Z-registers enabling indirect addressing of the whole data space on MCUs with more than 64K bytes data space, and constant data fetch on MCUs with more than 64K bytes program space.
RAMPD
Register concatenated with the Z-register enabling direct addressing of the whole data space on MCUs with more than 64K bytes data space.
EIND
Register concatenated with the Z-register enabling indirect jump and call to the whole program space on MCUs with more than 64K words (128K bytes) program space.
Stack
STACK: Stack for return address and pushed registers SP: Stack Pointer to STACK
Flags
: 0: 1: -: Flag affected by instruction Flag cleared by instruction Flag set by instruction Flag not affected by instruction
The operand is contained in register d (Rd). Register Direct, Two Registers Rd and Rr Figure 2. Direct Register Addressing, Two Registers
Operands are contained in register r (Rr) and d (Rd). The result is stored in register d (Rd).
3
0856IAVR07/10
Operand address is contained in 6 bits of the instruction word. n is the destination or source register address.
Note: Some complex AVR Microcontrollers have more peripheral units than can be supported within the 64 locations reserved in the opcode for I/O direct addressing. The extended I/O memory from address 64 to 255 can only be reached by data addressing, not I/O addressing.
31 OP
20 19 Rr/Rd
16
0x0000
Data Address 15 0
RAMEND
A 16-bit Data Address is contained in the 16 LSBs of a two-word instruction. Rd/Rr specify the destination or source register.
15 OP
10 Rr/Rd
6 5 q
RAMEND
Operand address is the result of the Y- or Z-register contents added to the address contained in 6 bits of the instruction word. Rd/Rr specify the destination or source register. Data Indirect Figure 6. Data Indirect Addressing
Data Space 0x0000 15 X, Y OR Z - REGISTER 0
RAMEND
Operand address is the contents of the X-, Y-, or the Z-register. In AVR devices without SRAM, Data Indirect Addressing is called Register Indirect Addressing. Register Indirect Addressing is a subset of Data Indirect Addressing since the data space form 0 to 31 is the Register File.
5
0856IAVR07/10
Data Indirect with Pre-decrement Figure 7. Data Indirect Addressing with Pre-decrement
Data Space 0x0000 15 X, Y OR Z - REGISTER 0
-1
RAMEND
The X,- Y-, or the Z-register is decremented before the operation. Operand address is the decremented contents of the X-, Y-, or the Z-register. Data Indirect with Post-increment Figure 8. Data Indirect Addressing with Post-increment
Data Space 0x0000 15 X, Y OR Z - REGISTER 0
RAMEND
The X-, Y-, or the Z-register is incremented after the operation. Operand address is the content of the X-, Y-, or the Z-register prior to incrementing.
LSB
FLASHEND
Constant byte address is specified by the Z-register contents. The 15 MSBs select word address. For LPM, the LSB selects low byte if cleared (LSB = 0) or high byte if set (LSB = 1). For SPM, the LSB should be cleared. If ELPM is used, the RAMPZ Register is used to extend the Z-register. Program Memory with Post-increment using the LPM Z+ and ELPM Z+ Instruction Figure 10. Program Memory Addressing with Post-increment
0x0000
LSB
1
FLASHEND
Constant byte address is specified by the Z-register contents. The 15 MSBs select word address. The LSB selects low byte if cleared (LSB = 0) or high byte if set (LSB = 1). If ELPM Z+ is used, the RAMPZ Register is used to extend the Z-register.
7
0856IAVR07/10
Direct Program Addressing, JMP and CALL Figure 11. Direct Program Memory Addressing
31 OP 16 LSB 15 21 PC 0 0 6 MSB 16 0x0000
FLASHEND
Program execution continues at the address immediate in the instruction word. Indirect Program Addressing, IJMP and ICALL Figure 12. Indirect Program Memory Addressing
0x0000
15 PC
FLASHEND
Program execution continues at address contained by the Z-register (i.e., the PC is loaded with the contents of the Zregister).
FLASHEND
Program execution continues at address PC + k + 1. The relative address k is from -2048 to 2047.
9
0856IAVR07/10
Complementary Rd Rr Rd < Rr Rd Rr Rd > Rr Rd Rr Rd Rr Rd < Rr Rd Rr Rd > Rr Rd Rr No carry Positive No overflow Not zero
Boolean Z+(N V) = 1 (N V) = 1 Z=0 Z(N V) = 0 (N V) = 0 C+Z=1 C=1 Z=0 C+Z=0 C=0 C=0 N=0 V=0 Z=0
Mnemonic BRGE* BRLT BRNE BRLT* BRGE BRSH* BRLO/BRCS BRNE BRLO* BRSH/BRCC BRCC BRPL BRVC BRNE
Comment Signed Signed Signed Signed Signed Unsigned Unsigned Unsigned Unsigned Unsigned Simple Simple Simple Simple
Rd = Rr Rd Rr Rd < Rr Rd > Rr Rd Rr
BRLT BRLO(1) BRSH/BRCC BREQ BRSH(1) BRLO/BRCS BRCS BRMI BRVS BREQ
1. Interchange Rd and Rr in the operation before the test, i.e., CP Rd,Rr CP Rr,Rd
10
Mnemonics
Operands
Description
Flags
#Clocks
#Clocks XMEGA
ADD ADC ADIW(1) SUB SUBI SBC SBCI SBIW AND ANDI OR ORI EOR COM NEG SBR CBR INC DEC TST CLR SER MUL(1) MULS
(1) (1) (1)
Rd, Rr Rd, Rr Rd, K Rd, Rr Rd, K Rd, Rr Rd, K Rd, K Rd, Rr Rd, K Rd, Rr Rd, K Rd, Rr Rd Rd Rd,K Rd,K Rd Rd Rd Rd Rd Rd,Rr Rd,Rr Rd,Rr Rd,Rr Rd,Rr Rd,Rr K
Add without Carry Add with Carry Add Immediate to Word Subtract without Carry Subtract Immediate Subtract with Carry Subtract Immediate with Carry Subtract Immediate from Word Logical AND Logical AND with Immediate Logical OR Logical OR with Immediate Exclusive OR Ones Complement Twos Complement Set Bit(s) in Register Clear Bit(s) in Register Increment Decrement Test for Zero or Minus Clear Register Set Register Multiply Unsigned Multiply Signed Multiply Signed with Unsigned Fractional Multiply Unsigned Fractional Multiply Signed Fractional Multiply Signed with Unsigned Data Encryption
Rd Rd Rd Rd Rd Rd Rd Rd + 1:Rd Rd Rd Rd Rd Rd Rd Rd Rd Rd Rd Rd Rd Rd Rd R1:R0 R1:R0 R1:R0 R1:R0 R1:R0 R1:R0 if (H = 0) then R15:R0 else if (H = 1) then R15:R0 Branch Instructions
Rd + Rr Rd + Rr + C Rd + 1:Rd + K Rd - Rr Rd - K Rd - Rr - C Rd - K - C Rd + 1:Rd - K Rd Rr Rd K Rd v Rr Rd v K Rd Rr $FF - Rd $00 - Rd Rd v K Rd ($FFh - K) Rd + 1 Rd - 1 Rd Rd Rd Rd $FF Rd x Rr (UU) Rd x Rr (SS) Rd x Rr (SU) Rd x Rr<<1 (UU) Rd x Rr<<1 (SS) Rd x Rr<<1 (SU) Encrypt(R15:R0, K) Decrypt(R15:R0, K)
Z,C,N,V,S,H Z,C,N,V,S,H Z,C,N,V,S Z,C,N,V,S,H Z,C,N,V,S,H Z,C,N,V,S,H Z,C,N,V,S,H Z,C,N,V,S Z,N,V,S Z,N,V,S Z,N,V,S Z,N,V,S Z,N,V,S Z,C,N,V,S Z,C,N,V,S,H Z,N,V,S Z,N,V,S Z,N,V,S Z,N,V,S Z,N,V,S Z,N,V,S None Z,C Z,C Z,C Z,C Z,C Z,C
1 1 2 1 1 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 1/2
MULSU
RJMP IJMP
(1)
PC + k + 1 Z, 0 Z, EIND k
2 2 2 3
EIJMP(1) JMP(1) k
Jump
11
0856IAVR07/10
Mnemonics RCALL ICALL(1) EICALL(1) CALL(1) RET RETI CPSE CP CPC CPI SBRC SBRS SBIC SBIS BRBS BRBC BREQ BRNE BRCS BRCC BRSH BRLO BRMI BRPL BRGE BRLT BRHS BRHC BRTS BRTC BRVS BRVC BRIE BRID
Operands k
Description Relative Call Subroutine Indirect Call to (Z) Extended Indirect Call to (Z)
Operation PC PC(15:0) PC(21:16) PC(15:0) PC(21:16) PC PC PC if (Rd = Rr) PC Rd - Rr Rd - Rr - C Rd - K if (Rr(b) = 0) PC if (Rr(b) = 1) PC if (I/O(A,b) = 0) PC If (I/O(A,b) =1) PC if (SREG(s) = 1) then PC if (SREG(s) = 0) then PC if (Z = 1) then PC if (Z = 0) then PC if (C = 1) then PC if (C = 0) then PC if (C = 0) then PC if (C = 1) then PC if (N = 1) then PC if (N = 0) then PC if (N V= 0) then PC if (N V= 1) then PC if (H = 1) then PC if (H = 0) then PC if (T = 1) then PC if (T = 0) then PC if (V = 1) then PC if (V = 0) then PC if (I = 1) then PC if (I = 0) then PC Data Transfer Instructions PC + 2 or 3 PC + 2 or 3 PC + 2 or 3 PC + 2 or 3 PC + k + 1 PC + k + 1 PC + k + 1 PC + k + 1 PC + k + 1 PC + k + 1 PC + k + 1 PC + k + 1 PC + k + 1 PC + k + 1 PC + k + 1 PC + k + 1 PC + k + 1 PC + k + 1 PC + k + 1 PC + k + 1 PC + k + 1 PC + k + 1 PC + k + 1 PC + k + 1 PC + k + 1 Z, 0 Z, EIND k STACK STACK PC + 2 or 3
Flags None None None None None I None Z,C,N,V,S,H Z,C,N,V,S,H Z,C,N,V,S,H None None None None None None None None None None None None None None None None None None None None None None None None
#Clocks 3 / 4(3)(5) 3 / 4(3) 4 (3) 4 / 5(3) 4 / 5(3) 4 / 5(3) 1/2/3 1 1 1 1/2/3 1/2/3 1/2/3 1/2/3 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2
Compare, Skip if Equal Compare Compare with Carry Compare with Immediate Skip if Bit in Register Cleared Skip if Bit in Register Set Skip if Bit in I/O Register Cleared Skip if Bit in I/O Register Set Branch if Status Flag Set Branch if Status Flag Cleared Branch if Equal Branch if Not Equal Branch if Carry Set Branch if Carry Cleared Branch if Same or Higher Branch if Lower Branch if Minus Branch if Plus Branch if Greater or Equal, Signed Branch if Less Than, Signed Branch if Half Carry Flag Set Branch if Half Carry Flag Cleared Branch if T Flag Set Branch if T Flag Cleared Branch if Overflow Flag is Set Branch if Overflow Flag is Cleared Branch if Interrupt Enabled Branch if Interrupt Disabled
2/3/4 2/3/4
Copy Register Copy Register Pair Load Immediate Load Direct from data space Load Indirect
Rd Rd+1:Rd Rd Rd Rd
1 1 1 1(5)/2(3) 1 2
(5) (3)
2(3)(4) 1(3)(4)
12
Operands Rd, X+ Rd, -X Rd, Y Rd, Y+ Rd, -Y Rd, Y+q Rd, Z Rd, Z+ Rd, -Z Rd, Z+q k, Rr X, Rr X+, Rr -X, Rr Y, Rr Y+, Rr -Y, Rr Y+q, Rr Z, Rr Z+, Rr -Z, Rr Z+q,Rr
Description Load Indirect and Post-Increment Load Indirect and Pre-Decrement Load Indirect Load Indirect and Post-Increment Load Indirect and Pre-Decrement Load Indirect with Displacement Load Indirect Load Indirect and Post-Increment Load Indirect and Pre-Decrement Load Indirect with Displacement Store Direct to Data Space Store Indirect Store Indirect and Post-Increment Store Indirect and Pre-Decrement Store Indirect Store Indirect and Post-Increment Store Indirect and Pre-Decrement Store Indirect with Displacement Store Indirect Store Indirect and Post-Increment Store Indirect and Pre-Decrement Store Indirect with Displacement Load Program Memory
Operation Rd X X X - 1, Rd (X) Rd (Y) Rd Y Y Rd Rd Rd Rd Z Z Rd Rd (k) (X) (X) X X (X) (Y) (Y) Y Y (Y) (Y + q) (Z) (Z) Z Z (Z + q) R0 Rd Rd Z R0 Rd Rd Z (RAMPZ:Z) (RAMPZ:Z) Z Rd I/O(A) STACK Rd (X) X+1 X-1 (X) (Y) (Y) Y+1 Y-1 (Y) (Y + q) (Z) (Z), Z+1 Z - 1, (Z) (Z + q) Rd Rr Rr, X+1 X - 1, Rr Rr Rr, Y+1 Y - 1, Rr Rr Rr Rr Z+1 Z-1 Rr (Z) (Z) (Z), Z+1 (RAMPZ:Z) (RAMPZ:Z) (RAMPZ:Z), Z+1 R1:R0 R1:R0, Z+2 I/O(A) Rr Rr STACK
Flags None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None
#Clocks 2(3) 2(3)/3(5) 1(5)/2(3) 2(3) 2(3)/3(5) 2(3) 1(5)/2(3) 2(3) 2(3)/3(5) 2(3) 1(5)/2(3) 1(5)/2(3) 1 /2 2(3) 1(5)/2(3) 1 /2 2(3) 2(3) 1 /2
(5) (3) (5) (3) (5) (3)
#Clocks XMEGA 1(3)(4) 2(3)(4) 1(3)(4) 1(3)(4) 2(3)(4) 2(3)(4) 1(3)(4) 1(3)(4) 2(3)(4) 2(3)(4) 2(3) 1(3) 1(3) 2(3) 1(3) 1(3) 2(3) 2(3) 1(3) 1(3) 2(3) 2(3) 3 3 3
ST(2) ST(2) ST
(2)
ST(2) STD(1) ST
(2)
1(5)/2(3) 2(3) 2 3 3 3 3 3 3 1 1 2 2
(3)
LPM(1)(2) LPM(1)(2) LPM(1)(2) ELPM(1) ELPM(1) ELPM(1) SPM(1) SPM(1) IN OUT PUSH(1) POP(1) Z+ Rd, A A, Rr Rr Rd Rd, Z Rd, Z+ Rd, Z Rd, Z+
Load Program Memory Load Program Memory and PostIncrement Extended Load Program Memory Extended Load Program Memory Extended Load Program Memory and Post-Increment Store Program Memory Store Program Memory and PostIncrement by 2 In From I/O Location Out To I/O Location Push Register on Stack Pop Register from Stack
1(3) 2(3)
13
0856IAVR07/10
Operands Z, Rd Z, Rd Z, Rd Z, Rd
Description Exchange Load and Set Load and Clear Load and Toggle
Operation (Z) Rd (Z) Rd (Z) Rd (Z) Rd Bit and Bit-test Instructions Rd, (Z) Rd v (Z) (Z) ($FF Rd) (Z) (Z) Rd (Z) (Z)
#Clocks 1 1 1 1
#Clocks XMEGA
LSL
Rd
Rd(n+1) Rd(0) C Rd(n) Rd(7) C Rd(0) Rd(n+1) C Rd(7) Rd(n) C Rd(n) Rd(3..0) SREG(s) SREG(s) I/O(A, b) I/O(A, b) T Rd(b) C C N N Z Z I I S S V V T T H H MCU Control Instructions
Rd(n), 0, Rd(7) Rd(n+1), 0, Rd(0) C, Rd(n), Rd(7) C, Rd(n+1), Rd(0) Rd(n+1), n=0..6 Rd(7..4) 1 0 1 0 Rr(b) T 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
Z,C,N,V,H
LSR
Rd
Z,C,N,V
ROL
Rd
Z,C,N,V,H
ROR
Rd
Z,C,N,V
ASR SWAP BSET BCLR SBI CBI BST BLD SEC CLC SEN CLN SEZ CLZ SEI CLI SES CLS SEV CLV SET CLT SEH CLH
Rd Rd s s A, b A, b Rr, b Rd, b
Arithmetic Shift Right Swap Nibbles Flag Set Flag Clear Set Bit in I/O Register Clear Bit in I/O Register Bit Store from Register to T Bit load from T to Register Set Carry Clear Carry Set Negative Flag Clear Negative Flag Set Zero Flag Clear Zero Flag Global Interrupt Enable Global Interrupt Disable Set Signed Test Flag Clear Signed Test Flag Set Twos Complement Overflow Clear Twos Complement Overflow Set T in SREG Clear T in SREG Set Half Carry Flag in SREG Clear Half Carry Flag in SREG
1 1 1 1 1(5)2 1 /2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
(5)
1 1
BREAK(1)
Break
None
14
Notes:
1. This instruction is not available in all devices. Refer to the device specific instruction set summary. 2. Not all variants of this instruction are available in all devices. Refer to the device specific instruction set summary. 3. Cycle times for Data memory accesses assume internal memory accesses, and are not valid for accesses via the external RAM interface. 4. One extra cycle must be added when accessing Internal SRAM. 5. Number of clock cycles for Reduced Core tinyAVR.
15
0856IAVR07/10
(i)
Rd Rd + Rr + C
Syntax: Operands: Program Counter:
(i)
ADC Rd,Rr
16-bit Opcode:
0001
0 d 31, 0 r 31
PC PC + 1
11rd
dddd
rrrr
H:
Rd3Rr3+Rr3R3+R3Rd3 Set if there was a carry from bit 3; cleared otherwise N V, For signed tests. Rd7Rr7R7+Rd7Rr7R7 Set if twos complement overflow resulted from the operation; cleared otherwise. R7 Set if MSB of the result is set; cleared otherwise. R7 R6 R5 R4 R3 R2 R1 R0 Set if the result is $00; cleared otherwise. Rd7Rr7+Rr7R7+R7Rd7 Set if there was carry from the MSB of the result; cleared otherwise.
S: V:
N:
Z:
C:
16
(i)
Rd Rd + Rr
Syntax: Operands: Program Counter:
(i)
ADD Rd,Rr
16-bit Opcode:
0000
0 d 31, 0 r 31
PC PC + 1
11rd
dddd
rrrr
H:
Rd3Rr3+Rr3R3+R3Rd3 Set if there was a carry from bit 3; cleared otherwise N V, For signed tests. Rd7Rr7R7+Rd7Rr7R7 Set if twos complement overflow resulted from the operation; cleared otherwise. R7 Set if MSB of the result is set; cleared otherwise. R7 R6 R5 R4 R3 R2 R1 R0 Set if the result is $00; cleared otherwise. Rd7 Rr7 +Rr7 R7+ R7 Rd7 Set if there was carry from the MSB of the result; cleared otherwise.
S: V:
N:
Z:
C:
17
0856IAVR07/10
(i)
Rd+1:Rd Rd+1:Rd + K
Syntax: Operands: Program Counter:
(i)
ADIW Rd+1:Rd,K
16-bit Opcode:
1001
d {24,26,28,30}, 0 K 63
PC PC + 1
0110
KKdd
KKKK
S: V:
N V, For signed tests. Rdh7 R15 Set if twos complement overflow resulted from the operation; cleared otherwise. R15 Set if MSB of the result is set; cleared otherwise. R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 Set if the result is $0000; cleared otherwise. R15 Rdh7 Set if there was carry from the MSB of the result; cleared otherwise.
N:
Z:
C:
18
(i)
Rd Rd Rr
Syntax: Operands: Program Counter:
(i)
AND Rd,Rr
16-bit Opcode:
0010
0 d 31, 0 r 31
PC PC + 1
00rd
dddd
rrrr
S: V:
N V, For signed tests. 0 Cleared R7 Set if MSB of the result is set; cleared otherwise. R7 R6 R5 R4 R3 R2 R1 R0 Set if the result is $00; cleared otherwise.
N:
Z:
19
0856IAVR07/10
(i)
Rd Rd K
Syntax: Operands: Program Counter:
(i)
ANDI Rd,K
16-bit Opcode:
0111
16 d 31, 0 K 255
PC PC + 1
KKKK
dddd
KKKK
S: V:
N V, For signed tests. 0 Cleared R7 Set if MSB of the result is set; cleared otherwise. R7 R6 R5R4 R3 R2 R1 R0 Set if the result is $00; cleared otherwise.
N:
Z:
20
(i)
b7-------------------b0
Syntax:
C
Operands: Program Counter:
(i)
ASR Rd
16-bit Opcode:
1001
0 d 31
PC PC + 1
010d
dddd
0101
S: V: N:
N V, For signed tests. N C (For N and C after the shift) R7 Set if MSB of the result is set; cleared otherwise. R7 R6 R5 R4 R3 R2 R1 R0 Set if the result is $00; cleared otherwise. Rd0 Set if, before the shift, the LSB of Rd was set; cleared otherwise.
Z:
C:
21
0856IAVR07/10
(i)
SREG(s) 0
Syntax: Operands: Program Counter:
(i)
BCLR s
16-bit Opcode:
1001
0s7
PC PC + 1
0100
1sss
1000
I: T: H: S: V: N: Z: C:
0 if s = 7; Unchanged otherwise. 0 if s = 6; Unchanged otherwise. 0 if s = 5; Unchanged otherwise. 0 if s = 4; Unchanged otherwise. 0 if s = 3; Unchanged otherwise. 0 if s = 2; Unchanged otherwise. 0 if s = 1; Unchanged otherwise. 0 if s = 0; Unchanged otherwise.
Example:
bclr bclr 0 7 ; Clear Carry Flag ; Disable interrupts
22
(i)
Rd(b) T
Syntax: Operands: Program Counter:
(i)
BLD Rd,b
16 bit Opcode:
1111
0 d 31, 0 b 7
PC PC + 1
100d
dddd
0bbb
Example:
; Copy bit bst bld r1,2 r0,4 ; Store bit 2 of r1 in T Flag ; Load T Flag into bit 4 of r0
23
0856IAVR07/10
(i)
Syntax:
Operands:
Program Counter:
(i)
BRBC s,k
0 s 7, -64 k +63
PC PC + k + 1 PC PC + 1, if condition is false
16-bit Opcode:
1111 01kk kkkk ksss
Example:
cpi ...
r20,5
; Compare r20 to the value 5 ; Branch if Zero Flag cleared ; Branch destination (do nothing)
24
(i)
Syntax:
Operands:
Program Counter:
(i)
BRBS s,k
0 s 7, -64 k +63
PC PC + k + 1 PC PC + 1, if condition is false
16-bit Opcode:
1111 00kk kkkk ksss
Example:
r0,3
brbs 6,bitset ; Branch T bit was set ; Branch destination (do nothing)
25
0856IAVR07/10
(i)
If C = 0 then PC PC + k + 1, else PC PC + 1
Syntax:
Operands:
Program Counter:
(i)
BRCC k
-64 k +63
PC PC + k + 1 PC PC + 1, if condition is false
16-bit Opcode:
1111 01kk kkkk k000
Example:
r22,r23
; Add r23 to r22 ; Branch if carry cleared ; Branch destination (do nothing)
brcc nocarry
26
(i)
If C = 1 then PC PC + k + 1, else PC PC + 1
Syntax:
Operands:
Program Counter:
(i)
BRCS k
-64 k +63
PC PC + k + 1 PC PC + 1, if condition is false
16-bit Opcode:
1111 00kk kkkk k000
Example:
r26,$56
; Compare r26 with $56 ; Branch if carry set ; Branch destination (do nothing)
brcs carry
27
0856IAVR07/10
BREAK Break
Description: The BREAK instruction is used by the On-chip Debug system, and is normally not used in the application software. When the BREAK instruction is executed, the AVR CPU is set in the Stopped Mode. This gives the On-chip Debugger access to internal resources. If any Lock bits are set, or either the JTAGEN or OCDEN Fuses are unprogrammed, the CPU will treat the BREAK instruction as a NOP and will not enter the Stopped mode. This instruction is not available in all devices. Refer to the device specific instruction set summary.
Operation:
(i)
Syntax:
Operands:
Program Counter:
(i)
BREAK
16-bit Opcode:
1001
None
PC PC + 1
0101
1001
1000
28
(i)
If Rd = Rr (Z = 1) then PC PC + k + 1, else PC PC + 1
Syntax:
Operands:
Program Counter:
(i)
BREQ k
-64 k +63
PC PC + k + 1 PC PC + 1, if condition is false
16-bit Opcode:
1111 00kk kkkk k001
Example:
r1,r0
; Compare registers r1 and r0 ; Branch if registers equal ; Branch destination (do nothing)
breq equal
29
0856IAVR07/10
(i)
If Rd Rr (N V = 0) then PC PC + k + 1, else PC PC + 1
Syntax:
Operands:
Program Counter:
(i)
BRGE k
-64 k +63
PC PC + k + 1 PC PC + 1, if condition is false
16-bit Opcode:
1111 01kk kkkk k100
Example:
r11,r12
; Compare registers r11 and r12 ; Branch if r11 r12 (signed) ; Branch destination (do nothing)
brge greateq
30
(i)
If H = 0 then PC PC + k + 1, else PC PC + 1
Syntax:
Operands:
Program Counter:
(i)
BRHC k
-64 k +63
PC PC + k + 1 PC PC + 1, if condition is false
16-bit Opcode:
1111 01kk kkkk k101
Example:
31
0856IAVR07/10
(i)
If H = 1 then PC PC + k + 1, else PC PC + 1
Syntax:
Operands:
Program Counter:
(i)
BRHS k
16-bit Opcode:
1111
-64 k +63
PC PC + k + 1 PC PC + 1, if condition is false
k101
00kk
kkkk
Example:
hset
32
(i)
If I = 0 then PC PC + k + 1, else PC PC + 1
Syntax:
Operands:
Program Counter:
(i)
BRID k
-64 k +63
PC PC + k + 1 PC PC + 1, if condition is false
16-bit Opcode:
1111 01kk kkkk k111
Example:
33
0856IAVR07/10
(i)
If I = 1 then PC PC + k + 1, else PC PC + 1
Syntax: Operands: Program Counter:
(i)
BRIE k
-64 k +63
PC PC + k + 1 PC PC + 1, if condition is false
16-bit Opcode:
1111 00kk kkkk k111
Example:
inten
34
(i)
(i)
BRLO k
-64 k +63
PC PC + k + 1 PC PC + 1, if condition is false
16-bit Opcode:
1111 00kk kkkk k000
Example:
; Clear r19 ; Increase r19 ; Compare r19 with $10 ; Branch if r19 < $10 (unsigned) ; Exit from loop (do nothing)
brlo loop
35
0856IAVR07/10
(i)
Syntax:
Operands:
Program Counter:
(i)
BRLT k
-64 k +63
PC PC + k + 1 PC PC + 1, if condition is false
16-bit Opcode:
1111
00kk
kkkk
k100
Example:
r16,r1
; Compare r16 to r1 ; Branch if r16 < r1 (signed) ; Branch destination (do nothing)
brlt less
36
(i)
If N = 1 then PC PC + k + 1, else PC PC + 1
Syntax:
Operands:
Program Counter:
(i)
BRMI k
-64 k +63
PC PC + k + 1 PC PC + 1, if condition is false
16-bit Opcode:
1111 00kk kkkk k010
Example:
r18,4 negative
; Subtract 4 from r18 ; Branch if result negative ; Branch destination (do nothing)
37
0856IAVR07/10
(i)
If Rd Rr (Z = 0) then PC PC + k + 1, else PC PC + 1
Syntax:
Operands:
Program Counter:
(i)
BRNE k
-64 k +63
PC PC + k + 1 PC PC + 1, if condition is false
16-bit Opcode:
1111 01kk kkkk k001
Example:
; Clear r27 ; Increase r27 ; Compare r27 to 5 ; Branch if r27<>5 ; Loop exit (do nothing)
38
(i)
If N = 0 then PC PC + k + 1, else PC PC + 1
Syntax:
Operands:
Program Counter:
(i)
BRPL k
-64 k +63
PC PC + k + 1 PC PC + 1, if condition is false
16-bit Opcode:
1111 01kk kkkk k010
Example:
; Subtract $50 from r26 ; Branch if r26 positive ; Branch destination (do nothing)
39
0856IAVR07/10
(i)
If Rd Rr (C = 0) then PC PC + k + 1, else PC PC + 1
Syntax:
Operands:
Program Counter:
(i)
BRSH k
-64 k +63
PC PC + k + 1 PC PC + 1, if condition is false
16-bit Opcode:
1111 01kk kkkk k000
Example:
; Subtract 4 from r19 ; Branch if r19 >= 4 (unsigned) ; Branch destination (do nothing)
40
(i)
If T = 0 then PC PC + k + 1, else PC PC + 1
Syntax:
Operands:
Program Counter:
(i)
BRTC k
-64 k +63
PC PC + k + 1 PC PC + 1, if condition is false
16-bit Opcode:
1111 01kk kkkk k110
Example:
r3,5 tclear
; Store bit 5 of r3 in T Flag ; Branch if this bit was cleared ; Branch destination (do nothing)
41
0856IAVR07/10
(i)
If T = 1 then PC PC + k + 1, else PC PC + 1
Syntax:
Operands:
Program Counter:
(i)
BRTS k
-64 k +63
PC PC + k + 1 PC PC + 1, if condition is false
16-bit Opcode:
1111 00kk kkkk k110
Example:
r3,5
; Store bit 5 of r3 in T Flag ; Branch if this bit was set ; Branch destination (do nothing)
brts tset
42
(i)
If V = 0 then PC PC + k + 1, else PC PC + 1
Syntax:
Operands:
Program Counter:
(i)
BRVC k
-64 k +63
PC PC + k + 1 PC PC + 1, if condition is false
16-bit Opcode:
1111 01kk kkkk k011
Example:
r3,r4
brvc noover
43
0856IAVR07/10
(i)
If V = 1 then PC PC + k + 1, else PC PC + 1
Syntax:
Operands:
Program Counter:
(i)
BRVS k
-64 k +63
PC PC + k + 1 PC PC + 1, if condition is false
16-bit Opcode:
1111 00kk kkkk k011
Example:
r3,r4 overfl
44
(i)
SREG(s) 1
Syntax: Operands: Program Counter:
(i)
BSET s
16-bit Opcode:
1001
0s7
PC PC + 1
0100
0sss
1000
I: T: H: S: V: N: Z: C:
1 if s = 7; Unchanged otherwise. 1 if s = 6; Unchanged otherwise. 1 if s = 5; Unchanged otherwise. 1 if s = 4; Unchanged otherwise. 1 if s = 3; Unchanged otherwise. 1 if s = 2; Unchanged otherwise. 1 if s = 1; Unchanged otherwise. 1 if s = 0; Unchanged otherwise.
Example:
bset bset 6 7 ; Set T Flag ; Enable interrupt
45
0856IAVR07/10
(i)
T Rd(b)
Syntax: Operands: Program Counter:
(i)
BST Rd,b
16-bit Opcode:
1111
0 d 31, 0 b 7
PC PC + 1
101d
dddd
0bbb
T:
Example:
; Copy bit bst bld r1,2 r0,4 ; Store bit 2 of r1 in T Flag ; Load T into bit 4 of r0
46
(i) (ii)
PC k PC k
Syntax:
Devices with 16 bits PC, 128K bytes Program memory maximum. Devices with 22 bits PC, 8M bytes Program memory maximum.
Operands: Program Counter Stack:
(i)
CALL k
PC k PC k
STACK PC+2 SP SP-2, (2 bytes, 16 bits) STACK PC+2 SP SP-3 (3 bytes, 22 bits)
(ii)
CALL k
32-bit Opcode:
1001 kkkk 010k kkkk kkkk kkkk 111k kkkk
Example:
mov call nop ... check: cpi breq ret ... error: rjmp
r16,r0 check
r16,$42 error
; Check if r16 has a special value ; Branch if equal ; Return from subroutine
error
; Infinite loop
2 (4 bytes) 4, devices with 16 bit PC 5, devices with 22 bit PC 3, devices with 16 bit PC 4, devices with 22 bit PC
47
0856IAVR07/10
(i)
I/O(A,b) 0
Syntax: Operands: Program Counter:
(i)
CBI A,b
16-bit Opcode:
1001
0 A 31, 0 b 7
PC PC + 1
1000
AAAA
Abbb
Example:
cbi
$12,7
1 (2 bytes) 2 1 1
48
(i)
Rd Rd ($FF - K)
Syntax: Operands: Program Counter:
(i)
CBR Rd,K
16 d 31, 0 K 255
PC PC + 1
S: V:
N V, For signed tests. 0 Cleared R7 Set if MSB of the result is set; cleared otherwise. R7 R6 R5 R4 R3 R2 R1 R0 Set if the result is $00; cleared otherwise.
N:
Z:
49
0856IAVR07/10
(i)
C0
Syntax: Operands: Program Counter:
(i)
CLC
16-bit Opcode:
1001
None
PC PC + 1
0100
1000
1000
C:
Example:
add clc r0,r0 ; Add r0 to itself ; Clear Carry Flag
50
(i)
H0
Syntax: Operands: Program Counter:
(i)
CLH
16-bit Opcode:
1001
None
PC PC + 1
0100
1101
1000
H:
Example:
clh ; Clear the Half Carry Flag
51
0856IAVR07/10
(i)
I0
Syntax: Operands: Program Counter:
(i)
CLI
16-bit Opcode:
1001
None
PC PC + 1
0100
1111
1000
I:
Example:
in cli sbi sbi out EECR, EEWE SREG, temp ; Restore SREG value (I-Flag) temp, SREG ; Store SREG value (temp must be defined by user) ; Disable interrupts during timed sequence EECR, EEMWE ; Start EEPROM write
52
(i)
N0
Syntax: Operands: Program Counter:
(i)
CLN
16-bit Opcode:
1001
None
PC PC + 1
0100
1010
1000
N:
Example:
add cln r2,r3 ; Add r3 to r2 ; Clear Negative Flag
53
0856IAVR07/10
(i)
Rd Rd Rd
Syntax: Operands: Program Counter:
(i)
CLR Rd
0 d 31
PC PC + 1
S:
V:
N:
Z:
54
(i)
S0
Syntax: Operands: Program Counter:
(i)
CLS
16-bit Opcode:
1001
None
PC PC + 1
0100
1100
1000
S:
Example:
add cls r2,r3 ; Add r3 to r2 ; Clear Signed Flag
55
0856IAVR07/10
(i)
T0
Syntax: Operands: Program Counter:
(i)
CLT
16-bit Opcode:
1001
None
PC PC + 1
0100
1110
1000
T:
0 T Flag cleared
Example:
clt ; Clear T Flag
56
(i)
V0
Syntax: Operands: Program Counter:
(i)
CLV
16-bit Opcode:
1001
None
PC PC + 1
0100
1011
1000
V:
Example:
add clv r2,r3 ; Add r3 to r2 ; Clear Overflow Flag
57
0856IAVR07/10
(i)
Z0
Syntax: Operands: Program Counter:
(i)
CLZ
16-bit Opcode:
1001
None
PC PC + 1
0100
1001
1000
Z:
Example:
add clz r2,r3 ; Add r3 to r2 ; Clear zero
58
(i)
Rd $FF - Rd
Syntax: Operands: Program Counter:
(i)
COM Rd
16-bit Opcode:
1001
0 d 31
PC PC + 1
010d
dddd
0000
S:
NV For signed tests. 0 Cleared. R7 Set if MSB of the result is set; cleared otherwise. R7 R6 R5 R4 R3 R2 R1 R0 Set if the result is $00; Cleared otherwise. 1 Set.
V:
N:
Z:
C:
59
0856IAVR07/10
CP Compare
Description: This instruction performs a compare between two registers Rd and Rr. None of the registers are changed. All conditional branches can be used after this instruction.
Operation:
(i)
Rd - Rr
Syntax: Operands: Program Counter:
(i)
CP Rd,Rr
16-bit Opcode:
0001
0 d 31, 0 r 31
PC PC + 1
01rd
dddd
rrrr
H:
Rd3 Rr3+ Rr3 R3 +R3 Rd3 Set if there was a borrow from bit 3; cleared otherwise N V, For signed tests. Rd7 Rr7 R7+ Rd7 Rr7 R7 Set if twos complement overflow resulted from the operation; cleared otherwise. R7 Set if MSB of the result is set; cleared otherwise. R7 R6 R5 R4 R3 R2 R1 R0 Set if the result is $00; cleared otherwise. Rd7 Rr7+ Rr7 R7 +R7 Rd7 Set if the absolute value of the contents of Rr is larger than the absolute value of Rd; cleared otherwise.
S: V:
N:
Z:
C:
60
(i)
Rd - Rr - C
Syntax: Operands: Program Counter:
(i)
CPC Rd,Rr
16-bit Opcode:
0000
0 d 31, 0 r 31
PC PC + 1
01rd
dddd
rrrr
H:
Rd3 Rr3+ Rr3 R3 +R3 Rd3 Set if there was a borrow from bit 3; cleared otherwise N V, For signed tests. Rd7 Rr7 R7+ Rd7 Rr7 R7 Set if twos complement overflow resulted from the operation; cleared otherwise. R7 Set if MSB of the result is set; cleared otherwise. R7 R6 R5 R4 R3 R2 R1 R0 Z Previous value remains unchanged when the result is zero; cleared otherwise. Rd7 Rr7+ Rr7 R7 +R7 Rd7 Set if the absolute value of the contents of Rr plus previous carry is larger than the absolute value of Rd; cleared otherwise.
S: V:
N:
Z:
C:
61
0856IAVR07/10
62
(i)
Rd - K
Syntax: Operands: Program Counter:
(i)
CPI Rd,K
16-bit Opcode:
0011
16 d 31, 0 K 255
PC PC + 1
KKKK
dddd
KKKK
H:
Rd3 K3+ K3 R3+ R3 Rd3 Set if there was a borrow from bit 3; cleared otherwise N V, For signed tests. Rd7 K7 R7 +Rd7 K7 R7 Set if twos complement overflow resulted from the operation; cleared otherwise. R7 Set if MSB of the result is set; cleared otherwise. R7 R6 R5 R4 R3 R2 R1 R0 Set if the result is $00; cleared otherwise. Rd7 K7 +K7 R7+ R7 Rd7 Set if the absolute value of K is larger than the absolute value of Rd; cleared otherwise.
S: V:
N:
Z:
C:
63
0856IAVR07/10
(i)
(i)
CPSE Rd,Rr
0 d 31, 0 r 31
PC PC + 1, Condition false - no skip PC PC + 2, Skip a one word instruction PC PC + 3, Skip a two word instruction
16-bit Opcode:
0001 00rd dddd rrrr
Example:
inc cpse neg nop r4 r4,r0 r4 ; Increase r4 ; Compare r4 to r0 ; Only executed if r4<>r0 ; Continue (do nothing)
Words: 1 (2 bytes) Cycles: 1 if condition is false (no skip) 2 if condition is true (skip is executed) and the instruction skipped is 1 word 3 if condition is true (skip is executed) and the instruction skipped is 2 words
64
(i)
Rd Rd - 1
Syntax: Operands: Program Counter:
(i)
DEC Rd
16-bit Opcode:
1001
0 d 31
PC PC + 1
010d
dddd
1010
S:
NV For signed tests. R7 R6 R5 R4 R3 R2 R1 R0 Set if twos complement overflow resulted from the operation; cleared otherwise. Twos complement overflow occurs if and only if Rd was $80 before the operation. R7 Set if MSB of the result is set; cleared otherwise. R7 R6 R5 R4 R3 R2 R1 R0 Set if the result is $00; Cleared otherwise.
V:
N:
Z:
brne loop
65
0856IAVR07/10
The DES algorithm is described in "Specifications for the Data Encryption Standard" (Federal Information Processing Standards Publication 46). Intermediate results in this implementation differ from the standard because the initial permutation and the inverse initial permutation are performed each iteration. This does not affect the result in the final ciphertext or plaintext, but reduces execution time.
Operation:
(i)
If H = 0 then If H = 1 then
Syntax:
(i)
DES K
16-bit Opcode:
1001
0x00K 0x0F
PC PC + 1
0100
KKKK
1011
Example:
DES 0x00 DES 0x01 DES 0x0E DES 0x0F
Words: 1 Cycles: 1 (2(1)) Note: 1. If the DES instruction is succeeding a non-DES instruction, an extra cycle is inserted.
66
(i)
(i)
EICALL
None
See Operation
16-bit Opcode:
1001 0101 0001 1001
Example:
ldi out ldi ldi eicall r16,$05 EIND,r16 r30,$00 r31,$10 ; Call to $051000 ; Set up EIND and Z-pointer
1 (2 bytes) 4 (only implemented in devices with 22 bit PC) 3 (only implemented in devices with 22 bit PC)
67
0856IAVR07/10
(i)
(i)
EIJMP
16-bit Opcode:
1001
None
See Operation
Not Affected
0100
0001
1001
Example:
ldi out ldi ldi eijmp r16,$05 EIND,r16 r30,$00 r31,$10 ; Jump to $051000 ; Set up EIND and Z-pointer
68
(RAMPZ:Z) (RAMPZ:Z) + 1
Operands:
RAMPZ:Z: Unchanged, R0 implied destination register RAMPZ:Z: Unchanged RAMPZ:Z: Post incremented
Program Counter:
None, R0 implied 0 d 31 0 d 31
PC PC + 1 PC PC + 1 PC PC + 1
Example:
ldi out ldi ldi ZL, byte3(Table_1<<1); Initialize Z-pointer RAMPZ, ZL ZH, byte2(Table_1<<1) ZL, byte1(Table_1<<1) ; Load constant from Program ; memory pointed to by RAMPZ:Z (Z is r31:r30) ... Table_1: .dw 0x3738 ; 0x38 is addressed when ZLSB = 0 ; 0x37 is addressed when ZLSB = 1
elpm r16, Z+
69
0856IAVR07/10
...
70
(i)
Rd Rd Rr
Syntax: Operands: Program Counter:
(i)
EOR Rd,Rr
16-bit Opcode:
0010
0 d 31, 0 r 31
PC PC + 1
01rd
dddd
rrrr
S: V:
N V, For signed tests. 0 Cleared R7 Set if MSB of the result is set; cleared otherwise. R7 R6 R5 R4 R3 R2 R1 R0 Set if the result is $00; cleared otherwise.
N:
Z:
71
0856IAVR07/10
Multiplier 8
Let (N.Q) denote a fractional number with N binary digits left of the radix point, and Q binary digits right of the radix point. A multiplication between two numbers in the formats (N1.Q1) and (N2.Q2) results in the format ((N1+N2).(Q1+Q2)). For signal processing applications, the format (1.7) is widely used for the inputs, resulting in a (2.14) format for the product. A left shift is required for the high byte of the product to be in the same format as the inputs. The FMUL instruction incorporates the shift operation in the same number of cycles as MUL. The (1.7) format is most commonly used with signed numbers, while FMUL performs an unsigned multiplication. This instruction is therefore most useful for calculating one of the partial products when performing a signed multiplication with 16-bit inputs in the (1.15) format, yielding a result in the (1.31) format. Note: the result of the FMUL operation may suffer from a 2s complement overflow if interpreted as a number in the (1.15) format. The MSB of the multiplication before shifting must be taken into account, and is found in the carry bit. See the following example. The multiplicand Rd and the multiplier Rr are two registers containing unsigned fractional numbers where the implicit radix point lies between bit 6 and bit 7. The 16-bit unsigned fractional product with the implicit radix point between bit 14 and bit 15 is placed in R1 (high byte) and R0 (low byte). This instruction is not available in all devices. Refer to the device specific instruction set summary.
Operation:
(i)
R1:R0 Rd Rr
Syntax:
(i)
FMUL Rd,Rr
16-bit Opcode:
0000 0011
16 d 23, 16 r 23
PC PC + 1
0ddd
1rrr
C:
R16 Set if bit 15 of the result before left shift is set; cleared otherwise. R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 Set if the result is $0000; cleared otherwise.
Z:
72
73
0856IAVR07/10
Multiplier 8
Product High
Let (N.Q) denote a fractional number with N binary digits left of the radix point, and Q binary digits right of the radix point. A multiplication between two numbers in the formats (N1.Q1) and (N2.Q2) results in the format ((N1+N2).(Q1+Q2)). For signal processing applications, the format (1.7) is widely used for the inputs, resulting in a (2.14) format for the product. A left shift is required for the high byte of the product to be in the same format as the inputs. The FMULS instruction incorporates the shift operation in the same number of cycles as MULS. The multiplicand Rd and the multiplier Rr are two registers containing signed fractional numbers where the implicit radix point lies between bit 6 and bit 7. The 16-bit signed fractional product with the implicit radix point between bit 14 and bit 15 is placed in R1 (high byte) and R0 (low byte). Note that when multiplying 0x80 (-1) with 0x80 (-1), the result of the shift operation is 0x8000 (-1). The shift operation thus gives a twos complement overflow. This must be checked and handled by software. This instruction is not available in all devices. Refer to the device specific instruction set summary.
Operation:
(i)
R1:R0 Rd Rr
Syntax:
(i)
FMULS Rd,Rr
16-bit Opcode:
0000 0011
16 d 23, 16 r 23
PC PC + 1
1ddd
0rrr
C:
R16 Set if bit 15 of the result before left shift is set; cleared otherwise. R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 Set if the result is $0000; cleared otherwise.
Z:
74
75
0856IAVR07/10
Multiplier 8
Product High
Let (N.Q) denote a fractional number with N binary digits left of the radix point, and Q binary digits right of the radix point. A multiplication between two numbers in the formats (N1.Q1) and (N2.Q2) results in the format ((N1+N2).(Q1+Q2)). For signal processing applications, the format (1.7) is widely used for the inputs, resulting in a (2.14) format for the product. A left shift is required for the high byte of the product to be in the same format as the inputs. The FMULSU instruction incorporates the shift operation in the same number of cycles as MULSU. The (1.7) format is most commonly used with signed numbers, while FMULSU performs a multiplication with one unsigned and one signed input. This instruction is therefore most useful for calculating two of the partial products when performing a signed multiplication with 16-bit inputs in the (1.15) format, yielding a result in the (1.31) format. Note: the result of the FMULSU operation may suffer from a 2's complement overflow if interpreted as a number in the (1.15) format. The MSB of the multiplication before shifting must be taken into account, and is found in the carry bit. See the following example. The multiplicand Rd and the multiplier Rr are two registers containing fractional numbers where the implicit radix point lies between bit 6 and bit 7. The multiplicand Rd is a signed fractional number, and the multiplier Rr is an unsigned fractional number. The 16-bit signed fractional product with the implicit radix point between bit 14 and bit 15 is placed in R1 (high byte) and R0 (low byte). This instruction is not available in all devices. Refer to the device specific instruction set summary.
Operation:
(i)
R1:R0 Rd Rr
Syntax:
(i)
FMULSU Rd,Rr
16-bit Opcode:
0000 0011
16 d 23, 16 r 23
PC PC + 1
1ddd
1rrr
C:
R16 Set if bit 15 of the result before left shift is set; cleared otherwise. R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 Set if the result is $0000; cleared otherwise.
Z:
76
77
0856IAVR07/10
(i) (ii)
PC(15:0) Z(15:0) Devices with 16 bits PC, 128K bytes Program memory maximum. PC(15:0) Z(15:0) Devices with 22 bits PC, 8M bytes Program memory maximum. PC(21:16) 0
Syntax: Operands: Program Counter: Stack:
(i)
ICALL
None
See Operation
(ii)
ICALL
None
See Operation
16-bit Opcode:
1001 0101 0000 1001
Example:
mov icall r30,r0 ; Set offset to call table ; Call routine pointed to by r31:r30
1 (2 bytes) 3, devices with 16 bit PC 4, devices with 22 bit PC 2, devices with 16 bit PC 3, devices with 22 bit PC
78
(i) (ii)
PC Z(15:0) Devices with 16 bits PC, 128K bytes Program memory maximum. PC(15:0) Z(15:0) Devices with 22 bits PC, 8M bytes Program memory maximum. PC(21:16) 0
Syntax: Operands: Program Counter: Stack:
(i),(ii)
IJMP
16-bit Opcode:
1001 0100
None
See Operation
Not Affected
0000
1001
Example:
mov ijmp r30,r0 ; Set offset to jump table ; Jump to routine pointed to by r31:r30
79
0856IAVR07/10
(i)
Rd I/O(A)
Syntax: Operands: Program Counter:
(i)
IN Rd,A
16-bit Opcode:
1011 0AAd
0 d 31, 0 A 63
PC PC + 1
dddd
AAAA
Example:
in cpi breq ... exit: nop ; Branch destination (do nothing) r25,$16 r25,4 exit ; Read Port B ; Compare read value to constant ; Branch if r25=4
80
(i)
Rd Rd + 1
Syntax: Operands: Program Counter:
(i)
INC Rd
16-bit Opcode:
1001 010d
0 d 31
PC PC + 1
dddd
0011
S:
NV For signed tests. R7 R6 R5 R4 R3 R2 R1 R0 Set if twos complement overflow resulted from the operation; cleared otherwise. Twos complement overflow occurs if and only if Rd was $7F before the operation. R7 Set if MSB of the result is set; cleared otherwise. R7 R6 R5 R4R3 R2 R1 R0 Set if the result is $00; Cleared otherwise.
V:
N:
Z:
81
0856IAVR07/10
82
(i)
PC k
Syntax: Operands: Program Counter: Stack:
(i)
JMP k
32-bit Opcode:
1001 kkkk 010k kkkk
0 k < 4M
PC k
Unchanged
kkkk kkkk
110k kkkk
Example:
mov jmp ... farplc: nop ; Jump destination (do nothing) r1,r0 farplc ; Copy r0 to r1 ; Unconditional jump
83
0856IAVR07/10
(i)
(i)
LAC Z,Rd
16-bit Opcode:
1001 001r
0 d 31
PC PC + 1
rrrr
0110
84
(i)
(i)
LAS Z,Rd
16-bit Opcode:
1001 001r
0 d 31
PC PC + 1
rrrr
0101
85
0856IAVR07/10
(i)
(i)
LAT Z,Rd
16-bit Opcode:
1001 001r
0 d 31
PC PC + 1
rrrr
0111
86
XX+1 Rd (X)
Operands:
0 d 31 0 d 31 0 d 31
PC PC + 1 PC PC + 1 PC PC + 1
87
0856IAVR07/10
16-bit Opcode:
(i) (ii) (iii) 1001 1001 1001 000d 000d 000d dddd dddd dddd 1100 1101 1110
88
(i) 1(2) (ii) 2 (iii) 3(2) Cycles XMEGA: (i) 1(1) (ii) 1(1) (iii) 2(1) Notes: 1. IF the LD instruction is accessing internal SRAM, one extra cycle is inserted. 2. LD instruction can load data from program memory since the flash is memory mapped. Loading data from the data memory takes 1 clock cycle, and loading from the program memory takes 2 clock cycles. But if an interrupt occur (before the last clock cycle) no additional clock cycles is necessary when loading from the program memory. Hence, the instruction takes only 1 clock cycle to execute. LD instruction with pre-decrement can load data from program memory since the flash is memory mapped. Loading data from the data memory takes 2 clock cycles, and loading from the program memory takes 3 clock cycles. But if an interrupt occur (before the last clock cycle) no additional clock cycles is necessary when loading from the program memory. Hence, the instruction takes only 1 clock cycle to execute.
89
0856IAVR07/10
YY+1 Rd (Y)
Operands:
0 d 31 0 d 31 0 d 31 0 d 31, 0 q 63
PC PC + 1 PC PC + 1 PC PC + 1 PC PC + 1
90
Example:
clr ldi ld ld ldi ld ld ldd r29 r28,$60 r0,Y+ r1,Y r28,$63 r2,Y r3,-Y r4,Y+2 ; Clear Y high byte ; Set Y low byte to $60 ; Load r0 with data space loc. $60(Y post inc) ; Load r1 with data space loc. $61 ; Set Y low byte to $63 ; Load r2 with data space loc. $63 ; Load r3 with data space loc. $62(Y pre dec) ; Load r4 with data space loc. $64
(i) 1(2) (ii) 2 (iii) 3(2) Cycles XMEGA: (i) 1(1) (ii) 1(1) (iii) 2(1) (iv) 2(1) Notes: 1. IF the LD instruction is accessing internal SRAM, one extra cycle is inserted. 2. LD instruction can load data from program memory since the flash is memory mapped. Loading data from the data memory takes 1 clock cycle, and loading from the program memory takes 2 clock cycles. But if an interrupt occur (before the last clock cycle) no additional clock cycles is necessary when loading from the program memory. Hence, the instruction takes only 1 clock cycle to execute. LD instruction with pre-decrement can load data from program memory since the flash is memory mapped. Loading data from the data memory takes 2 clock cycles, and loading from the program memory takes 3 clock cycles. But if an interrupt occur (before the last clock cycle) no additional clock cycles is necessary when loading from the program memory. Hence, the instruction takes only 1 clock cycle to execute.
91
0856IAVR07/10
ZZ+1 Rd (Z)
Operands:
0 d 31 0 d 31 0 d 31 0 d 31, 0 q 63
PC PC + 1 PC PC + 1 PC PC + 1 PC PC + 1
92
(i) 1(2) (ii) 2 (iii) 3(2) Cycles XMEGA: (i) 1(1) (ii) 1(1) (iii) 2(1) (iv) 2(1) Notes: 1. IF the LD instruction is accessing internal SRAM, one extra cycle is inserted. 2. LD instruction can load data from program memory since the flash is memory mapped. Loading data from the data memory takes 1 clock cycle, and loading from the program memory takes 2 clock cycles. But if an interrupt occur (before the last clock cycle) no additional clock cycles is necessary when loading from the program memory. Hence, the instruction takes only 1 clock cycle to execute. LD instruction with pre-decrement can load data from program memory since the flash is memory mapped. Loading data from the data memory takes 2 clock cycles, and loading from the program memory takes 3 clock cycles. But if an interrupt occur (before the last clock cycle) no additional clock cycles is necessary when loading from the program memory. Hence, the instruction takes only 1 clock cycle to execute.
93
0856IAVR07/10
(i)
Rd K
Syntax: Operands: Program Counter:
(i)
LDI Rd,K
16-bit Opcode:
1110 KKKK
16 d 31, 0 K 255
PC PC + 1
dddd
KKKK
Example:
clr ldi lpm r31 r30,$F0 ; Clear Z high byte ; Set Z low byte to $F0 ; Load constant from Program ; memory pointed to by Z
94
(i)
Rd (k)
Syntax: Operands: Program Counter:
(i)
LDS Rd,k
32-bit Opcode:
1001 kkkk 000d kkkk
0 d 31, 0 k 65535
PC PC + 2
dddd kkkk
0000 kkkk
Example:
lds add sts r2,$FF00 r2,r1 $FF00,r2 ; Load r2 with the contents of data space location $FF00 ; add r1 to r2 ; Write back
2 2 If the LDS instruction is accessing internal SRAM, one extra cycle is inserted.
95
0856IAVR07/10
(i)
Rd (k)
Syntax: Operands: Program Counter:
(i)
LDS Rd,k
16-bit Opcode:
1010 0kkk
16 d 31, 0 k 127
PC PC + 1
dddd
kkkk
Example:
lds add sts r16,$00 r16,r17 $00,r16 ; Load r16 with the contents of data space location $00 ; add r17 to r16 ; Write result to the same address it was fetched from
96
ZZ+1
Operands:
None, R0 implied 0 d 31 0 d 31
PC PC + 1 PC PC + 1 PC PC + 1
Example:
ldi ldi lpm ... Table_1: .dw 0x5876 ... ; 0x76 is addresses when ZLSB = 0 ; 0x58 is addresses when ZLSB = 1 ZH, high(Table_1<<1); Initialize Z-pointer ZL, low(Table_1<<1) r16, Z ; Load constant from Program ; Memory pointed to by Z (r31:r30)
97
0856IAVR07/10
98
(i)
C
b7 - - - - - - - - - - - - - - - - - - b0
0
Program Counter:
Syntax:
Operands:
(i)
LSL Rd
0 d 31
PC PC + 1
H: S: V: N:
Rd3 N V, For signed tests. N C (For N and C after the shift) R7 Set if MSB of the result is set; cleared otherwise. R7 R6 R5 R4 R3 R2 R1 R0 Set if the result is $00; cleared otherwise. Rd7 Set if, before the shift, the MSB of Rd was set; cleared otherwise.
Z:
C:
99
0856IAVR07/10
Syntax:
Operands:
Program Counter:
(i)
LSR Rd
16-bit Opcode:
1001 010d
0 d 31
PC PC + 1
dddd
0110
S: V: N: Z:
N V, For signed tests. N C (For N and C after the shift) 0 R7 R6 R5 R4 R3 R2 R1 R0 Set if the result is $00; cleared otherwise. Rd0 Set if, before the shift, the LSB of Rd was set; cleared otherwise.
C:
100
(i)
Rd Rr
Syntax: Operands: Program Counter:
(i)
MOV Rd,Rr
16-bit Opcode:
0010 11rd
0 d 31, 0 r 31
PC PC + 1
dddd
rrrr
Example:
mov call ... check: cpi ... ret ; Return from subroutine r16,$11 ; Compare r16 to $11 r16,r0 check ; Copy r0 to r16 ; Call subroutine
101
0856IAVR07/10
(i)
Rd+1:Rd Rr+1:Rr
Syntax: Operands: Program Counter:
(i)
PC PC + 1
Example:
movw call ... check: cpi ... cpi ... ret ; Return from subroutine r17,$32 ; Compare r17 to $32 r16,$11 ; Compare r16 to $11 r17:16,r1:r0 ; Copy r1:r0 to r17:r16 check ; Call subroutine
102
Multiplier 8
Product High
The multiplicand Rd and the multiplier Rr are two registers containing unsigned numbers. The 16-bit unsigned product is placed in R1 (high byte) and R0 (low byte). Note that if the multiplicand or the multiplier is selected from R0 or R1 the result will overwrite those after multiplication. This instruction is not available in all devices. Refer to the device specific instruction set summary.
Operation:
(i)
R1:R0 Rd Rr
Syntax:
(i)
MUL Rd,Rr
16-bit Opcode:
1001 11rd
0 d 31, 0 r 31
PC PC + 1
dddd
rrrr
C:
R15 Set if bit 15 of the result is set; cleared otherwise. R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 Set if the result is $0000; cleared otherwise.
Z:
103
0856IAVR07/10
Multiplier 8
Product High
The multiplicand Rd and the multiplier Rr are two registers containing signed numbers. The 16-bit signed product is placed in R1 (high byte) and R0 (low byte). This instruction is not available in all devices. Refer to the device specific instruction set summary.
Operation:
(i)
R1:R0 Rd Rr
Syntax:
(i)
MULS Rd,Rr
16-bit Opcode:
0000 0010
16 d 31, 16 r 31
PC PC + 1
dddd
rrrr
C:
R15 Set if bit 15 of the result is set; cleared otherwise. R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 Set if the result is $0000; cleared otherwise.
Z:
104
Multiplier 8
Product High
The multiplicand Rd and the multiplier Rr are two registers. The multiplicand Rd is a signed number, and the multiplier Rr is unsigned. The 16-bit signed product is placed in R1 (high byte) and R0 (low byte). This instruction is not available in all devices. Refer to the device specific instruction set summary.
Operation:
(i)
R1:R0 Rd Rr
Syntax:
(i)
MULSU Rd,Rr
16-bit Opcode:
0000 0011
16 d 23, 16 r 23
PC PC + 1
0ddd
0rrr
C:
R15 Set if bit 15 of the result is set; cleared otherwise. R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 Set if the result is $0000; cleared otherwise.
Z:
105
0856IAVR07/10
movwr19:r18, r1:r0 mulr22, r20; al * bl movwr17:r16, r1:r0 mulsur23, r20; (signed)ah * bl sbcr19, r2 addr17, r0 adcr18, r1 adcr19, r2 mulsur21, r22; (signed)bh * al sbcr19, r2 addr17, r0 adcr18, r1 adcr19, r2 ret
106
(i)
Rd $00 - Rd
Syntax: Operands: Program Counter:
(i)
NEG Rd
16-bit Opcode:
1001 010d
0 d 31
PC PC + 1
dddd
0001
H:
R3 + Rd3 Set if there was a borrow from bit 3; cleared otherwise NV For signed tests. R7 R6 R5 R4 R3 R2 R1 R0 Set if there is a twos complement overflow from the implied subtraction from zero; cleared otherwise. A twos complement overflow will occur if and only if the contents of the Register after operation (Result) is $80. R7 Set if MSB of the result is set; cleared otherwise. R7 R6 R5 R4 R3 R2 R1 R0 Set if the result is $00; Cleared otherwise. R7 + R6 + R5 + R4 + R3 + R2 + R1 + R0 Set if there is a borrow in the implied subtraction from zero; cleared otherwise. The C Flag will be set in all cases except when the contents of Register after operation is $00.
S:
V:
N:
Z:
C:
107
0856IAVR07/10
NOP No Operation
Description: This instruction performs a single cycle No Operation.
Operation:
(i)
No
Syntax: Operands: Program Counter:
(i)
NOP
16-bit Opcode:
0000 0000
None
PC PC + 1
0000
0000
Example:
clr ser out nop out $18,r17 r16 r17 $18,r16 ; Clear r16 ; Set r17 ; Write zeros to Port B ; Wait (do nothing) ; Write ones to Port B
108
(i)
Rd Rd v Rr
Syntax: Operands: Program Counter:
(i)
OR Rd,Rr
16-bit Opcode:
0010 10rd
0 d 31, 0 r 31
PC PC + 1
dddd
rrrr
S: V:
N V, For signed tests. 0 Cleared R7 Set if MSB of the result is set; cleared otherwise. R7 R6 R5 R4 R3 R2 R1 R0 Set if the result is $00; cleared otherwise.
N:
Z:
109
0856IAVR07/10
(i)
Rd Rd v K
Syntax: Operands: Program Counter:
(i)
ORI Rd,K
16-bit Opcode:
0110 KKKK
16 d 31, 0 K 255
PC PC + 1
dddd
KKKK
S: V:
N V, For signed tests. 0 Cleared R7 Set if MSB of the result is set; cleared otherwise. R7 R6 R5 R4 R3 R2 R1 R0 Set if the result is $00; cleared otherwise.
N:
Z:
110
(i)
I/O(A) Rr
Syntax: Operands: Program Counter:
(i)
OUT A,Rr
16-bit Opcode:
1011 1AAr
0 r 31, 0 A 63
PC PC + 1
rrrr
AAAA
Example:
clr ser out nop out $18,r17 r16 r17 $18,r16 ; Clear r16 ; Set r17 ; Write zeros to Port B ; Wait (do nothing) ; Write ones to Port B
111
0856IAVR07/10
(i)
Rd STACK
Syntax: Operands: Program Counter: Stack:
(i)
POP Rd
16-bit Opcode:
1001 000d
0 d 31
PC PC + 1
SP SP + 1
dddd
1111
Example:
call ... routine: push push ... pop pop ret r13 r14 ; Restore r13 ; Restore r14 ; Return from subroutine r14 r13 ; Save r14 on the Stack ; Save r13 on the Stack routine ; Call subroutine
112
(i)
STACK Rr
Syntax: Operands: Program Counter: Stack:
(i)
PUSH Rr
16-bit Opcode:
1001 001d
0 r 31
PC PC + 1
SP SP - 1
dddd
1111
Example:
call ... routine: push push ... pop pop ret r13 r14 ; Restore r13 ; Restore r14 ; Return from subroutine r14 r13 ; Save r14 on the Stack ; Save r13 on the Stack routine ; Call subroutine
1 (2 bytes) 2 1
113
0856IAVR07/10
(i) (ii)
PC PC + k + 1 PC PC + k + 1
Syntax:
Devices with 16 bits PC, 128K bytes Program memory maximum. Devices with 22 bits PC, 8M bytes Program memory maximum.
Operands: Program Counter: Stack:
(i)
RCALL k
PC PC + k + 1 PC PC + k + 1
(ii)
RCALL k
16-bit Opcode:
1101 kkkk kkkk kkkk
Example:
rcall ... routine: push ... pop ret r14 ; Restore r14 ; Return from subroutine r14 ; Save r14 on the Stack routine ; Call subroutine
Words : Cycles :
1 (2 bytes) 3, devices with 16 bit PC 4, devices with 22 bit PC Cycles XMEGA: 2, devices with 16 bit PC 3, devices with 22 bit PC Cycles Reduced Core tinyAVR:4
114
(i) (ii)
PC(15:0) STACK Devices with 16 bits PC, 128K bytes Program memory maximum. PC(21:0) STACKDevices with 22 bits PC, 8M bytes Program memory maximum.
Syntax: Operands: Program Counter: Stack:
(i) (ii)
RET RET
16-bit Opcode:
1001 0101
None None
0000
1000
Example:
call ... routine: push ... pop ret r14 ; Restore r14 ; Return from subroutine r14 ; Save r14 on the Stack routine ; Call subroutine
115
0856IAVR07/10
(i) (ii)
PC(15:0) STACK Devices with 16 bits PC, 128K bytes Program memory maximum. PC(21:0) STACKDevices with 22 bits PC, 8M bytes Program memory maximum.
Syntax: Operands: Program Counter: Stack
(i) (ii)
RETI RETI
16-bit Opcode:
1001 0101
None None
0001
1000
I:
Example:
... extint: push ... pop reti r0 ; Restore r0 ; Return and enable interrupts r0 ; Save r0 on the Stack
116
(i)
PC PC + k + 1
Syntax: Operands: Program Counter: Stack
(i)
RJMP k
16-bit Opcode:
1100 kkkk
-2K k < 2K
PC PC + k + 1
Unchanged
kkkk
kkkk
Example:
cpi brne rjmp error: ok: add inc nop r16,$42 error ok r16,r17 r16 ; Compare r16 to $42 ; Branch if r16 <> $42 ; Unconditional branch ; Add r17 to r16 ; Increment r16 ; Destination for rjmp (do nothing)
117
0856IAVR07/10
C b7 - - - - - - - - - - - - - - - - - - b0
C
Program Counter:
Syntax:
Operands:
(i)
ROL Rd
0 d 31
PC PC + 1
H: S: V: N:
Rd3 N V, For signed tests. N C (For N and C after the shift) R7 Set if MSB of the result is set; cleared otherwise. R7 R6 R5 R4 R3 R2 R1 R0 Set if the result is $00; cleared otherwise. Rd7 Set if, before the shift, the MSB of Rd was set; cleared otherwise.
Z:
C:
brcs oneenc
118
Syntax:
Operands:
Program Counter:
(i)
ROR Rd
16-bit Opcode:
1001 010d
0 d 31
PC PC + 1
dddd
0111
S: V: N:
N V, For signed tests. N C (For N and C after the shift) R7 Set if MSB of the result is set; cleared otherwise. R7 R6 R5 R4 R3 R2 R1 R0 Set if the result is $00; cleared otherwise. Rd0 Set if, before the shift, the LSB of Rd was set; cleared otherwise.
Z:
C:
brcc zeroenc1
brcc zeroenc2
119
0856IAVR07/10
zeroenc1:
nop
120
(i)
Rd Rd - Rr - C
Syntax: Operands: Program Counter:
(i)
SBC Rd,Rr
0 d 31, 0 r 31
PC PC + 1
16-bit Opcode:
0000 10rd dddd rrrr
H:
Rd3 Rr3 + Rr3 R3 + R3 Rd3 Set if there was a borrow from bit 3; cleared otherwise N V, For signed tests. Rd7 Rr7 R7 +Rd7 Rr7 R7 Set if twos complement overflow resulted from the operation; cleared otherwise. R7 Set if MSB of the result is set; cleared otherwise. R7 R6 R5 R4 R3 R2 R1 R0 Z Previous value remains unchanged when the result is zero; cleared otherwise. Rd7 Rr7+ Rr7 R7 +R7 Rd7 Set if the absolute value of the contents of Rr plus previous carry is larger than the absolute value of the Rd; cleared otherwise.
S: V:
N:
Z:
C:
121
0856IAVR07/10
(i)
Rd Rd - K - C
Syntax: Operands: Program Counter:
(i)
SBCI Rd,K
16 d 31, 0 K 255
PC PC + 1
16-bit Opcode:
0100 KKKK dddd KKKK
H:
Rd3 K3 + K3 R3 + R3 Rd3 Set if there was a borrow from bit 3; cleared otherwise N V, For signed tests. Rd7 K7 R7 +Rd7 K7 R7 Set if twos complement overflow resulted from the operation; cleared otherwise. R7 Set if MSB of the result is set; cleared otherwise. R7 R6 R5 R4 R3 R2 R1 R0 Z Previous value remains unchanged when the result is zero; cleared otherwise. Rd7 K7+ K7 R7 +R7 Rd7 Set if the absolute value of the constant plus previous carry is larger than the absolute value of Rd; cleared otherwise.
S: V:
N:
Z:
C:
122
(i)
I/O(A,b) 1
Syntax: Operands: Program Counter:
(i)
SBI A,b
16-bit Opcode:
1001 1010
0 A 31, 0 b 7
PC PC + 1
AAAA
Abbb
Example:
out sbi in $1E,r0 $1C,0 r1,$1D ; Write EEPROM address ; Set read bit in EECR ; Read EEPROM data
123
0856IAVR07/10
(i)
(i)
SBIC A,b
0 A 31, 0 b 7
PC PC + 1, Condition false - no skip PC PC + 2, Skip a one word instruction PC PC + 3, Skip a two word instruction
16-bit Opcode:
1001 1001 AAAA Abbb
Example:
e2wait: sbic $1C,1 rjmp e2wait nop ; Skip next inst. if EEWE cleared ; EEPROM write not finished ; Continue (do nothing)
Words : Cycles :
Cycles XMEGA:
1 (2 bytes) 1 if condition is false (no skip) 2 if condition is true (skip is executed) and the instruction skipped is 1 word 3 if condition is true (skip is executed) and the instruction skipped is 2 words 2 if condition is false (no skip) 3 if condition is true (skip is executed) and the instruction skipped is 1 word 4 if condition is true (skip is executed) and the instruction skipped is 2 words
124
(i)
(i)
SBIS A,b
0 A 31, 0 b 7
PC PC + 1, Condition false - no skip PC PC + 2, Skip a one word instruction PC PC + 3, Skip a two word instruction
16-bit Opcode:
1001 1011 AAAA Abbb
Example:
waitset: sbis $10,0 rjmp waitset nop ; Skip next inst. if bit 0 in Port D set ; Bit not set ; Continue (do nothing)
Words : Cycles :
Cycles XMEGA:
1 (2 bytes) 1 if condition is false (no skip) 2 if condition is true (skip is executed) and the instruction skipped is 1 word 3 if condition is true (skip is executed) and the instruction skipped is 2 words 2 if condition is false (no skip) 3 if condition is true (skip is executed) and the instruction skipped is 1 word 4 if condition is true (skip is executed) and the instruction skipped is 2 words
125
0856IAVR07/10
(i)
Rd+1:Rd Rd+1:Rd - K
Syntax: Operands: Program Counter:
(i)
SBIW Rd+1:Rd,K
16-bit Opcode:
1001 0111
d {24,26,28,30}, 0 K 63
PC PC + 1
KKdd
KKKK
S: V:
N V, For signed tests. Rdh7 R15 Set if twos complement overflow resulted from the operation; cleared otherwise. R15 Set if MSB of the result is set; cleared otherwise. R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 Set if the result is $0000; cleared otherwise. R15 Rdh7 Set if the absolute value of K is larger than the absolute value of Rd; cleared otherwise.
N:
Z:
C:
126
(i)
Rd Rd v K
Syntax: Operands: Program Counter:
(i)
SBR Rd,K
16-bit Opcode:
0110 KKKK
16 d 31, 0 K 255
PC PC + 1
dddd
KKKK
S: V:
N V, For signed tests. 0 Cleared R7 Set if MSB of the result is set; cleared otherwise. R7 R6 R5 R4 R3 R2 R1 R0 Set if the result is $00; cleared otherwise.
N:
Z:
127
0856IAVR07/10
(i)
(i)
SBRC Rr,b
0 r 31, 0 b 7
PC PC + 1, Condition false - no skip PC PC + 2, Skip a one word instruction PC PC + 3, Skip a two word instruction
16-bit Opcode:
1111 110r rrrr 0bbb
Example:
sub sub nop r0,r1 r0,r1 ; Subtract r1 from r0 ; Skip if bit 7 in r0 cleared ; Only executed if bit 7 in r0 not cleared ; Continue (do nothing) sbrc r0,7
Words: 1 (2 bytes) Cycles: 1 if condition is false (no skip) 2 if condition is true (skip is executed) and the instruction skipped is 1 word 3 if condition is true (skip is executed) and the instruction skipped is 2 words
128
(i)
(i)
SBRS Rr,b
0 r 31, 0 b 7
PC PC + 1, Condition false - no skip PC PC + 2, Skip a one word instruction PC PC + 3, Skip a two word instruction
16-bit Opcode:
1111 111r rrrr 0bbb
Example:
sub sbrs neg nop r0,r1 r0,7 r0 ; Subtract r1 from r0 ; Skip if bit 7 in r0 set ; Only executed if bit 7 in r0 not set ; Continue (do nothing)
Words: 1 (2 bytes) Cycles: 1 if condition is false (no skip) 2 if condition is true (skip is executed) and the instruction skipped is 1 word 3 if condition is true (skip is executed) and the instruction skipped is 2 words
129
0856IAVR07/10
(i)
C1
Syntax: Operands: Program Counter:
(i)
SEC
16-bit Opcode:
1001 0100
None
PC PC + 1
0000
1000
C:
Example:
sec adc r0,r1 ; Set Carry Flag ; r0=r0+r1+1
130
(i)
H1
Syntax: Operands: Program Counter:
(i)
SEH
16-bit Opcode:
1001 0100
None
PC PC + 1
0101
1000
H:
Example:
seh ; Set Half Carry Flag
131
0856IAVR07/10
(i)
I1
Syntax: Operands: Program Counter:
(i)
SEI
16-bit Opcode:
1001 0100
None
PC PC + 1
0111
1000
I:
Example:
sei sleep ; set global interrupt enable ; enter sleep, waiting for interrupt ; note: will enter sleep before any pending interrupt(s)
132
(i)
N1
Syntax: Operands: Program Counter:
(i)
SEN
16-bit Opcode:
1001 0100
None
PC PC + 1
0010
1000
N:
Example:
add sen r2,r19 ; Add r19 to r2 ; Set Negative Flag
133
0856IAVR07/10
(i)
Rd $FF
Syntax: Operands: Program Counter:
(i)
SER Rd
16-bit Opcode:
1110 1111
16 d 31
PC PC + 1
dddd
1111
Example:
clr ser out nop out $18,r17 r16 r17 $18,r16 ; Clear r16 ; Set r17 ; Write zeros to Port B ; Delay (do nothing) ; Write ones to Port B
134
(i)
S1
Syntax: Operands: Program Counter:
(i)
SES
16-bit Opcode:
1001 0100
None
PC PC + 1
0100
1000
S:
Example:
add ses r2,r19 ; Add r19 to r2 ; Set Negative Flag
135
0856IAVR07/10
(i)
T1
Syntax: Operands: Program Counter:
(i)
SET
16-bit Opcode:
1001 0100
None
PC PC + 1
0110
1000
T:
1 T Flag set
Example:
set ; Set T Flag
136
(i)
V1
Syntax: Operands: Program Counter:
(i)
SEV
16-bit Opcode:
1001 0100
None
PC PC + 1
0011
1000
V:
Example:
add sev r2,r19 ; Add r19 to r2 ; Set Overflow Flag
137
0856IAVR07/10
(i)
Z1
Syntax: Operands: Program Counter:
(i)
SEZ
16-bit Opcode:
1001 0100
None
PC PC + 1
0001
1000
Z:
Example:
add sez r2,r19 ; Add r19 to r2 ; Set Zero Flag
138
SLEEP
16-bit Opcode:
1001 0101
None
PC PC + 1
1000
1000
Example:
mov ldi out sleep r0,r11 r16,(1<<SE) MCUCR, r16 ; Put MCU in sleep mode ; Copy r11 to r0 ; Enable sleep mode
139
0856IAVR07/10
(RAMPZ:Z) $ffff (RAMPZ:Z) R1:R0 (RAMPZ:Z) R1:R0 (RAMPZ:Z) TEMP BLBITS R1:R0
Syntax: Operands:
Erase Program memory page Write Program memory word Write temporary page buffer Write temporary page buffer to Program memory Set Boot Loader Lock bits
Program Counter:
(i)-(v)
SPM
16-bit Opcode:
Z+
PC PC + 1
1001
0101
1110
1000
Example:
;This example shows SPM write of one page for devices with page write ;- the routine writes one page of data from RAM to Flash ; ; the first data location in RAM is pointed to by the Y-pointer the first data location in Flash is pointed to by the Z-pointer
;- error handling is not included ;- the routine must be placed inside the boot space ; ; ; ; (at least the do_spm sub routine) (temp1, temp2, looplo, loophi, spmcrval must be defined by the user) storing and restoring of registers is not included in the routine register usage can be optimized at the expense of code size ;- registers used: r0, r1, temp1, temp2, looplo, loophi, spmcrval
.equPAGESIZEB = PAGESIZE*2;PAGESIZEB is page size in BYTES, not words .org SMALLBOOTSTART write_page:
140
141
0856IAVR07/10
ret
142
(RAMPZ:Z) $ffff (RAMPZ:Z) R1:R0 (RAMPZ:Z) BUFFER (RAMPZ:Z) $fff (RAMPZ:Z) R1:R0 (RAMPZ:Z) BUFFER
Erase Program memory page Load Page Buffer Write Page Buffer to Program memory Erase Program memory page, Z post incremented Load Page Buffer, Z post incremented Write Page Buffer to Program memory, Z post incremented
Program Counter:
Syntax:
Operands:
None None
PC PC + 1 PC PC + 1
0101 0101
1110 1111
1000 1000
Example:
TBD
143
0856IAVR07/10
X X+1 (X) Rr
Operands:
ST X, Rr ST X+, Rr ST -X, Rr
16-bit Opcode :
(i) (ii) (iii) 1001 1001 1001
0 r 31 0 r 31 0 r 31
PC PC + 1 PC PC + 1 PC PC + 1
144
1 1 2 1 1 2
145
0856IAVR07/10
Y Y+1 (Y) Rr
Operands:
0 r 31 0 r 31 0 r 31 0 r 31, 0 q 63
PC PC + 1 PC PC + 1 PC PC + 1 PC PC + 1
146
Example:
clr ldi st st ldi st st std r29 r28,$60 Y+,r0 Y,r1 r28,$63 Y,r2 -Y,r3 Y+2,r4 ; Clear Y high byte ; Set Y low byte to $60 ; Store r0 in data space loc. $60(Y post inc) ; Store r1 in data space loc. $61 ; Set Y low byte to $63 ; Store r2 in data space loc. $63 ; Store r3 in data space loc. $62(Y pre dec) ; Store r4 in data space loc. $64
(i) (ii) (iii) (iv) Cycles Reduced Core tinyAVR:(i) (ii) (iii)
2 1 1 2 2 1 1 2
147
0856IAVR07/10
Z Z+1 (Z) Rr
Operands:
0 r 31 0 r 31 0 r 31 0 r 31, 0 q 63
PC PC + 1 PC PC + 1 PC PC + 1 PC PC + 1
148
Example:
clr ldi st st ldi st st std r31 r30,$60 Z+,r0 Z,r1 r30,$63 Z,r2 -Z,r3 Z+2,r4 ; Clear Z high byte ; Set Z low byte to $60 ; Store r0 in data space loc. $60(Z post inc) ; Store r1 in data space loc. $61 ; Set Z low byte to $63 ; Store r2 in data space loc. $63 ; Store r3 in data space loc. $62(Z pre dec) ; Store r4 in data space loc. $64
(i) (ii) (iii) (iv) Cycles Reduced Core tinyAVR:(i) (ii) (iii)
2 1 1 2 2 1 1 2
149
0856IAVR07/10
(i)
(k) Rr
Syntax: Operands: Program Counter:
(i)
STS k,Rr
32-bit Opcode:
1001 kkkk 001d kkkk
0 r 31, 0 k 65535
PC PC + 2
dddd kkkk
0000 kkkk
Example:
lds add sts r2,$FF00 r2,r1 $FF00,r2 ; Load r2 with the contents of data space location $FF00 ; add r1 to r2 ; Write back
150
(i)
(k) Rr
Syntax: Operands: Program Counter:
(i)
STS k,Rr
16-bit Opcode:
1010 1kkk
16 r 31, 0 k 127
PC PC + 1
dddd
kkkk
Example:
lds add sts r16,$00 r16,r17 $00,r16 ; Load r16 with the contents of data space location $00 ; add r17 to r16 ; Write result to the same address it was fetched from
151
0856IAVR07/10
(i)
Rd Rd - Rr
Syntax: Operands: Program Counter:
(i)
SUB Rd,Rr
16-bit Opcode:
0001 10rd
0 d 31, 0 r 31
PC PC + 1
dddd
rrrr
H:
Rd3 Rr3 +Rr3 R3 +R3 Rd3 Set if there was a borrow from bit 3; cleared otherwise N V, For signed tests. Rd7 Rr7 R7 +Rd7 Rr7 R7 Set if twos complement overflow resulted from the operation; cleared otherwise. R7 Set if MSB of the result is set; cleared otherwise. R7 R6 R5 R4 R3 R2 R1 R0 Set if the result is $00; cleared otherwise. Rd7 Rr7 +Rr7 R7 +R7 Rd7 Set if the absolute value of the contents of Rr is larger than the absolute value of Rd; cleared otherwise.
S: V:
N:
Z:
C:
152
(i)
Rd Rd - K
Syntax: Operands: Program Counter:
(i)
SUBI Rd,K
16-bit Opcode:
0101 KKKK
16 d 31, 0 K 255
PC PC + 1
dddd
KKKK
H:
Rd3 K3+K3 R3 +R3 Rd3 Set if there was a borrow from bit 3; cleared otherwise N V, For signed tests. Rd7 K7 R7 +Rd7 K7 R7 Set if twos complement overflow resulted from the operation; cleared otherwise. R7 Set if MSB of the result is set; cleared otherwise. R7 R6 R5 R4 R3 R2 R1 R0 Set if the result is $00; cleared otherwise. Rd7 K7 +K7 R7 +R7 Rd7 Set if the absolute value of K is larger than the absolute value of Rd; cleared otherwise.
S: V:
N:
Z:
C:
153
0856IAVR07/10
(i)
(i)
SWAP Rd
16-bit Opcode:
1001 010d
0 d 31
PC PC + 1
dddd
0010
154
(i)
Rd Rd Rd
Syntax: Operands: Program Counter:
(i)
TST Rd
0 d 31
PC PC + 1
S: V:
N V, For signed tests. 0 Cleared R7 Set if MSB of the result is set; cleared otherwise. R7 R6 R5 R4 R3 R2 R1 R0 Set if the result is $00; cleared otherwise.
N:
Z:
155
0856IAVR07/10
(i)
WD timer restart.
Syntax: Operands: Program Counter:
(i)
WDR
16-bit Opcode:
1001 0101
None
PC PC + 1
1010
1000
Example:
wdr ; Reset watchdog timer
156
Operation:
(i)
(i)
XCH Z,Rd
16-bit Opcode:
1001 001r
0 d 31
PC PC + 1
rrrr
0100
157
0856IAVR07/10
Rev.0856I 07/10
1. Updated Complete Instruction Set Summary on page 11 with new instructions: LAC, LAS, LAT and XCH. LAC Load And Clear on page 84 LAS Load And Set on page 85 LAT Load And Toggle on page 86 XCH Exchange on page 157 2. Updated number of clock cycles column to include Reduced Core tinyAVR. (ATtiny replaced by Reduced Core tinyAVR).
Rev.0856H 04/09
1. Updated Complete Instruction Set Summary on page 11: Updated number of clock cycles column to include Reduced Core tinyAVR. 2. Updated sections for Reduced Core tinyAVR compatibility: CBI Clear Bit in I/O Register on page 48 LD Load Indirect from Data Space to Register using Index X on page 87 LD (LDD) Load Indirect from Data Space to Register using Index Y on page 90 LD (LDD) Load Indirect From Data Space to Register using Index Z on page 92 RCALL Relative Call to Subroutine on page 114 SBI Set Bit in I/O Register on page 123 ST Store Indirect From Register to Data Space using Index X on page 144 ST (STD) Store Indirect From Register to Data Space using Index Y on page 146 ST (STD) Store Indirect From Register to Data Space using Index Z on page 148 3. Added sections for Reduced Core tinyAVR compatibility: LDS (16-bit) Load Direct from Data Space on page 96 STS (16-bit) Store Direct to Data Space on page 151
Rev.0856G 07/08
1. Inserted Datasheet Revision History 2. Updated Cycles XMEGA for ST, by removing (iv). 3. Updated SPM #2 opcodes.
158
159
0856IAVR07/10
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0856IAVR07/10