RISC1

Roadmap
Success is not an accident!
Part 1: Modeling, Verification and Synthesis of Combinational Logic Logic

Design Flow for HDLHDL-Based Design Methodology Modeling, Verification, and Synthesis of Combinational Logic Structural decomposition and toptop-down design Verilog language constructs Test plan, test bench, simulation, and verification
ECE 4242 / 5242 Fall 2007
Advanced Digital Design Methodology

Synthesis of Datapath Controllers
Professor Michael D. Ciletti Department of Electrical and Computer Engineering University of Colorado at Colorado Springs ciletti@eas.uccs.edu
Part 2: Modeling, Verification, and Synthesis of Sequential Logic Logic

RTL data flow constructs and operators Control flow constructs Sequential ( = ) vs. concurrent ( <= ) assignments
Part 3: Synchronous Finite State Machines and Datapath Controllers

Mealy, Moore machines Behavioral modeling for latch-free synthesis Race-Free Synthesis of Datapath Controllers
ECE 4242 / 5242 Advanced Digital Design Methodology: Synthesis of Datapath Controllers Copyright 2007 Michael D. Ciletti 2
EKE 4242 / 5242 Advanced Digital Design Methodology: Synthesis of Datapath Controllers
Copyright 2007 Michael D. Ciletti 1
Verilog Models of Combinational and Sequential Logic

Descriptive Options Verilog Options Structural
Synchronous Finite State Machines
Schematic/Gates Truth Tables Boolean Equations RTL / Dataflow
Primitives UserUser-Defined Primitives (UDPs) Continuous Assignments Cyclic Behaviors
State/Next State Tables State Transition Graphs ASM Charts

R1 R1 + R2 R3 R3 + 1 R4 shr R4 R5 0 Add content of R2 to R1 Increment R3 by 1 (count up) Shift right R4 Clear R5 to 0
Behavioral
ASMD Charts Algorithm
Use cyclic behaviors to model sequential logic.

Copyright 2007 Michael D. Ciletti 3 ECE 4242 / 5242 Advanced Digital Design Methodology: Synthesis of Datapath Controllers Copyright 2007 Michael D. Ciletti 4
ECE 4242 / 5242 Advanced Digital Design Methodology: Synthesis of Datapath Controllers
Relevant Questions
How should a datapath and its controller be modeled to avoid race
conditions? How can simulation mismatches be prevented?
Datapath Controller (p. 347)

ASMD charts describe complex machines (e.g., datapath controller)
Control signals (FSM outputs) Primary inputs (external) Control Unit
Data inputs
Datapath Unit
Status signals (FSM inputs) Data outputs
FSM Controller for a Datapath
ASMD Chart (p. 194)

An algorithmic state machine and datapath (ASMD) chart describes a finite state machine for controlling the register operations of a datapath. datapath.
Datapaths
Datapath Unit Control Unit External Control Inputs Finite-State Machine Clock Datapath Registers Status signals Clock Datapath Logic Control signals
Process:
Annotate the ASM chart to indicate the concurrent register operations operations that occur in
the associated datapath unit when (1) the controller is in a state (Moore output signal), or (2) when the state makes a transition along a path (Mealy output signal)
Edit the chart (add output signals) to identify the signals that launch the indicated
datapath operations Benefits:
Clarifies a design of a sequential machine by separating the design design of its datapath
from the design of its controller
Maintains a clear/ documented relationship between a datapath and its controller

Note: Put status signals and primary inputs in decision boxes
Datapath Controller Design

Specify register operations for the datapath Define the ASM chart of the controller (PI and feedback from
datapath) datapath) Annotate the arcs of the ASM chart with the datapath operations associated with the state transitions of the controller Annotate the state of the controller with unconditional (Moore) output signals Include conditional boxes for the Mealy output signals generated by the controller to control the datapath. datapath. Verify the controller Verify the datapath Verify the integrated units Verify postpost-synthesis
Datapath Control Signals

The architecture (registers, ALUs, busses) and opcodes of the datapath determine the signals that must be generated to control the datapath.
Load, clear, shift contents of registers Fetch instructions from memory Store data in memory Steer signals through muxes Control threethree-state devices Select/execute ALU operations
Application-Driven Design
Application
Example: Binary Counter
Architecture (Implementation)
Instruction Set (Specification)
Control Sequence
Control Unit FSM
Binary Counter: Simplified STG

rst
enable enable enable
Partitioned Machine ASMD CHART
count <= next_count

0011
enable
0000
0001
0010
rst
S_running 0
rst
S_running
0111
enable
0110
enable
0101
enable
0100
enable
enable
enable 1 enable_DP
1
1000
enable
1001
enable
1010
enable
1011
enable
count <= next_count
1111
enable
1110
enable
1101
enable
1100
Confusion: Mixed Datapath Operations and FSM
Clarity: Partitioned Datapath and Controller

ASMD-Based Verilog Model (1 of 2)

module Binary_Counter_Part_RTL # (parameter size = 4) ( output [size -1: 0] count, input enable, clk, rst ); wire enable_DP; Control_Unit M0 (enable_DP, enable, clk, rst); Datapath_Unit M1 (count, enable_DP, clk, rst); endmodule module Control_Unit (output enable_DP, input enable, clk, rst); wire enable_DP = enable; // pass through endmodule
ASMD-Based Verilog Model (2 of 2)

module Datapath_Unit # (parameter size = 4, incr = 1) ( output reg [size[size-1: 0] count, input enable, clk, rst); wire [size[size-1: 0] next_count; always @ (posedge clk) if (rst == 1) count <= 0; else if (enable == 1) count <= next_count(count); function [size[size-1: 0] next_count (input [size[size-1: 0] count); begin next_count = count + incr; end endfunction endmodule Adjust for increment
Binary Counter: Simulation Results
Binary CountCount-byby-3 Clocks (Implicit State Machine)

module Control_Unit_by_3 ( output reg enable_DP, input enable, clk, rst );
Named block
always begin: Cycle_by_3 @ (posedge clk) enable_DP <= 0; if ((rst == 1) || (enable != 1)) disable Cycle_by_3; else @ (posedge clk) if ((rst == 1) || (enable != 1)) disable Cycle_by_3; else @ (posedge clk) if ((rst == 1) || (enable != 1)) disable Cycle_by_3; else enable_DP <= 1; end // Cycle_by_3 Caution: Model has pipeline endmodule effect one extra cycle to recover from reset.
Simulation Results: CountCount-byby-3 Clocks
Synthesis Result: Count-by-3 Clocks
enable enable_DP dfnf311 rst clk dfnf311 dfnf311
osu05_stdcells Implementation
ASMD Chart (Two Stage Pipeline)

Data
8
P1[7: 0]
P0[7: 0]
8
S_idle
{P1, P0} <= {0, 0}
P1[7: 0]
P0[7: 0]
R0[15: 0]
rst
P1 <= Data P0 <= P1 P1 <= Data P0 <= P1
En
1 S_1
{P1, P0} <= {0, 0}
S_full
enable enable_DP dfnf311 rst clk dfnf311 dfnf311
P1 <= Data P0 <= P1
S_wait
Ld
1 1
Ld
En
R0 <= {P1, P0}
Complete ASMD Chart

S_idle clr_P1_P0 clr_P1_P0
ASMDASMD-Based Datapath Controller Design Methodology Clarify the design of a sequential machine by separating the design design
of its datapath from the design of the controller
rst
Mealy outputs? Moore outputs?
P1 <= Data P0 <= P1
{P1, P0} <= {0, 0}
Specify register operations for the datapath Define the ASM chart of the controller (primary inputs and feedback feedback
from datapath)
En
P1 <= Data P0 <= P1 1 load_P1_P0 S_1 /load_P1_P0 S_full
Annotate the arcs of the ASM chart with the datapath operations
associated with the state transitions of the controller
Annotate the state of the controller with unconditional (Moore)

output signals
P1 <= Data P0 <= P1
Include conditional boxes (Mealy) for the signals generated by the the
controller to control the datapath.
S_wait
Ld
1
load_P1_P0 1 load_R0
Verify the controller Verify the datapath Verify the integrated units
Ld
En
R0 <= {P1, P0}

ECE 4242 / 5242 Advanced Digital Design Methodology: Synthesis of Datapath Controllers Copyright 2007 Michael D. Ciletti 23 ECE 4242 / 5242 Advanced Digital Design Methodology: Synthesis of Datapath Controllers Copyright 2007 Michael D. Ciletti 24
ASMD Model: D-Type Flip-flop (For Illustration!)
D Flip-flop: Partitioned Model

module d_flop_Partition (output q, q_bar, input data, set, rst, clock); Controller M0 (reset_q, set_q, clock, rst, set); Datapath M_1(q, q_bar, data, reset_q, set_q ); endmodule module Controller (output reset_q, set_q, input clock, reset, set); assign reset_q = reset, set_q = set; Wires! endmodule
Synchronous reset/set with reset priority

module d_flop (output reg q, output q_bar, input data, set, rst, clock); always @ (posedge clock) Register if (reset) q <= 1'b0; else if (set) q <= 1'b1; else q <= data; assign q_bar = q; endmodule
module Datapath ( output reg q, output q_bar, input data, R, S); always @ (posedge clock) if (R) q <= 1'b0; else if (S) q <= 1'b1; else q <= data; assign q_bar = q; endmodule
Operations
Datapath logic
The description of a controller that has only combinational logic (i.e., no states) can be embedded in the datapath logic.
Post-Synthesis Simulation Mismatch

In a given time step, multiple assignments to the same register variable are made in an indeterminate order.
Control Unit External Control Inputs Finite-State Machine Clock Datapath Logic Control signals
Rules for Race-Free Datapath Controller Design

(1) Model I/O combinational logic with continuous assignments or levelsensitive cyclic behavior using the blocking assignment operator ( = ). (2) Model register operations with edge-sensitive cyclic behavior using the (concurrent) non-blocking assignment operator ( <= ).
Datapaths Datapath Unit Control Unit Datapath Registers External Control Inputs Finite-State Machine Clock Datapath Logic Control signals
Datapaths Datapath Unit
Race?
Status signals Clock
Race?
Status signals Clock
Datapath Registers
state
Control
Status
state ?
Unexpected Pipelines and Data Slip

Be careful when using nonblocking assignments that have dependencies between their statements.
Example:
always @ (posedge clock) if (reset ==1) begin q <= 0; q_bar <= 0; end else begin q <= data; q_bar <= ~q; end
Smart Counter of 1s: ASMD Chart

Status signal
data temp_gt_1
load_temp clear shift_add start busy Controller
Datapath temp
bit_count
Data slip: q_bar is pipelined from q and will lag by one cycle.
q data
D Q D Q
done reset clock bit_count
q_bar
clock reset
Alternative: wire q_bar = ~q;

Smart Counter of 1s (1 of 5)
module count_ones_SM # (parameter counter_size = 3, word_size = 4) ( output [counter_size -1: 0] bit_count, output busy, done, input [word_size[word_size-1: 0] data, input start, clk, reset ); wire load_temp, shift_add, clear, temp_0, temp_gt_1; controller M0 (load_temp, shift_add, clear, busy, done, start, temp_gt_1, clk, reset); datapath M1 (temp_gt_1, temp_0, data, load_temp, shift_add, clk, clk, reset); bit_counter_unit M2 (bit_count, temp_0, clear, clk, reset); endmodule Note: Bit Counter is separate - for convenience.
module controller # (parameter state_size = 2; S_idle = 0, S_counting = 1, S_waiting = 2) ( output reg load_temp, shift_add, clear, busy, done, input start, temp_gt_1, clk, reset); reg bit_count; reg [state_sizestate, next_state; [state_size-1 : 0] always @ (posedge clk) // state transitions if (reset) state <= S_idle; else state <= next_state; always @ (state, start, temp_gt_1) begin load_temp = 0; shift_add = 0; done = 0; busy = 0; clear = 0; next_state = S_idle; // Comb Logic
case (state) S_idle: S_counting: if (start) begin next_state = S_counting; load_temp = 1; end begin busy = 1; if (temp_gt_1) begin next_state = S_counting; shift_add = 1; end else begin next_state = S_waiting; shift_add = 1; end end begin done = 1; if (start) begin next_state = S_counting; load_temp = 1; clear = 1; end else next_state = S_waiting; end begin clear = 1; next_state = S_idle; end
module datapath # (parameter word_size = 4) (output temp_gt_1, temp_0, input, load_temp, shift_add, clk, reset, input [word_size[word_size-1: 0] data ); reg [word_sizetemp; [word_size-1: 0] wire temp_gt_1 = (temp > 1); wire temp_0 = temp[0]; always @ (posedge clk) // state and register transfers if (reset) begin temp <= 0; end else begin if (load_temp) temp <= data; if (shift_add) begin temp <= temp >> 1; end end endmodule
S_waiting:
default: endcase end endmodule
module bit_counter_unit (bit_count, temp_0, clear, clk, reset); parameter counter_size = 3; output [counter_size -1 : 0] bit_count; input temp_0; input clear, clk, reset; reg bit_count; always @ (posedge clk) // state and register transfers if (reset || clear) bit_count <= 0; else bit_count <= bit_count + temp_0; endmodule
Smart Counter of 1s: Simulation Results
Smart Counter of 1s: Synthesis Results (1 of 3)
Datapath: Datapath
Controller:
Reduced Register Multiplier - Architectural Tradeoffs
Bit Counter
Sequential multiplier: Add and shift algorithm Separate registers Long adder Shift multiplicand and multiplier ReducedReduced-register alternative machine Form product in multiplier reg Hardwired multiplicand Load multiplier in right side Form row sums in left side Eliminate register Shorter adder Fewer shift registers Adapted from Ciletti, M D. Advanced Digital Design with the Verilog
HDL. Upper Saddle River, NJ: PrenticePrentice-Hall, 2003
clk
xnor2_a xor2_a
temp_0 reset clear

esdpupd or2_a
nor2_a
dffspqb_a
nand2_a
xor2_a
nor2_a
dffspqb_a
and2i_a
nor2_a
dffspqb_a
bit_count<2:0>
bit_count<2>
bit_count<1> bit_count<0>
Reduced Register Multiplier - Data Flow
Reduced Register Multiplier - ASMD Chart
ASMD chart for the datapath controller:

Datapath operations
Reduced Register Multiplier - Model (1 of 3)

module Multiplier_RR_ASM (product, Ready, word1, word2, Start, clock, reset); parameter L_word = 4; parameter L_cnt = 3; output [2*L_word: 0] product; output Ready; input [L_word -1: 0] word1, word2; input Start, clock, reset; reg state, next_state; reg [L_word -1: 0] multiplicand; reg product, Load_words; reg Flush, Shift, Add_shift, Increment; reg [L_cnt -1 : 0] counter; parameter S_idle = 0, S_running = 1; wire Empty = (word1 == 0) || (word2 == 0); wire Ready = (state == S_idle) && (!reset );

always @ (posedge clock, posedge reset) // State transitions if (reset) state <= S_idle; else state <= next_state; // Combinational logic for ASM-based controller always @ (state, Start, Empty, product, counter) begin Flush = 0; Load_words = 0; Shift = 0; Add_shift = 0; Increment = 0; case (state) S_idle: if (!Start) next_state = S_idle; else if (Empty) begin next_state = S_idle; Flush = 1; end else begin Load_words = 1; next_state = S_running; end if (counter == L_word) next_state = S_idle; else begin Increment = 1; if (product[0]) begin Add_shift = 1; next_state = S_running; end else begin Shift = 1; next_state = S_running; end end
S_running:

default: next_state = S_idle; endcase end // Register/Datapath Operations always @ (posedge clock, posedge reset) if (reset) begin multiplicand <= 0; product <= 0; counter <= 0; end else begin if (Flush) product <= 0; if (Load_words == 1) begin multiplicand <= word1; product <= word2; counter <= 0; end if (Shift) begin product <= product >> 1; end if (Add_shift) begin product <= {product[2*L_word: L_word] + multiplicand, product[L_word -1: 0]} >> 1; end if (Increment) counter <= counter +1; end endmodule
Reduced Register Multiplier: Simulation Results
Example: Bubble Sort Algorithm

Sort a set of unsigned binary numbers and arrange them
Bubble Sort Algorithm: ASMD Chart
in ascending order Pseudocode:
Data flow graph
j=1 i=2 7
j=2 6
j=3 5
j=4 4
for i=2 to N_key begin for j = N_key downto i do if a[j-1] > a[j] then begin temp= a[j-1]; a[j-1]=a[j]; a[j]=temp end end
Adapted from Ciletti, M D. Advanced Digital Design with the Verilog HDL. Upper Saddle River, NJ: Prentice-Hall, 2003
Architecture
i =3 4
incr_i
decr_i
decr_j
incr_j
swap
i =4 4
Bubble Sort Algorithm: Simulation Results

Load the registers
Bubble Sort Algorithm: Model Declarations
Datapath operations
Sorted data
module Bubble_Sort (A1, A2, A3, A4, A5, A6, A7, A8,En, Ld, clk, rst); output [3:0] A1, A2, A3, A4, A5, A6, A7, A8; input En, Ld, clk, rst; parameter N = 8; parameter word_size = 4; parameter a1 = 8, a2 = 1, a3 = 8, a4 = 1, a5 = 8, a6 = 1, a7 = 8, a8 = 1; reg [word_size -1: 0] A [1: N]; // Array of words wire [3:0] A1 = A[1], A2 = A[2], A3 = A[3], A4 = A[4]; wire [3:0] A5 = A[5], A6 = A[6], A7 = A[7], A8 = A[8]; parameter S_idle = 0, S_run = 1; reg [3: 0] i, j; reg swap, decr_j, incr_i, set_i, set_j; reg state, next_state; wire gt = (A[j-1] > A[j]); // compares words
Bubble Sort Algorithm: State Machine Controller
Bubble Sort Algorithm: Datapath Operations

always @ (posedge clk) // Datapath and status registers if (rst) begin i <= 0; j <= 0; A[1] <= 0; A[2] <= 0; A[3] <= 0; A[4] <= 0; A[5] <= 0; A[6] <= 0; A[7] <= 0; A[8] <= 0; end else if (Ld) begin i <= 2; j <= N; A[1] <= a1; A[2] <= a2; A[3] <= a3; A[4] <= a4; A[5] <= a5; A[6] <= a6; A[7] <= a7; A[8] <= a8; end else begin /*#1 // Unit delay for display only; remove for synthesis */ if (swap) begin A[j] <= A[j-1]; A[j-1] <= A[j]; end if (decr_j) j <= j-1; if (incr_i) i <= i+1; if (set_j) j <= N; if (set_i) i <= 2; end endmodule
always @ (posedge clk) if (rst) state <= S_idle; else state <= next_state; always @ (state or En or Ld or gt or i or j) begin swap = 0; decr_j = 0; incr_i = 0; set_j = 0; set_i = 0; case (state) S_idle: if (Ld) begin next_state = S_idle; end else if (En) begin next_state = S_run; if (gt) begin swap = 1; decr_j = 1; end else next_state = S_idle; end S_run: if (j >= i) begin next_state = S_run; decr_j = 1; if (gt) swap = 1; end else if (i <= N) begin next_state = S_run; set_j = 1; incr_i = 1; end else begin next_state = S_idle; set_j = 1; set_i = 1; end
endcase end
Bubble Sort Algorithm: Testbench

module t_Bubble_Sort (); wire [3:0] A1, A2, A3, A4, A5, A6, A7, A8; reg En, Ld, clk, rst; Bubble_Sort M0 (A1, A2, A3, A4, A5, A6, A7, A8,En, Ld, clk, rst); initial #1000 $finish; initial begin clk = 0; forever #5 clk = ~clk; end initial fork rst = 1; #20 rst = 0; #30 Ld = 1; #40 Ld = 0; #60 En = 1; #70 En = 0; #450 rst = 1; #470 rst = 0; #500 Ld = 1; #510 Ld = 0; join initial fork #10 En = 1; #20 En = 0; #500 En = 1; join endmodule
ASMD-Based Design: RISC Machine

Stored program ISA Fetch, decode, execute instructions ALU operations Load registers Change contents of program counter, instruction register, address register Simplicity: no I/O
Adapted from: M. D. Ciletti, Advanced Digital Design with the Verilog HDL, Upper Saddle River, Prentice-Hall, Inc., NJ. 2003
RISC: ALU Instruction Set

Specificatiion (Instruction Set)
Bus_1 Bus_1
RISC: Opcodes
Reg_Y Reg_Y
Instr
Instruction Word opcode src ?? src src src src ?? src ?? ?? ?? dest ?? dest dest dest dest dest ?? ?? ?? ??
Action none dest <= src + dest dest <= dest - src dest <= src && dest dest <= ~src dest <= memory[Add_R] memory[Add_R] <= src PC <= memory[Add_R] PC <= memory[Add_R] Halts execution until reset
Implementaton (Architecture) Realization (ASIC)

Instruction Action
opcode opcode
ALU ALU
NOP ADD SUB AND NOT RD* WR* BR* BRZ* HALT
0000 0001 0010 0011 0100 0101 0110 0111 1000 1111
alu_zero_flag alu_zero_flag
ADD SUB AND NOT
Adds the datapaths to form data_1 + data_2 Subtracts the datapaths to form data_1 - data_2 Takes the bitwise-and of the datapaths, data_1 & data_2 Takes the bitwise Boolean complement of data_1
* Requires a second word of data; ? denotes a don't care.
RISC: Instruction Format
RISC: Control Signals (1 of 2)

Load_Add_Reg Load _PC Load_IR Inc_PC Sel_Bus_1_Mux
opcode source 0 1 0 destination
don't care don't care
Short instruction (SUB) (Single byte): Long instruction (WR) (Two bytes):
opcode 0 0 1 0
source 0 1
destination 1 0
Loads the address register Loads Bus_2 to the program counter Loads Bus_2 to the instruction register Increments the program counter Selects among the Program_Counter, R0, R1, R2, and R3 to drive Bus_1 Selects among Alu_out, Bus_1, and memory to drive Bus_2
Sel_Bus_2_Mux
address 0 0 0 1 1 1 0 1
The control unit (1) determines when to load registers, (2) selects the path of data through the multiplexers, (3) determines when data should be written to memory, and (4) controls the three-state busses in the architecture.
RISC: Control Signals (2 of 2)
RISC: Verilog Model

module RISC_SPM # ( parameter parameter parameter )(input wire wire [Sel1_size-1: 0] [Sel2_size-1: 0] word_size = 8, Sel1_size = 3, Sel2_size = 2, clk, rst); Sel_Bus_1_Mux; Sel_Bus_2_Mux;
Load_R0 Load_R1 Load_R2 Load_R3 Load_Reg_Y Load Reg_Z write
Loads general purpose register R0 Loads general purpose register R1 Loads general purpose register R2 Loads general purpose register R3 Loads Bus_2 to the register Reg_Y Stores output of ALU in register Reg_Z Loads Bus_1 into the SRAM memory at the location specified by the address register
// Data Nets wire wire [word_size-1: 0]
zero; instruction, address, Bus_1, mem_word;
// Control Nets wire Load_R0, Load_R1, Load_R2, Load_R3; wire Load_PC, Inc_PC, Load_IR; wire Load_Add_R, Load_Reg_Y, Load_Reg_Z; wire write;
RISC: Instantiated Modules
RISC: Processor Unit (1 of 3)
Processing_Unit M0_Processor (instruction, zero, address, Bus_1, mem_word, Load_R0, Load_R1, Load_R2, Load_R3, Load_PC, Inc_PC, Sel_Bus_1_Mux, Load_IR, Load_Add_R, Load_Reg_Y, Load_Reg_Z, Sel_Bus_2_Mux, clk, rst); Control_Unit M1_Controller (Load_R0, Load_R1, Load_R2, Load_R3, Load_PC, Inc_PC, Sel_Bus_1_Mux, Sel_Bus_2_Mux , Load_IR, Load_Add_R, Load_Reg_Y, Load_Reg_Z, write, instruction, zero, clk, rst); Memory_Unit M2_MEM ( .data_out (mem_word), .data_in (Bus_1), .address (address), .clk (clk), .write (write)); endmodule // RISC_SPM

module Processing_Unit # ( parameter word_size = 8, parameter op_size = 4, parameter Sel1_size = 3, parameter Sel2_size = 2 )( output [word_size-1: 0] instruction, address, Bus_1, output Zflag, input [word_size-1: 0] mem_word, input Load_R0, Load_R1, Load_R2, Load_R3, Load_PC, Inc_PC, input [Sel1_size-1: 0] Sel_Bus_1_Mux, input [Sel2_size-1: 0] Sel_Bus_2_Mux, input Load_IR, Load_Add_R, Load_Reg_Y, Load_Reg_Z, input clk, rst );
wire wire [word_size-1: 0] wire [word_size-1: 0] wire [word_size-1: 0] wire wire [op_size-1 : 0]
Load_R0, Load_R1, Load_R2, Load_R3; Bus_2; R0_out, R1_out, R2_out, R3_out; PC_count, Y_value, alu_out; alu_zero_flag; opcode = instruction [word_size-1: word_size-op_size];
RISC: Processor Unit: Instantiated Modules

(R0_out, Bus_2, Load_R0, clk, rst); (R1_out, Bus_2, Load_R1, clk, rst); (R2_out, Bus_2, Load_R2, clk, rst); (R3_out, Bus_2, Load_R3, clk, rst); (Y_value, Bus_2, Load_Reg_Y, clk, rst); (Zflag, alu_zero_flag, Load_Reg_Z, clk, rst); (address, Bus_2, Load_Add_R, clk, rst); (instruction, Bus_2, Load_IR, clk, rst); (PC_count, Bus_2, Load_PC, Inc_PC, clk, rst); Multiplexer_5ch Mux_1 (Bus_1, R0_out, R1_out, R2_out, R3_out, PC_count, Sel_Bus_1_Mux); Multiplexer_3ch Mux_2 (Bus_2, alu_out, Bus_1, mem_word, Sel_Bus_2_Mux); Alu_RISC ALU (alu_zero_flag, alu_out, Y_value, Bus_1, opcode); endmodule // Processing_Unit Register_Unit Register_Unit Register_Unit Register_Unit Register_Unit D_flop Address_Register Instruction_Register Program_Counter R0 R1 R2 R3 Reg_Y Reg_Z Add_R IR PC
Register Unit
module Register_Unit # (parameter word_size = 8)( output reg [word_sizedata_out, [word_size-1: 0] input [word_sizedata_in, [word_size-1: 0] input load, input clk, rst, ); always @ (posedge clk, negedge rst) if (rst == 0) data_out <= 0; else if (load) data_out <= data_in; endmodule
Flip-Flop Model
module D_flop ( output reg data_out, input data_in, input load, input clk, rst, ); always @ (posedge clk, negedge rst) if (rst == 0) data_out <= 0; else if (load == 1)data_out <= data_in; endmodule
RISC: Address Register

module D_flop ( output reg input input input ); data_out, data_in, load, clk, rst
always @ (posedge clk, negedge rst) if (rst == 0) data_out <= 0; else if (load == 1) data_out <= data_in; endmodule module Address_Register # (parameter word_size = 8)( output reg [word_size-1: 0] data_out, input [word_size-1: 0] data_in, input load, clk, rst ); always @ (posedge clk, negedge rst) if (rst == 0) data_out <= 0; else if (load) data_out <= data_in; endmodule
RISC: Instruction Register, Program Counter

module Instruction_Register (parameter word_size = 8)( output reg [word_size-1: 0] data_out, input [word_size-1: 0] data_in, input load, clk, rst ); always @ (posedge clk, negedge rst) if (rst == 0) data_out <= 0; else if (load) data_out <= data_in; endmodule module Program_Counter # (parameter word_size = 8)( output reg [word_size-1: 0] count; input [word_size-1: 0] data_in; input Load_PC, Inc_PC, clk, rst; ); always @ (posedge clk, negedge rst) if (rst == 0) count <= 0; else if (Load_PC) count <= data_in; else if (Inc_PC) count <= count +1; endmodule
RISC: Five-Channel Multiplexer

module Multiplexer_5ch # (parameter word_size = 8) ( output [word_size-1: 0] mux_out, input [word_size-1: 0] data_a, data_b, data_c, data_d, data_e, input [2: 0] sel ); always @ (sel, data_a, data_b, data_c, data_d, data_e) case (sel) 0: mux_out = data_a; 1: mux_out = data_b; 2: mux_out = data_c; 3: mux_out = data_d; 4: mux_out = data_e; default: mux_out = 'bx; endmodule
RISC: Three-Channel Multiplexer

module Multiplexer_3ch (mux_out, data_a, data_b, data_c, sel); parameter word_size = 8; output [word_size-1: 0] mux_out; input [word_size-1: 0] data_a, data_b, data_c; input [1: 0] sel; assign mux_out = (sel == 0) ? data_a: (sel == 1) ? data_b : (sel == 2) ? data_c: 'bx; endmodule
RISC: ALU (1 of 2)
module Alu_RISC (alu_zero_flag, alu_out, data_1, data_2, sel); parameter word_size = 8; parameter op_size = 4; // Opcodes parameter NOP parameter ADD parameter SUB parameter AND parameter NOT parameter RD parameter WR parameter BR parameter BRZ
= 4'b0000; = 4'b0001; = 4'b0010; = 4'b0011; = 4'b0100; = 4'b0101; = 4'b0110; = 4'b0111; = 4'b1000;
RISC: ALU (2 of 2)
output output input input reg [word_size-1: 0] [word_size-1: 0] [op_size-1: 0] alu_zero_flag; alu_out; data_1, data_2; sel; alu_out;
RISC: Control Unit

RISC_SPM
Controller Processor R0 R1 R2 R3 PC IR
assign alu_zero_flag = ~|alu_out; always @ (sel or data_1 or data_2) case (sel) NOP: alu_out = 0; ADD: alu_out = data_1 + data_2; // Reg_Y + Bus_1 SUB: alu_out = data_2 - data_1; AND: alu_out = data_1 & data_2; NOT: alu_out = ~ data_2; // Gets data from Bus_1 default: alu_out = 0; endcase endmodule
Develop Verilog model directly from the ASM or ASMD chart State machine (Mealy/Moore) Output signals control the datapath operations of the processor Uses feedback from the processor
Load_R0 Load_R1 Load_R2 Load_R3 Load_PC Inc_PC instruction Sel_Bus_1_Mux Load_IR Load_Add_Reg Load_Reg_Y
01 2 34 Mux_1 Bus_1
Reg_Y
opcode
ALU
alu_zero_flag
Memory
mem_word
Load_Reg_Z zero Sel_Bus_2_Mux
Reg_Z
Zflag
1 2 Mux_2
Add_R
Bus_2 write
RISC: ASM Chart Short Instructions
RISC_SPM: ASM Chart Long Instructions
Mealy outputs
Moore outputs
Note both Moore and Mealy outputs
...
Strategy: Develop the state machine directly from the ASM chart
...
Long instructions require two cycles to execute
...
RISC_SPM: Control Unit Verilog Model (1 of 7)

module Control_Unit ( The program is loaded into memory Load_R0, Load_R1, by the testbench and executes after Load_R2, Load_R3, reset is dede-asserted Load_PC, Inc_PC, Sel_Bus_1_Mux, Sel_Bus_2_Mux, Load_IR, Load_Add_R, Load_Reg_Y, Load_Reg_Z, write, instruction, zero, clk, rst); parameter word_size = 8, op_size = 4, state_size = 4; parameter src_size = 2, dest_size = 2, Sel1_size = 3, Sel2_size = 2; // State Codes parameter S_idle = 0, S_fet1 = 1, S_fet2 = 2, S_dec = 3; parameter S_ex1 = 4, S_rd1 = 5, S_rd2 = 6; parameter S_wr1 = 7, S_wr2 = 8, S_br1 = 9, S_br2 = 10, S_halt = 11; // Opcodes parameter NOP = 0, ADD = 1, SUB = 2, AND = 3, NOT = 4; parameter RD = 5, WR = 6, BR = 7, BRZ = 8; // Source and Destination Codes parameter R0 = 0, R1 = 1, R2 = 2, R3 = 3;

// Ports output Load_R0, Load_R1, Load_R2, Load_R3; output Load_PC, Inc_PC; output [Sel1_size-1: 0] Sel_Bus_1_Mux; output Load_IR, Load_Add_R; output Load_Reg_Y, Load_Reg_Z; output [Sel2_size-1: 0] Sel_Bus_2_Mux; output write; input [word_size-1: 0] instruction; input zero; input clk, rst; // Datapath and State Register Variables reg [state_size-1: 0] state, next_state; reg Load_R0, Load_R1, Load_R2, Load_R3, Load_PC, Inc_PC; reg Load_IR, Load_Add_R, Load_Reg_Y; reg Sel_ALU, Sel_Bus_1, Sel_Mem; reg Sel_R0, Sel_R1, Sel_R2, Sel_R3, Sel_PC; reg Load_Reg_Z, write; reg err_flag;

// Structural connections wire [op_size-1: 0] opcode = instruction [word_size-1: word_size - op_size]; wire [src_size-1: 0] src = instruction [src_size + dest_size -1: dest_size]; wire [dest_size-1: 0] dest = instruction [dest_size -1: 0]; // Datapath mux selectors assign Sel_Bus_1_Mux[Sel1_size-1: 0] = Sel_R0 ? 0: Sel_R1 ? 1: Sel_R2 ? 2: Sel_R3 ? 3: Sel_PC ? 4: 3'bx; // 3-bits, sized number assign Sel_Bus_2_Mux[Sel2_size-1: 0] = Sel_ALU ? 0: Sel_Bus_1 ? 1: Sel_Mem ? 2: 2'bx;

// State machine always @ (posedge clk, negedge rst) begin: State_transitions if (rst == 0) state <= S_idle; else state <= next_state; end
/* always @ (state, instruction, zero) begin: Output_and_next_state Note: The above event control expression leads to incorrect operation. operation. The state transition causes the activity to be evaluated once, then the resulting instruction change causes it to be evaluated again, but with the residual value of opcode. On the second pass the value seen is the value opcode had before the state change, which results in Sel_PC = 0 in state 3, which will cause a return to state 1 at the next clock. Finally, opcode is changed, but this does not trigger a rere-evaluation because it is not in the event control expression. So, the caution is to be sure to use opcode in the event control expression. That way, the final execution of the behavior uses the the value of opcode that results from the state change, and leads to the correct value value of Sel_PC. */
Correct Event Sensitivity List

always @ (state, opcode, src, dest, zero) begin: Output_and_next_state // Initialize to default values Sel_R0 = 0; Sel_R1 = 0; Sel_R2 = 0; Sel_R3 = 0; Sel_PC = 0; Load_R0 = 0; Load_R1 = 0; Load_R2 = 0; Load_R3 = 0; Load_PC = 0; Load_IR = 0; Load_Add_R = 0; Load_Reg_Y = 0; Load_Reg_Z = 0; Inc_PC = 0; Sel_Bus_1 = 0; Sel_ALU = 0; Sel_Mem = 0; write = 0; err_flag = 0; // Used for de-bug in simulation next_state = state;
case (state)
All outputs are initialized to 0 immediately, so values can be assigned by exception.

S_idle: next_state = S_fet1; S_fet1: begin next_state = S_fet2; Sel_PC = 1; Sel_Bus_1 = 1; ASM chart states Load_Add_R = 1; end S_fet2: begin next_state = S_dec; Sel_Mem = 1; Load_IR = 1; Inc_PC = 1; end
Decode the state and generate the next state and the outputs.
Assignment by exception reduces the complexity of the code and reduces the chances of making an error in the logic.

NOP, ADD, SUB, AND Instructions ASMD state
S_dec: case (opcode) // Decode NOP: next_state = S_fet1; ADD, SUB, AND: begin next_state = S_ex1; Sel_Bus_1 = 1; Load_Reg_Y = 1; case (src) // Select ALU src reg R0: Sel_R0 = 1; R1: Sel_R1 = 1; R2: Sel_R2 = 1; R3: Sel_R3 = 1; default : err_flag = 1; endcase end // ADD, SUB, AND

NOT: begin next_state = S_fet1; Load_Reg_Z = 1; Sel_Bus_1 = 1; Sel_ALU = 1; case (src) // Select the ALU source reg R0: Sel_R0 = 1; R1: Sel_R1 = 1; R2: Sel_R2 = 1; R3: Sel_R3 = 1; default : err_flag = 1; endcase case (dest) // Select the ALU destination reg R0: Load_R0 = 1; R1: Load_R1 = 1; R2: Load_R2 = 1; R3: Load_R3 = 1; default: err_flag = 1; endcase end // NOT
NOT Instruction
S_dec 3
NOP
src = R0 1
Sel_R0 Sel_Bus_1 Load_Reg_Y
S_ex1 4
0 Sel_R1 Sel_Bus_ 1 Load_Reg_Y
Develop similar descriptions for the remaining states of the ASMD chart
ADD
src = R1 1
RISC_SPM: Memory Unit

RISC_SPM
Controller Load_R0 Load_R1 Load_R2 Load_R3 Load_PC Inc_PC instruction Sel_Bus_1_Mux Load_IR Load_Add_Reg Load_Reg_Y Reg_Y Processor R0 R1 R2 R3 PC IR
RISC_SPM: Memory Unit

module Memory_Unit (data_out, data_in, address, clk, write); parameter word_size = 8; parameter memory_size = 256; output input input input reg [word_size-1: 0] data_out; [word_size-1: 0] data_in; [word_size-1: 0] address; clk, write; [word_size-1: 0] memory [memory_size-1: 0];
01 2 34 Mux_1 Bus_1
assign data_out = memory[address];

opcode
ALU
alu_zero_flag
Memory
mem_word
Load_Reg_Z zero Sel_Bus_2_Mux
Reg_Z
Zflag
always @ (posedge clk) if (write) memory[address] = data_in; endmodule
1 2 Mux_2
Add_R
Bus_2 write

RISC1

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Roadmap

Success is not an accident!

Part 1: Modeling, Verification and Synthesis of Combinational Logic Logic

ECE 4242 / 5242 Fall 2007

Advanced Digital Design Methodology

Part 2: Modeling, Verification, and Synthesis of Sequential Logic Logic

Part 3: Synchronous Finite State Machines and Datapath Controllers

Copyright 2007 Michael D. Ciletti 1

Verilog Models of Combinational and Sequential Logic

Synchronous Finite State Machines

Schematic/Gates Truth Tables Boolean Equations RTL / Dataflow

Primitives UserUser-Defined Primitives (UDPs) Continuous Assignments Cyclic Behaviors

State/Next State Tables State Transition Graphs ASM Charts

ASMD Charts Algorithm

Use cyclic behaviors to model sequential logic.

Datapath Controller (p. 347)

Control signals (FSM outputs) Primary inputs (external) Control Unit

Status signals (FSM inputs) Data outputs

Copyright 2007 Michael D. Ciletti 5

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FSM Controller for a Datapath

ASMD Chart (p. 194)

Maintains a clear/ documented relationship between a datapath and its controller

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Datapath Controller Design

Datapath Control Signals

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Example: Binary Counter

Instruction Set (Specification)

Control Unit FSM

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Binary Counter: Simplified STG

Partitioned Machine ASMD CHART

count <= next_count

count <= next_count

Confusion: Mixed Datapath Operations and FSM

Clarity: Partitioned Datapath and Controller

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ASMD-Based Verilog Model (1 of 2)

ASMD-Based Verilog Model (2 of 2)

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Binary Counter: Simulation Results

Binary CountCount-byby-3 Clocks (Implicit State Machine)

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Simulation Results: CountCount-byby-3 Clocks

Synthesis Result: Count-by-3 Clocks

enable enable_DP dfnf311 rst clk dfnf311 dfnf311

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ASMD Chart (Two Stage Pipeline)

{P1, P0} <= {0, 0}

P1 <= Data P0 <= P1 P1 <= Data P0 <= P1

{P1, P0} <= {0, 0}

P1 <= Data P0 <= P1

R0 <= {P1, P0}

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Complete ASMD Chart