EE 4271 VLSI Design, Fall 2011

Combinational Circuits

Overview
Combinational Circuit Chip Design styles
Full-custom design Cell library based design Programmable Logic Array

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Combinational Circuits
A combinational circuit consists of logic gates whose outputs, at any time, are determined by combining the values of the inputs. For n input variables, there are 2n possible binary input combinations. For each binary combination of the input variables, there is one possible output.

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Combinational Circuits (cont.)

Hence, a combinational circuit can be described by:
1. A truth table that lists the output values for each combination of the input variables, or 2. m Boolean functions, one for each output variable.

n-inputs

Combinational Circuit

m-outputs

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Combinational vs. Sequential Circuits

Combinational circuits are memory-less. Thus, the output value depends ONLY on the current input values. Sequential circuits consist of combinational logic as well as memory elements (used to store certain circuit states). Outputs depend on BOTH current input values and previous input values (kept in the storage elements).

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Combinational vs. Sequential Circuits

n-inputs Combinational Circuit m-outputs (Depend only on inputs)

Combinational Circuit n-inputs m-outputs Next state

Combinational Circuit

Storage Elements

Present state

Sequential Circuit
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Important Design Concepts

Modern digital design deals with various methods and tools that are used to design and verify complex circuits and systems. Concepts:
Design Hierarchy Computer-Aided-Design (CAD) tools Hardware Description Languages (HDLs)

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Design Hierarchy
Divide-and-Conquer approach used to cope with the challenges of designing complex circuits and systems (many times in the order of millions of gates). Circuit is broken into blocks, repetitively.

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Design Hierarchy Example: 9-input odd function (for counting # of 1 in inputs)

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Why is Hierarchy useful?

Reduces the complexity required to design and represent the overall schematic of the circuit. Reuse of blocks is possible. Identical blocks can be used in various places in a design, or in different designs.

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Reusable Functions and CAD

Whenever possible, we try to decompose a complex design into common, reusable function blocks These blocks are
verified and well-documented placed in libraries for future use

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Integrated Circuits
Integrated circuit (a chip) is a semiconductor crystal (most often silicon) containing the electronic components for the digital gates and storage elements which are interconnected on the chip. Terminology - Levels of chip integration
SSI (small-scale integrated) - fewer than 10 gates MSI (medium-scale integrated) - 10 to 100 gates LSI (large-scale integrated) - 100 to thousands of gates VLSI (very large-scale integrated) - thousands to 100s of millions of gates

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Technology Parameters
Specific gate implementation technologies are characterized by the following parameters:
Fan-in the number of inputs available on a gate Fan-out the number of standard loads driven by a gate output Cost for a gate - a measure of the contribution by the gate to the cost of the integrated circuit Propagation Delay The time required for a change in the value of a signal to propagate from an input to an output Power Dissipation the amount of power drawn from the power supply and consumed by the gate

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Propagation Delay
Propagation delay is the time for a change on an input of a gate to propagate to the output. Delay is usually measured at the 50% point with respect to the H and L output voltage levels. High-to-low falling and low-to-high rising delays.

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Propagation Delay Example

IN (volts) OUT (volts)

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1.0 ns per division

Combinational Logic

t (ns)
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Chip Design Styles

Full custom - the entire design of the chip down to the smallest detail of the layout is performed
Expensive, its timing and power is hard to analyze only for dense, fast chips with high sales volume

Standard cell - blocks have been design ahead of time or as part of previous designs
Intermediate cost Less density and speed compared to full custom

Gate array - regular patterns of gate transistors that can be used in many designs built into chip - only the interconnections between gates are specific to a design
Lowest cost Less density compared to full custom and standard cell Prototype design The base of FPGA

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Cell Libraries
Cell - a pre-designed primitive block Cell library - a collection of cells available for design using a particular implementation technology Cell characterization - a detailed specification of a cell for use by a designer

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Cell Library Based Design Procedure

1.

Specification
Write a specification for the circuit if one is not already available

2.

Formulation
Derive a truth table or initial Boolean equations that define the required relationships between the inputs and outputs, if not in the specification

3.

Optimization
Draw a logic diagram or provide a netlist for the resulting circuit using ANDs, ORs, and inverters

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Cell Library Based Design Procedure

4. Technology Mapping
Map the logic diagram to the implementation technology selected Map to CMOS

5. Evaluation
Evaluate the timing and power

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Design Example
1. Specification
BCD to Excess-3 code converter Transforms BCD code for the decimal digits to Excess-3 code for the decimal digits BCD code words for digits 0 through 9: 4-bit patterns 0000 to 1001, respectively Excess-3 code words for digits 0 through 9: 4-bit patterns consisting of 3 (binary 0011) added to each BCD code word

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Design Example (continued)

2.

Formulation
Conversion of 4-bit codes can be most easily formulated by a truth table Variables - BCD: Input BCD Output Excess-3 A,B,C,D ABCD WXYZ Variables 0000 0011 - Excess-3 W,X,Y,Z 0001 0100 0010 0101 Dont Cares - BCD 1010 0011 0110 to 1111 0100 0111

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0101 0110 0111 1000 1001 Combinational Logic

1000 1001 1010 1011 1011

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Design Example (continued)

3. Optimization
a. K-maps
A W = A + BC + BD B+ B X= B C+ D Y = CD + CD Z= D

C
1
0 1 3

1
2

y
6

C
1
0 1

1
3 2

1
4 5 7

1
4 5 7 6

X
12

X
13 8 9

X
15

X
14

B A

X
12

X
13 8 9

X
15

X
14

X
11

X
10

X
11

X
10

D CD

D C

x
1
0 1

1
3 5 7

1
2 6

w
0 1 3

C
2

1
4

1 X
13

1
5 7

1
6

X
12

X
15

X
14

B A

X
12

X
13

X
15

X
14

A
8

1
9

X
11

X
10

1
8

1
9

X
11

X
10

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Design Example (continued)

3. Optimization (continued)
Multiple-level using transformations
W = A + BC + BD B X = BC + D +B Y = CD + C D Z=

CD

D Perform extraction, finding factor:

T1 = C + D W = A + BT1 X = B T1 + B C D Y = CD + C D Z=

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Design Example (continued)

4. Technology Mapping
Map with a library containing inverters and 2-input NAND, and then map it to a CMOS based circuit
A W

C D
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Y Z Z

Technology Mapping Example

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Timing Analysis
Use static timing analysis which has been covered.

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Transmission Gate Based Design Multiplexer

Selects binary information from one of many input lines and directs it to a single output line. Also know as the selector circuit, Selection is controlled by a particular set of inputs lines whose # depends on the # of the data input lines. For a 2n-to-1 multiplexer, there are 2n data input lines and n selection lines whose bit combination determines which input is selected.

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Multiplexer (cont.)

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2-to-1-Line Multiplexer
Since 2 = 21, n = 1 The single selection variable S has two values:
S = 0 selects input I0 S = 1 selects input I1

The equation: Y = S I0 + SI1 The circuit:

Decoder I0
Y S
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Enabling Circuits

I1

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Example: 4-to-1 MUX - Cell Library Based Design

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4to1-Line Multiplexer using Transmission Gates

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MUX as a Universal Gate

We can construct AND and NOT gates using 2-to-1 MUXs. Thus, 2-to-1 MUX is a universal gate.

z = 0x + 1x = x
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z = x1x0 + 0x0 = x1x0

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Programmable Logic Array

The set of functions to be implemented is first transformed to product terms Since output inversion is available, terms can implement either a function or its complement

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Programmable Logic Array Example

To implement
F1= ABC+ABC+ABC=(AB+AC+BC+ABC) F2=AB+AC+BC

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Programmable Logic Array Example

A B

C X X 1 X X

X Fuse intact
Fuse blown

X
X 0

C C B B A A

1 F1

F2

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Summary
Three design styles
Full custom design Gate library based design PLA based design

Transmission gate based design

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