1. Define response time, execution time, throughput, wall clock time, elapsed time.

Response time: Response time is the time between the start and the completion of an event, such as milliseconds for a disk access. Execution time: The time between the start and the completion of an event is referred as Execution time. Throughput: The total amount of work done in a given time. Elapsed time: The latency required completing a task, including disk accesses memory accesses, input/output activities, operating system overhead everything. 2. What is the relationship between execution time and performance? The relationship between execution time and performance is given by,

3. What is CPU time? How it can be classified, with one example.

CPU time: CPU time is the amount of time for which a central processing unit (CPU) was used for processing instructions of a computer program, as opposed to. For example: Waiting for input/output operations. 4. What is meant by system performance? System performance means the complete behavior of a repository system in response to the conditions, processes, and events that may affect it.
5. Define Workload of CPU.

In computing, the workload of CPU is the amount of processing that the computer has been given to do at a given time. The workload consists of some amount of application programming running in the computer and usually some number of users connected to and interacting with the computer's applications. 6. What is the use of Synthetic benchmarks? Give 2 examples. Synthetic benchmarks certainly have their usefulness since the data and performance is capable of being replicated on several different machines. It is also useful since in the world of reviews the reader very rarely has a system identical to that in the review. Examples are 3DMark Vantage, Sisoft Sandra, CineBench R10, SuperPI 7. Define SPEC. What is the use of it?

The Standard Performance Evaluation Corporation (SPEC) is a non-profit organization that aims to "produce, establish, maintain and endorse a standardized set" of performance benchmarks for computers. SPEC benchmarks are widely used to evaluate the performance of computer systems; 8. Define desktop benchmarks? What are the types of it? Desktop benchmarks are real programs modified to be portable and to minimize the effect of I/O on performance. Desktop benchmarks divide into two broad classes: processor-intensive benchmarks and graphics-intensive benchmarks. 9. Define server benchmarks? Server benchmarks are perhaps a processor throughput-oriented processor. Server benchmarks to construct a simple throughput benchmark where the processing rate of a multiprocessor can be measured by running multiple copies (usually as many as there are processors) of each SPEC CPU benchmark and converting the CPU time into a rate. This leads to a measurement called the SPEC rate. 10. Define reproducibility, arithmetic mean, geometric mean Reproducibility: Reproducibility is the process to list everything another experiment would need to duplicate the results. Arithmetic Mean: The arithmetic mean, often referred to as simply the mean or average when the context is clear, is a method to derive the central tendency of a sample space. Geometric Mean: The geometric mean, in mathematics, is a type of mean or average, which indicates the central tendency or typical value of a set of numbers. 11. Define IC,CPI,CPUtime The term ClockCyclesPerInstruction which is the average number of clock cycles each instruction takes to execute, is often abbreviated as CPI. CPI= CPU clock cycles/Instruction count. The number of clock cycles needed to execute a program, we can also count the number of instructions executed is the instruction path length or instruction count(IC). 12. Define Overall CPI

The relative performance effect of a longer branch penalty depends on the overall CPI of the processor. 13. What are the major choices of ISA The major choices of ISA are a stack, an accumulator, or a set of registers. 14. List out the addressing modes. Register, Immediate, Displacement, Register Indirect, Indexed, Direct or Absolute, Memory indirect, Auto Increment, Auto Decrement, Scaled. 15. Explain the addressing mode of signal processing. The addressing modes of signal processing are circular addressing mode and bit reverse addressing mode. Circular addressing mode keeps a start register and an end register with every address register, allowing the auto increment and auto decrement addressing modes to reset when they reach the end of the buffer. In the bit reverse addressing mode the hardware reverses the lower bits of the address with the number of bits reversed depending on the step of FFT algorithm.
16. List out the basic operations in the Instruction set.

17. List out the different types of control change. The different types of control flow change are Conditional branches, Jumps, Procedure Calls, Procedure return. 18. List all types of compiler optimization techniques Peephole optimizations, Local optimizations, Interprocedural or whole-program optimization, Loop optimizations. 19. Define Super pipelining.

Super pipelining simply refers to pipelining that uses a longer pipeline (with more stages) than "regular" pipelining. In theory, a design with more stages, each doing less work, can be scaled to higher clock frequency. However, this depends a lot on other design characteristics, and it isn't true by default that a processor claiming super pipelining is "better" than one that does not. 20. Highlight the ways of maintaining precise exceptions The first is to ignore the problem and settle for imprecise exceptions. A second approach is to buffer the results of an operation until all the operations that were issued earlier are complete. A third technique in use is to allow the exceptions to become somewhat imprecise, but to keep enough information so that the trap-handling routines can create a precise sequence for the exception. The final technique is a hybrid scheme that allows the instruction issue to continue only if it is certain that all the instructions before the issuing instruction will complete without causing an exception. 21. Define History file & Future file. History file: When an exception occurs and the state must be rolled back earlier than some instruction that completed out of order, the original value of the register can be restored from the history file. Future file: It keeps the newer value of a register; when all earlier instructions have completed, the main register file is updated from the future file.
22. Define exception precise and imprecise exceptions, repeat

interval and initiation interval. Exception Precise: Precise exception means that all instructions before the faulting instruction are committed and those after it can be restarted from scratch. Imprecise Exception: An exception is imprecise if the processor state when an exception is raised does not look exactly as if the instructions were executed sequentially in strict program order. Repeat Interval or Initiation Interval: The initiation or repeat interval is the number of cycles that must elapse between issuing two operations of a given type. For example, we will use the latencies and initiation intervals. 23. Define delayed branch If the compiler get the opportunities to improve the performance, then we in use in some processors is called delayed branch. This technique was heavily used in early RISC processors and works reasonably well in the five-stage pipeline. 24. Highlight the 4 ways of dealing branches. Branch-Target Buffers, Return Address Predictors, Integrated Instruction Fetch Units and Speculation Support: Register Renaming versus Reorder Buffers 25. Define Structural, Data & Control Hazards.

Structural hazards arise from resource conflicts when the hardware cannot support all possible combinations of instructions simultaneously in overlapped execution. Data hazards arise when an instruction depends on the results of a previous instruction in a way that is exposed by the overlapping of instructions in the pipeline. Control hazards arise from the pipelining of branches and other instructions that change the PC. 26. Define pipeline interlock and mention its use. Pipeline interlock is a mechanism to detect hazard and resolve it. This mechanism is used to preserve original data dependencies specified in the sequence of the instructions.

27. Define the time/instruction on the pipeline processor.

28. Define pipeline, pipe segment, processor cycle. Pipeline: An activity, item of information, material, or product, that is between the starting point and the completion point is 'in pipeline.' Pipe Segment: Like the assembly line, different steps are completing different parts of different instructions in parallel. Each of these steps is called a pipe stage or a pipe segment. Processor Cycle: The time required between instruction one step down the pipeline is a processor cycle. 29. What are the three classes of instruction of RISC? The three classes of instruction of RISC are ALU operations, Load and Store instructions and Branch & jumps. 30. List out the 5 stages of RISC ACHITECTURE. First, we use separate instruction and data memories, which we would typically implement with separate instruction and data caches. Second, the register file is used in the two stages: one for reading in ID and one for writing in WB. Third To start a new instruction every clock, we must increment and store the PC every clock, and this must be done during the IF stage in preparation for the next instruction. We must also ensure that instructions in different stages of the pipeline do not interfere with one another. This separation is done by introducing pipeline registers between successive stages of the pipeline. 31. Define Effective Address, Fixed field encoding.

Effective Address: The address that is obtained by applying any specified indexing or indirect addressing rules to the specified address; the effective address is then used to identify the current operand. Often fixed length encoding will have only a single size for all instructions; it works best when there are few addressing modes and operations. 32. What is the use of pipeline registers? In the case of a pipelined processor, the pipeline registers also play the key role of carrying intermediate results from one stage to another where the source and destination may not be directly adjacent.
33. Define average instruction execution time, speedup from pipelining, stalls.

Average Instruction Execution time= Clock Cycle * Average CPI Speed up from pipelining is defined as the ratio of the average instruction time unpipelined to the average instruction time pipelined. Speed up=Average Instruction time unpipelined/Average Instruction time pipelined A stall is where one or more pipeline of the stages are prevented from advancing so that some activity can finish, for example so that a hazard condition can be resolved or a multi-cycle operation can occur. 34. List out major hurdles of Pipelining. The major hurdles of pipelining are Pipeline Hazards. There are situations, called hazards that prevent the next instruction in the instruction stream from executing during its designated clock cycle. Hazards reduce the performance from the ideal speedup gained by pipelining. There are three classes of hazards: Structural hazards, data hazards, & control hazards. 35. Define Speed up from pipelining. Speed up from pipelining is defined as the ratio of the average instruction time unpipelined to the average instruction time pipelined. Speed up=Average Instruction time unpipelined/Average Instruction time pipelined 36. What is the alternate to structural hazard? This single register port represents a structural hazard. An alternative scheme is to stall a conflicting instruction when it tries to enter either the MEM or WB stage. If we wait to stall the conflicting instructions until they want to enter the MEM or WB stage, we can choose to stall either instruction. 37. What is the CPI of processor without structural hazard?

38. Define data hazard, forwarding or bypassing of short-circuiting?

Minimizing Data Hazard Stalls by Forwarding. The problem solved with a simple hardware technique called forwarding (also called bypassing and sometimes shortcircuiting). The key insight in forwarding is that the result is not really needed by the DSUB until after the DADD actually produces it. Data hazards arise when an instruction depends on the results of a previous instruction in a way that is exposed by the overlapping of instructions in the pipeline. 39. CPU time is equally dependent upon what characteristics? Why? CPU time is equally dependent on these three characteristics: A 10% improvement in any one of them leads to a 10% improvement in CPU time. Unfortunately, it is difficult to change one parameter in complete isolation from others because the basic technologies involved in changing each characteristic are interdependent: Clock cycle time Hardware technology and organization _ CPI Organization and instruction set architecture _ Instruction count Instruction set architecture and compiler technology 40. If 30 secs of the execution time of a program that takes 60secs in total can use the enhancement. Find the fraction enhancement. Sol: Fraction enhanced=30/60=1/2=0.5 Fraction enhanced<1 0.5<1