Z. Napraviti preskaler (delitelj takta) koji omoguava deljenje osnovne frekvencije frekvencija takta od 50MHz na frekvenciju od 1.5Hz.

Reenje: Broj potrebnih flip flopova (x), a time i duinu vektora za preskaler odreujemo po formuli: 1.5Hz = 50MHz/2x Kada se izrauna x vidi se da je potrebno 25 flip flopova pa je definicija signala u preskaleru sledea:
-- nove kljune rei: signal, std_logic_vector, downto, process, if, -- end if, others, event -- novi operatori: :=, =>, =, <=, + signal clk_scaler : std_logic_vector(24 downto 0) := (others => '0'); preskaler_p: process (clk) begin if clk = '1' and clk'event then clk_scaler <= clk_scaler + 1; end if; end process preskaler_p; jedan_i_po_Hz <= clk_scaler(24);

Z. Napraviti proces koji realizuje dekoder 2 na 4 sa invertovanom logikom na izlazu. Reenje:

-- nove kljune rei: case, when, null signal sel : std_logic_vector(1 downto 0) := "00"; mux_p: process (sel) begin case sel is when "00" => izlaz <= when "01" => izlaz <= when "10" => izlaz <= when "11" => izlaz <= when others => null; end case; end process mux_p;

"1110"; "1101"; "1011"; "0111";

Z. Napraviti proces koji realizuje 4-bitni sinhroni broja sa dozvolom brojanja, asinhronim resetom, sinhronim loadom i izborom smera. Reenje:

-- nove kljune rei: elsif -- novi operatori: -- 4-bitni sinhroni broja sa dozvolom brojanja, -- asinhronim resetom, sinhronim load i smerom -CLK: in STD_LOGIC; -RESET: in STD_LOGIC; -CE, LOAD, DIR: in STD_LOGIC; -DIN: in STD_LOGIC_VECTOR(3 downto 0); signal COUNT : STD_LOGIC_VECTOR(3 downto 0);

process (CLK, RESET) begin if RESET='1' then COUNT <= "0000"; elsif CLK='1' and CLK'event then if CE='1' then if LOAD='1' then COUNT <= DIN; else if DIR='1' then COUNT <= COUNT + 1; else COUNT <= COUNT - 1; end if; end if; end if; end if; end process;

Z. Napraviti proces koji realizuje sinhroni dekoder 3 na 8. Reenje:

-- Sinhroni dekoder 3 na 8 sa Resetom -RESET: in STD_LOGIC; -CLK: in STD_LOGIC; -D_IN: in STD_LOGIC_VECTOR(2 downto 0); -D_OUT: out STD_LOGIC_VECTOR(7 downto 0); process(CLK,RESET,D_IN) begin if ( RESET = '1') then D_OUT <= "00000000"; elsif ( CLK'event and CLK case D_IN is when "000" => D_OUT when "001" => D_OUT when "010" => D_OUT when "011" => D_OUT when "100" => D_OUT when "101" => D_OUT when "110" => D_OUT

='1') then <= <= <= <= <= <= <= "00000001"; "00000010"; "00000100"; "00001000"; "00010000"; "00100000"; "01000000";

when "111" => D_OUT <= "10000000"; when others => NULL; end case; end if; end process;

Z. Napraviti proces koji realizuje sinhroni enkoder 8 na 3. Reenje:

-- Sinhroni enkoder 8 na 3 sa Resetom -RESET: in STD_LOGIC; -CLK: in STD_LOGIC; -D_IN: in STD_LOGIC_VECTOR(7 downto 0); -D_OUT: out STD_LOGIC_VECTOR(2 downto 0); process(CLK,RESET,D_IN) begin if ( RESET = '1') then D_OUT <= "000"; elsif ( CLK'event and CLK ='1') then case D_IN is when "00000001" => D_OUT <= "000"; when "00000010" => D_OUT <= "001"; when "00000100" => D_OUT <= "010"; when "00001000" => D_OUT <= "011"; when "00010000" => D_OUT <= "100"; when "00100000" => D_OUT <= "101"; when "01000000" => D_OUT <= "110"; when "10000000" => D_OUT <= "111"; when others => NULL; end case; end if; end process;

Z. Napraviti proces koji realizuje 4-bitni pomeraki registar sa serijskim ulazom i serijskim izlazom. Reenje:
-- novi operator: & -- 4-bitni pomeraki registar sa serijskim ulazom i izlazom i -- mogunou unosa -CLK: in STD_LOGIC; -DIN: in STD_LOGIC; -LOAD: in STD_LOGIC; -LOAD_DATA: in STD_LOGIC_VECTOR(3 downto 0); -DOUT: out STD_LOGIC;

signal REG: STD_LOGIC_VECTOR(3 downto 0);

process (CLK) begin if CLK'event and CLK='1' then if (LOAD='1') then REG <= LOAD_DATA; else REG <= REG(2 downto 0) & DIN; end if; end if; DOUT <= REG(3); end process;

Z. Deklarisati ROM memoriju koja ima 8 rei duine 28 bita i potom inicijalizovati te rei kao tako da svaka bude rezultat lepljenja* po 4 slova tj. 4 7-bitne konstante za ispis odgovarajuih slova na sedmosegmentnim displejima prema tabeli: adresa 0 1 2 3 4 5 6 7
*

28 bitna re off off off off off off off d off off d C off d C b d C b A C b A off b A off off A off off off

operator lepljenja (concatenate) je &

Reenje:
-- nove kljune rei: constant, type, array -- novi operatori: & constant constant constant constant constant slovo_a slovo_b slovo_c slovo_d off: : std_logic_vector (6 downto 0) : std_logic_vector (6 downto 0) : std_logic_vector (6 downto 0) : std_logic_vector (6 downto 0) STD_LOGIC_VECTOR := "1111111"; := := := := "0001000"; "0000011"; "1000110"; "0100001";

type niz_t is array (0 to 7) of std_logic_vector(27 downto 0); constant niz : niz_t := (off & off & off & off, off & off & off & slovo_d, off & off & slovo_d & slovo_c, off & slovo_d & slovo_c & slovo_b, slovo_d & slovo_c & slovo_b & slovo_a, slovo_c & slovo_b & slovo_a & off, slovo_b & slovo_a & off & off, slovo_a & off & off & off);

Z. Koristei ROM memoriju iz prethodnog zadatka, 3-bitni signal cnt koji sadri adresu i neki 28-bitni signal, napisati kako taj signal dobija vrednost iz ROMa . Reenje: Potrebno je koristiti funkciju conv_integer iz biblioteke IEEE.STD_LOGIC_UNSIGNED koja konvertuje std_logic_vector u integer koji je potreban za indeksiranje niza (adresiranje ROMa).
-- nove kljune rei: conv_integer signal vektor : std_logic_vector(27 downto 0);

...
vektor <= niz(conv_integer(cnt));

Z. Napisati VHDL program koji realizuje ROM modul 32*8 koji ima sve uobiajene signale za rad sa ROM.
-- nove kljune rei: entity, port, in, out, architecture entity ROM is port( Clock : Reset : Enable : Read : Address : Data_out: ); end entity ROM; in std_logic; in std_logic; in std_logic; in std_logic; in std_logic_vector(4 downto 0); out std_logic_vector(7 downto 0)

architecture Beh of ROM is type ROM_Array is array (0 to 31) of std_logic_vector(7 downto 0); constant Content: ROM_Array := ( 0 => "00000001", 1 => "00000010", 2 => "00000011", 3 => "00000100", 4 => "00000101", 5 => "00000110", 6 => "00000111", 7 => "00001000", 8 => "00001001", 9 => "00001010", 10 => "00001011", 11 => "00001100", 12 => "00001101", 13 => "00001110", 14 => "00001111",

OTHERS => "11111111" ); begin process(Clock, Reset, Read, Address) begin if( Reset = '1' ) then Data_out <= "ZZZZZZZZ"; elsif( Clock'event and Clock = '1' ) then if Enable = '1' then if( Read = '1' ) then Data_out <= Content(conv_integer(Address)); else Data_out <= "ZZZZZZZZ"; end if; end if; end if; end process; end architecture Beh;

Z. Napisati VHDL program koji realizuje RAM modul 4*4. Reenje: U okviru generic dela entity mogu se zadavati razni parametri za dati VHDL program. U ovom primeru zadata je irina brojaa u bitima. Na ovaj nain mogue je parametrizovanje VHDL programa.
-- nove kljune rei: generic, integer, range entity RAM is generic( width: integer:=4; depth: integer:=4; addr: integer:=2); port( Clock: in std_logic; Enable: in std_logic; Read: in std_logic; Write: in std_logic; Read_Addr: in std_logic_vector(addr-1 downto 0); Write_Addr: in std_logic_vector(addr-1 downto 0); Data_in: in std_logic_vector(width-1 downto 0); Data_out: out std_logic_vector(width-1 downto 0) ); end entity RAM; architecture beh of RAM is -- koristiti array za definisanje signala od kojeg e u procesu -- nastati RAM type ram_type is array (0 to depth-1) of std_logic_vector(width-1 downto 0); signal tmp_ram: ram_type; begin

-- read deo process(Clock, Read) begin if (Clock'event and Clock='1') then if Enable='1' then if Read='1' then -- funkcija conv_integer menja tip -- iz std_logic_vector u integer Data_out <= tmp_ram(conv_integer(Read_Addr)); else Data_out <= (Data_out'range => 'Z'); end if; end if; end if; end process; -- write deo process(Clock, Write) begin if (Clock'event and Clock='1') then if Enable='1' then if Write='1' then tmp_ram(conv_integer(Write_Addr)) <= Data_in; end if; end if; end if; end process; end architecture beh;

Z. Napisati deo programa koji realizuje paralelno-serijsku konverziju.

if load = '0' then shift_reg <= parallel; elsif (clock'event and clock = '1') then serial <= shift_reg(7); shift_reg(7 downto 1) <= shift_reg(6 downto 0); end if;

Z. Napisati deo programa koji realizuje jednostavan 4-bitni broja unazad sa TC (terminal count) izlazom.

if load = '0' then

output <= "1111"; elsif (clock'event and clock = '1') then output <= data - '1'; end if; carry <= '0' when output = "0000" else '1'; load <= carry;

Z. Napisati deo programa koji realizuje jednobitni sabira.

-- novi operatori: and, or if c = '0' then if (a and b) = '1' then sum <= '0'; carry <= '1'; elsif (a or b) = '1' then sum <= '1'; carry <= '0' end if; elsif c = '1' then if (a and b) = '1' then sum <= '1'; carry <= '1'; elsif (a or b) = '1' then sum <= '0'; carry <= '1'; end if; end if;

Z. Napisati VHDL program koji realizuje jednostavnu aritmetiko-logiku jedinicu koja ima mogunost izvravanja operacija sabiranja, oduzimanja, logikog i i logike ili operacije.
-- novi operatori: not entity ALU is port( A: in std_logic_vector(1 downto 0); B: in std_logic_vector(1 downto 0); Sel: in std_logic_vector(1 downto 0); Res: out std_logic_vector(1 downto 0) ); end entity ALU; architecture beh of ALU is begin process(A,B,Sel)

begin case Sel is when "00" => Res <= A + B; when "01" => Res <= A + (not B) + 1; when "10" => Res <= A and B; when "11" => Res <= A or B; when others => Res <= "XX"; end case; end process; end architecture beh;

Z. Napraviti 3-bitni up/down counter gde se smer brojanja bira prekidaem, a frekvencija rada je 1.5Hz. Osnovna frekvencija takta je 50MHz. Reenje:
signal cnt : std_logic_vector(2 downto 0) := (others => '0'); cnt_p: process (clk) is variable odbrojao : std_logic; begin if clk = '1' and clk'event then if clk_scaler(24) = '1' and odbrojao = '0' then if prekidac = '1' then cnt <= cnt + 1; else cnt <= cnt - 1; end if; odbrojao := '1'; elsif clk_scaler(24) = '0' then odbrojao := '0'; end if; end if; end process cnt_p;

Z. Napraviti program koji na svaki pritisak tastera vri invertovanje (toggle) nekog signala pom. Realizacija treba da bude sekvencijalna i taktovana sa osnovnim taktom od 50MHz. Reenje:
signal pom : std_logic := '0'; btn_p: process (btn) is variable stisnut : std_logic; begin

if clk'event and clk = '1' then if btn = '1' and stisnut = '0' then pom <= not pom; stisnut := '1'; elsif btn = '0' then stisnut := '0'; end if; end if; end process btn_p;

Z. Napraviti 3-bitni up/down counter gde se smer brojanja bira tasterom, a frekvencija rada je 1.5Hz. Koristiti proces iz prethodnog zadatka. Osnovna frekvencija takta je 50MHz. Reenje:
signal cnt : std_logic_vector(2 downto 0) := (others => '0'); signal pom : std_logic := '0'; ... cnt_p: process (clk) is variable odbrojao : std_logic; begin if clk = '1' and clk'event then if clk_scaler(24) = '1' and odbrojao = '0' then if pom = '1' then cnt <= cnt + 1; else cnt <= cnt - 1; end if; odbrojao := '1'; elsif clk_scaler(24) = '0' then odbrojao := '0'; end if; end if; end process cnt_p;

Z. Napisati program koji realizuje broja gde je irina u bitima parametar koji se zadaje u generic delu u entity. Reenje: Nekada je korisno definisanje i podtipa (subtype) za podrebe odreenih signala. U ovom primeru e biti korien podtip od integer-a. U reenju e biti koriena i funkcija to_unsigned koja pretvara integer u unsigned sa zadatom irinom.
-- nove kljune rei: subtype, rising_edge -- novi operator: ** library ieee;

use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity test_counter generic ( width : port ( clk : reset : enable : count : end test_counter; is integer := 12 ); in std_ulogic; in std_ulogic; in std_ulogic; out std_logic_vector ( width - 1 downto 0) );

architecture rtl of test_counter is constant terminal_count : integer := 2**width - 1; subtype counter_range is integer range 0 to terminal_count; signal count_int : counter_range; begin -- rtl count <= std_logic_vector (to_unsigned ( count_int, width )); counter : process ( clk, reset ) begin if reset = '0' then count_int <= 0; elsif rising_edge ( clk ) then if enable = '1' then if count_int = terminal_count then count_int <= 0; else count_int <= count_int + 1; end if; end if; end if; end process counter; end rtl;

Z. Napisati program koji realizuje shift registar sa serijskim ulazom i serijaskim izlazom gde je irina u bitima parametar koji se zadaje u generic delu u entity. Reenje:
-- nove kljune rei: high, unsigned library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity test_shift is generic ( width : integer := 9 ); port ( clk : in std_ulogic; inp : in std_logic; outp : out std_ulogic ); end test_shift; architecture rtl of test_shift is

signal shift_reg : unsigned ( width downto 0 ); begin outp <= shift_reg (shift_reg'high); shifter : process ( clk ) begin if rising_edge ( clk ) then shift_reg <= shift_reg(width 2 downto 0) & inp; end if; end process shifter; end architecture rtl;

Z. Napisati VHDL program koji realizuje automat stanja korienjem pristupa sa dva procesa. Automat ima jedan ulaz, jedan izlaz i 4 stanja. Izlaz x je jednak 1 samo u 3. stanju, a iz pethodnog stanja se prelazi u naredno ukoliko je ulaz a = 1 , u suprotnom ostaje u trenutnom stanju (nacrtati bubble dijagram!)
entity seq_design is port( a: in std_logic; clock: in std_logic; reset: in std_logic; x: out std_logic ); end entity seq_design; architecture FSM of seq_design is -- definisemo stanja type stanja_type is (S0, S1, S2, S3); signal naredno_stanje, trenutno_stanje: stanja_type; begin -- proces #1: registar stanja state_reg_p: process(clock, reset) begin if (reset='1') then trenutno_stanje <= S0; elsif (clock'event and clock='1') then trenutno_stanje <= naredno_stanje; end if; end process state_reg_p; -- proces #2: kombinaciona logika za odredjivanje -- narednog stanja i izlaza comb_logic_p: process(trenutno_stanje, a) begin case trenutno_stanje is when S0 => x <= '0'; if a='0' then naredno_stanje <= S0; elsif a ='1' then naredno_stanje <= S1;

end if; when S1 => x <= '0'; if a='0' then naredno_stanje <= S1; elsif a='1' then naredno_stanje <= S2; end if; when S2 => x <= '0'; if a='0' then naredno_stanje <= S2; elsif a='1' then naredno_stanje <= S3; end if; when S3 => x <= '1'; if a='0' then naredno_stanje <= S3; elsif a='1' then naredno_stanje <= S0; end if; when others => x <= '0'; naredno_stanje <= S0; end case; end process; end architecture FSM;

ZADACI U VEZI SA RAZVOJNIM SISTEMOM Z. Napraviti proces koji omoguava ispis vrednosti na 4 segmosegmentna displeja u multipleksnom reimu rada. Perioda odabiranja u multipleksnom reimu bi trebalo da je u opsegu 1-16 ms. Pogledati reference manual za DIO4. Reenje:
signal signal signal signal cifra1 cifra2 cifra3 cifra4 : : : : std_logic_vector(6 std_logic_vector(6 std_logic_vector(6 std_logic_vector(6 downto downto downto downto 0) 0) 0) 0) := := := := (others (others (others (others => => => => '0'); '0'); '0'); '0');

disp_p: process (clk_scaler(16 downto 15)) begin case clk_scaler(16 downto 15) is when "00" => AN <= "1110"; SEG <= cifra1; when "01" => AN <= "1101"; SEG <= cifra2; when "10" => AN <= "1011"; SEG <= cifra3; when "11" => AN <= "0111"; SEG <= cifra4; when others => AN <= "1111"; SEG <= off; end case; end process disp_p;

Z. Na DIO4 ekspanzionoj kartici koristi se 4-cifreni 7-segmentni displej u multipleksnom reimu rada. Dakle vrednost segmenata se prosleuje istovremeno na sve cifre, a koja e da svetli se odreuje pomou 4 bita (an u prethodnom primeru). Zbog tromosti oka mogue je tako podesiti prikaz da se vrednost koja je ispisana na displeju vidi bez treperenja iako je u stvari primenjen sukscesivno pojedinaan ispis na svakoj cifri posebno. Vie detalja o ovome pogledati u reference manualu za DIO4 karticu. Realizovati ispis rei NULA. Reenje:
entity slova is Port ( mclk control_led seg an end slova; : : : : in std_logic; -- takt 50MHz out std_logic; out std_logic_vector(6 downto 0); out std_logic_vector(3 downto 0));

architecture Behavioral of slova is --KONSTANTE constant slovo_a constant slovo_n constant slovo_l constant slovo_u : : : : STD_LOGIC_VECTOR STD_LOGIC_VECTOR STD_LOGIC_VECTOR STD_LOGIC_VECTOR := := := := "0001000"; "0101011"; "1000111"; "1000001";

-- SIGNALI signal clk_scaler : STD_LOGIC_VECTOR (22 downto 0) := (others => '0'); begin --preskaler takta od 50MHza preskaler_p: process(mclk) begin if mclk'event and mclk = '1' then clk_scaler <= clk_scaler + 1; end if; end process preskaler_p; control_led <= clk_scaler(22); -- multipleksni ispis na displej ispis_ p: process(clk_scaler(16 downto 15)) begin case clk_scaler(16 downto 15) is when "00" => an <= "1110"; seg <= slovo_n; when "01" => an <= "1101"; seg <= slovo_u; when "10" => an <= "1011"; seg <= slovo_l; when "11" => an <= "0111"; seg <= slovo_a; when others => an <= "1111"; end case; end process preskaler_p; end architecture Behavioral;

Z. Napisati program koji 4-bitni broj koji se formira na osnovu poloaja 4 prekidaa pretvara u odgovarajuu heksadecimalnu cifru i prikazuje je na displeju.
entity hex2led is Port (mclk : in std_logic; -- takt 50MHz hex : in std_logic_vector(3 downto 0); -- ulaz sa prekidaca an : out std_logic_vector (3 downto 0); -- aktivacija cifre led : out std_logic_vector(6 downto 0); -- 7 seg vrednost control_led : out std_logic); -- blink ledovka za kontrolu end hex2led; architecture Behavioral of hex2led is constant constant constant constant constant constant constant constant constant constant constant constant nula : std_logic_vector (6 downto 0) := "1000000"; jedan : std_logic_vector (6 downto 0) := "1111001"; dva : std_logic_vector (6 downto 0) := "0100100" ; tri : std_logic_vector (6 downto 0) := "0110000"; cetiri: std_logic_vector (6 downto 0) := "0011001"; pet : std_logic_vector (6 downto 0) := "0010010"; sest: std_logic_vector (6 downto 0) := "0000010"; sedam : std_logic_vector (6 downto 0) := "1111000"; osam : std_logic_vector (6 downto 0) := "0000000"; devet : std_logic_vector (6 downto 0) := "0010000"; a : std_logic_vector (6 downto 0) := "0001000"; b : std_logic_vector (6 downto 0) := "0000011";

constant constant constant constant constant

c : d : e : f : off

std_logic_vector (6 downto 0) := "1000110"; std_logic_vector (6 downto 0) := "0100001"; std_logic_vector (6 downto 0) := "0000110"; std_logic_vector (6 downto 0) := "0001110"; : std_logic_vector (6 downto 0) := "1111111";

signal count : std_logic_vector (22 downto 0); begin an <= "1110"; -- aktivna samo prva cifra process (mclk) begin if mclk'event and mclk = '1' then count <= count + 1; end if; end process; control_led <= count (22); process (hex) begin case hex is when "0000" when "0001" when "0010" when "0011" when "0100" when "0101" when "0110" when "0111" when "1000" when "1001" when "1010" when "1011" when "1100" when "1101" when "1110" when "1111" when others end case; end process; end Behavioral;

=> => => => => => => => => => => => => => => => =>

led led led led led led led led led led led led led led led led led

<= <= <= <= <= <= <= <= <= <= <= <= <= <= <= <= <=

nula; jedan; dva; tri; cetiri; pet; sest; sedam; osam; devet; a; b; c; d; e; f; off;

Z. Napisati program koji realizuje blinkanje jedne od dve rei, jednom od dve frekvencije. Biranje rei se vri prekidaem1, a frekvencije prekidaem2 prema tabeli. pr1 0 1 Reenje: Re AbCd dECA pr0 Frekvencija 0 1.5 Hz 1 6 Hz

constant constant constant constant constant constant signal signal signal signal signal signal signal signal signal signal ...

slovo_a slovo_b slovo_c slovo_d slovo_e off:

: std_logic_vector (6 downto 0) : std_logic_vector (6 downto 0) : std_logic_vector (6 downto 0) : std_logic_vector (6 downto 0) : std_logic_vector (6 downto 0) STD_LOGIC_VECTOR := "1111111";

:= := := := :=

"0001000"; "0000011"; "1000110"; "0100001"; "0000110";

clk_scaler : std_logic_vector (24 downto 0) := (others => '0'); cifra1: STD_LOGIC_VECTOR (6 downto 0) := "0000000"; cifra2: STD_LOGIC_VECTOR (6 downto 0) := "0000000"; cifra3: STD_LOGIC_VECTOR (6 downto 0) := "0000000"; cifra4: STD_LOGIC_VECTOR (6 downto 0) := "0000000"; slovo_1: STD_LOGIC_VECTOR (6 downto 0) := "0000000"; slovo_2: STD_LOGIC_VECTOR (6 downto 0) := "0000000"; slovo_3: STD_LOGIC_VECTOR (6 downto 0) := "0000000"; slovo_4: STD_LOGIC_VECTOR (6 downto 0) := "0000000"; pom : std_logic := '0';

preskaler_p: process (clk) begin if clk = '1' and clk'event then clk_scaler <= clk_scaler + 1; end if; end process preskaler_p; disp_p: process (clk_scaler(16 downto 15)) begin case clk_scaler(16 downto 15) is when "00" => AN <= "1110"; SEG <= cifra1; when "01" => AN <= "1101"; SEG <= cifra2; when "10" => AN <= "1011"; SEG <= cifra3; when "11" => AN <= "0111"; SEG <= cifra4; when others => AN <= "1111"; SEG <= off; end case; end process disp_p; pr0_p: process (pom, slovo_1, slovo_2, slovo_3, slovo_4) begin if pom = '1' then cifra1 <= slovo_1; cifra2 <= slovo_2; cifra3 <= slovo_3; cifra4 <= slovo_4; else cifra1 <= off; cifra2 <= off; cifra3 <= off; cifra4 <= off;

end if; end process pr0_p; pom <= clk_scaler(22) when pr0 = '1' else clk_scaler(24); pr1_p: process (pr1) begin if pr1 = '1' then slovo_1 slovo_2 slovo_3 slovo_4 else slovo_1 slovo_2 slovo_3 slovo_4 end if; end process pr1_p;

<= <= <= <= <= <= <= <=

slovo_a; slovo_b; slovo_c; slovo_d; slovo_d; slovo_e; slovo_c; slovo_a;

Z. Napisati VHDL program koji realizuje FIR filter .

-- VHDL Data-Flow modeling -- KEYWORD: -- generate, array, range, constant and subtype entity FIR_filter is port( rst: clk: coef_ld: start: o_enable: bypass: Xn_in: Yn_in: Xn_out: Yn_out: ); end FIR_filter; in in in in in in in in out out std_logic; std_logic; std_logic; std_logic; std_logic; std_logic; std_logic_vector(3 downto 0); std_logic_vector(15 downto 0); std_logic_vector(3 downto 0); std_logic_vector(15 downto 0)

architecture BEH of FIR_filter is constant K: integer := 4; -- circuit has four stages

-- use type and subtype to define the complex signals subtype bit4 is subtype bit8 is subtype bit16 is type type type type type klx4 kx8 klx8 kx16 klx16 is is is is is std_logic_vector(3 downto 0); std_logic_vector(7 downto 0); std_logic_vector(15 downto 0); array array array array array (K downto 0) of bit4; (K-1 downto 0) of bit8; (K downto 0) of bit8; (K-1 downto 0) of bit16; (K downto 0) of bit16;

-- define signal in type of arrays signal REG1, REG2, COEF : klx4; signal MULT8 : kx8; signal MULT16 : kx16; signal SUM : klx16; signal Xn_tmp : bit4; signal Yn_tmp : bit16; begin -- initialize the first stage of FIR circuit REG2(K) REG1(K) SUM(K) COEF(K) <= Xn_in when (start='1') else (REG2(K)'range => '0'); <= (REG1(K)'range => '0'); <= Yn_in; <= Xn_in;

-- start the computation, use generate to obtain the -- multiple stages gen8: for j in K-1 downto 0 generate

stages: process (rst, clk) begin if (rst='0') then REG1(j) <= (REG1(j)'range => '0'); REG2(j) <= (REG2(j)'range => '0'); COEF(j) <= (COEF(j)'range => '0'); MULT16(j) <= (MULT16(j)'range => '0'); SUM(j) <= (SUM(j)'range => '0'); elsif (clk'event and clk ='1') then REG1(j) <= REG2(j+1); REG2(j) <= REG1(j); if (coef_ld = '1') then COEF(j) <= COEF(j+1); end if; MULT8(j) <= signed(REG1(j))*signed(COEF(j)); MULT16(j)(7 downto 0) <= MULT8(j); if (MULT8(j)(7)='0') then MULT16(j)(15 downto 8) <= "00000000"; else MULT16(j)(15 downto 8) <= "11111111"; end if; SUM(j) <= signed(MULT16(j))+signed(SUM(j+1)); end if; end process; end generate; -- control the outputs by concurrent statements Xn_tmp <= Xn_in when bypass = '1' else REG2(0) when coef_ld = '0' else COEF(0); when bypass = '1' else SUM(0);

Yn_tmp <= Xn_out <= Yn_out <= end BEH;

Yn_in

Xn_tmp when o_enable = '0' else (Xn_out'range => 'Z'); Yn_tmp when o_enable = '0' else (Yn_out'range => 'Z');

------------------------------------------------------------------