ELE 4550 ASIC Technologies Project Tutorial

Simple Shift-add Multiplier

0011 (Multiplicand) x 0111 (Multiplier) 0011 0011 0011 + 0000 00010101 Disadvantage: number of addition depends on number of bits of multiplication which cannot be reduced. .

Booth Multiplier
Compared to shift add multiplier, booth multiplier can reduce the number of multiplier in average. Here is its algorithm.

2s complement representation of multiplier:

b = 2 n bn + 2 n 1 bn 1 + 2 n 2 bn 2 + ... + 2 0 b0
consider the term 2n, it can be rewritten as: 2n = 2n+1 2n based on this property, we can recode every set bit in the multiplier as +2 -1 for example: 0 0 1 1 1 +1 +1 +1 +1 0 1 -1 0 0 0 -1 0 0 (recoded multiplier) -1 -1 1 -1 0 0 (Multiplier)

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ELE 4550 ASIC Technologies Project Tutorial As shown above, less 1 in the recoded multiplier, this implied that less addition is needed.

Example: 6 x 14 = 84 0 x 0 +1 0 1 0 1 1 1 1 0 0 0 (Multiplicand) (Multiplier) (recoded multiplier)

0 -1

0 1 1 1 0 0 + 0 0 0 0 0 1 1 1 0 0 1 0 1 0 0 0 1

0 0 0 0

0 1 0

0 0

0 (sign extension)

. 0 1 0 0 (84)

Question: What is the worst case for booth multiplier?

Hardware algorithm

Multiplicand

Zero

- Multiplicand

Partial Product Multiplexer

Multiplier

Adder

DFF

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ELE 4550 ASIC Technologies Project Tutorial

Radix -4 Modified Booth Algorithm

Can design n-bit synchronous multiplier that generates exactly n/2 partial products.

Example

Note: The results must be obtained after a fixed cycles through the pipeline!!! Eg: 16*16bit Raix-4 booth multiplier can get the result after 8 cycles.

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