LAB

EEE241 DIGITAL LOGIC DESIGN

LAB Report # 07

Submitted by: ABDULLAH KHALID

Roll no: FA17-BCS-005
Section: 3A Submitted to: Mr. Shahid Mehmood
Objectives
Part 1
This experiment is to design gate-level hierarchal description of a 4-bit binary adder / Subtractor in HDL
and implement it on FPGA

Part 2
Introduce the different Verilog keywords (Parameter, always etc) and use them to simulate the
incremental function in Verilog.

Pre-Lab:
Background theory:
Binary Adder is digital circuit that produces the arithmetic sum of two binary numbers. It can be
constructed with full adders connected in cascade, with the output carry from each full adder connected
to the input carry of the next full adder in the chain. The process of addition proceeds on a bit-by-bit
basis, right to left, beginning with the least significant bit. After the least significant bit, addition at each
position adds not only the respective bits of the words, but also consider a possible carry bit from
addition at the previous position. Addition of n-bit binary numbers requires the use of a n full adder, or a
chain of one-half adder and n-1 full adders. The four-bit adder is an example of a standard component. It
can be used in many applications involving arithmetic operations.

Binary Adder/Subtractor can be combined into one circuit with one common binary adder by including
an exclusive-OR gate with each full adder. A four-bit adder/subtractor circuit of two binary numbers
A(A3A2A1A0) and B(B3B2B1B0) is shown in Figure 7.1. The mode input M controls the operation. When M =
0, the circuit is an adder. As B 0 = B, C0 = 0 , full adders receive the value of B, and the circuit performs
A + B. when M = 1, the circuit becomes a subtractor. Now we have B 1 = B’ and C0 = 1. The B inputs
are all complemented and a 1 is added through the input carry (C 0 ). The circuit performs the operation A
plus the 2’s complement of B i.e A-B .The exclusive-OR with output V is for detecting an overflow and C
is carry out.

Full Adder (4bit Verilog Code)

It was implemented on 7 segment display of Nexys2 FPGA board.
Test Fixture

0001
+0100
_______
0101
_______
The Result is same as on simulator and on 7th display on FPGA.

Full Subtractor
It was done by taking the 2’s complement of second no.

a= 1111, b = 1011
sum = a -b = a + (-b) = 1111 + (-1011)

Taking 1’s complement of 0011 which is 0100 and then adding +1 to get 2’s complement.
0100 1111
+0001 + 0101
____ _______
0101 discard (1) 0100
____ ________

The Result is as same on simulator