Digital Logic Design

Lab Assignment no. 3

Name: ZAIN AFZAL

Registration Number: F18-BCS-109

Presented to:

Date: 11October 2019

 In Lab-Tasks
Verification of all the basic logic gates using the XILINX ISE simulation tool and
verified by using waveform with logic gates truth table.

AND gate

Task 01:

Verilog code for AND gate:

Task 02: Test bench/stimulus for AND gate:

OR gate

Task 01: Verilog code for OR gate:

Task 02: Test bench/stimulus for OR gate:

NOT gate

Task 01: Verilog code for NOT gate:

Task 02: Test bench/stimulus for NOT gate:

NOR gate

Task 01: Verilog code for NOR gate:

Task 02: Test bench/stimulus for NOR gate:

NAND gate

Task 01: Verilog code for NAND gate:

Task 02: Test bench/stimulus for NAND gate:
 XOR gate

Task 01: Verilog code for XOR gate:

Task 02: Test bench/stimulus for XOR gate:

XNOR gate
Task 01: Verilog code for XNOR gate:

Task 02: Test bench/stimulus for XNOR gate:

TASK 03

Task 03: Run simulation of XNOR gate:

One cycle is of 200ns.

Task 03: Run simulation of NAND gate:

One cycle is of 300ns.

Task 03: Run simulation of XOR gate:

One cycle is of 200ns.

Task 03: Run simulation of XNOR gate:

One cycle is of 200ns.

Task 03: Run simulation of NOT gate:

Gate Level Diagram:

XNOR: NOT:

NOR:

XOR:

NAND: