EXPERIMENT – 1

NAME:CH VENUGOPAL
REG. NO.: 22BCE9142
SLOT: L25 + L26

LOGIC GATES
AND GATE
Testbench code for AND gate:

Design code for AND gate:

Result:

OR GATE
Testbench code for OR gate:
Design code for OR gate:

Result:
NOT GATE
Testbench code for NOT gate:

Design code for NOT gate:

Result:

NAND GATE
Testbench code for NAND gate:
Design code for NAND gate:

Result:
NOR GATE
Testbench code for NOR gate:
Design code for NOR gate:

Result:
XOR GATE
Testbench code for XOR gate:

Design code for XOR gate:

Result:

XNOR GATE
Testbench code for XNOR gate:
Design code for XNOR gate:

Result:
 EXPERIMENT 2
NAME :ch venugopal
REG. NO:22BCE9142
SLOT : L25+L26

HALF ADDER
Testbench code for HALF ADDER:

Design code for HALF ADDER:

Result:

FULL ADDER
Testbench code for FULL ADDER:
Design code for FULL ADDER:

Result:
HALF SUBTRACTOR
Testbench code for HALF SUBTRACTOR:
Design code for HALF SUBTRACTOR:

Result:
FULL SUBTRACTOR
Testbench code for FULL SUBTRACTOR:
Design code for FULL SUBTRACTOR:

Result:
 DLD LAB ASSSIGNMENT
CH VENUGOPAL
22BCE9142

RIPPLE CARRY ADDER:

EP WAVE:
 RIPPLE CARRY SUBTRACTOR:

EP WAVE:
 ENCODER AND DECODER
NAME : CH VENUGOPAL
REG.NO : 22BCE9142
SLOT : L25+26

ENCODER
Design code:

Testbench code:
Result:

Wave form:
DECODER
Design code:

Testbench code:
Result:

Wave form: