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Student Name: ABHISHEK Branch: BE CSE


UID: 20BCS7817 Section/Group: 40A
Date of Performance: 19/10/2020 Subject Name: DIGITAL
ELECTRONICS LAB

Aim
Validate truth table for:

 NAND gates HD74LS00


 NOR gates HD74LS02
 NOT gates HD74LS04
 AND gates HD74LS08
 XOR gates HD74LS86

Task to be done
To understand the work of logic gates and verify the truth table of the following gates

 NAND gates HD74LS00


 NOR gates HD74LS02
 NOT gates HD74LS04
 AND gates HD74LS08
 XOR gates HD74LS86

Requirements
HARDWARE REQUIREMENTS:
 IC for 7400, 7402, 7404, 7408, 7486,
 Breadboard
 Connecting wires
 2 momentary switches
 LED

SOFTWARE REQUIREMENTS:
 TINKERCAD
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CircuitDiagram/BlockDiagram
 DIAGRAM OF NAND GATE (HD74LS00)

 DIAGRAM OF NOR GATE (HD74LS02)

 DIAGRAM OF NOT GATE (HD74LS04)


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 DIAGRAM OF AND GATE (HD74LS08)

 DIAGRAM OF XOR GATE (HD74LS86)


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Simulation Results:

FOR NAND GATE:


Both inputsHIGH OUTPUT LOW

One inputLOW & other inputHIGH OUTPUT HIGH

One inputHIGH & other inputLOW OUTPUT HIGH

Both inputsLOW OUTPUT LOW

FOR N0R GATE:


Both inputsHIGH OUTPUT LOW

One inputLOW & other inputHIGH OUTPUT LOW

One inputHIGH & other inputLOW OUTPUT LOW

Both inputsLOW OUTPUT HIGH

FOR NOT GATE:

INPUTLOW OUTPUT HIGH

INPUTHIGH OUTPUT LOW


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FOR AND GATE:


Both inputsHIGH OUTPUT HIGH

One inputLOW & other inputHIGH OUTPUT LOW

One inputHIGH & other inputLOW OUTPUT LOW

Both inputsLOW OUTPUT LOW

FOR XOR GATE:


Both inputsHIGH OUTPUT LOW

One inputLOW & other inputHIGH OUTPUT HIGH

One inputHIGH & other inputLOW OUTPUT HIGH

Both inputsLOW OUTPUT LOW


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Concept used
The basic logic gates are the building blocks of more complex logic circuits. These logic
gates perform the basic Boolean functions, such as AND, OR, NAND, NOR, Inversion,
Exclusive-OR, Exclusive-NOR. Each gate has one or two binary inputs, A and B, and
one binary output, C. The small circle on the output of the circuit symbols designates the
logic complement. The AND, OR, NAND, and NOR gates can be extended to have more
than two inputs. A gate can be extended to have multiple inputs if the binary operation it
represents is commutative and associative
 NAND GATE
The Logic NAND Gate is the reverse or “Complementary” form of the AND gate. The logic or
Boolean expression given for a logic NAND gate is that for Logical Addition, which is the
opposite to the AND gate, and which it performs on the complements of the inputs.
“If either A or B are NOT true, then Q is true”

 NOR GATE

The Logic NOR Gate is the reverse or “Complementary” form of the inclusive OR gate. The
logic or Boolean expression is given for a logic NOR gate is that for Logical Multiplication
which it performs on the complements of the inputs

“If both A and B are NOT true, then Q is true”

 NOT GATE
Inverting NOT gates are single-input devices which have an output level that is normally
at logic level “1” and goes “LOW” to a logic level “0” when its single input is at logic level
“1”, in other words, it “inverts” (complements) its input signal. The output from a NOT
gate only returns “HIGH” again when its input is at logic level “0”
“If A is NOT true, then Q is true”

 AND GATE
The output state of a digital logic AND gate only returns “LOW” again when ANY of its
inputs are at a logic level “0”. In other words, for a logic AND gate, any LOW input will
give a LOW output.
“If both A and B are true, then Q is true”

 XOR GATE
The output of an Exclusive-OR gate ONLY goes “HIGH” when its two input terminals are at
“DIFFERENT” logic levels with respect to each other . An odd number of logic “1’s” on its
inputs gives a logic “1” at the output.
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Learning/ observation
NAND GATE’S TRUTH TABLE

NOR GATE’S TRUTH TABLE


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NOT GATE’S TRUTH TABLE

AND GATE’S TRUTH TABLE


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XOR GATE’S TRUTH TABLE

Troubleshooting

 PROBLEMS FACED  SOLUTION


 Connections may not be  Try to make connections
made properly as defined
 Power Supply may not  Take defined power
be appropriate supply
 Resistor may not be  Connect a resistor of
connected 330 ohms

RESULT:
Truth tables of the required gates is verified

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